Who’s Who

July 1st, 2022

Li Jiang

Assistant Professor

Shanghai Jiao Tong University

Email:

ljiang_cs@sjtu.edu.cn

Personal webpage

https://www.cs.sjtu.edu.cn/~jiangli/

Research interests

Compute-in-memory, Neuromorphic Computing, Domain Specific Architecture for AI, Database, networking etc.

Short bio

Li Jiang received the B.S. degree from the Dept. of CS&E, Shanghai Jiao Tong University in 2007, the MPhil, and the Ph.D. degree from the Dept. of CS&E, the Chinese University of Hong Kong in 2010 and 2013, respectively. He has published more than 80 peer-review papers in top-tier computer architecture, EDA and AI/Database conferences and journals, including ISCA, MICRO, DAC, ICCAD, AAAI, ICCV, SigIR, TC, TCAD, TPDS and etc. He received the Best Paper Award in DATE’22, Best Paper Nomination in ICCAD10, and DATE21. According to the IEEE Digital Library, five articles ranked in the top 5 of citations of all papers collected at its conferences. Some of the achievements have been introduced into the IEEE P1838 standard, and several technologies have been in commercial use in cooperation with TSMC, Huawei, and Alibaba.

He got the best Ph.D. Dissertation award in ATS 2014, and he was in the final list of TTTC’s E. J. McCluskey Doctoral Thesis Award. He received ACM Shanghai Rising Star award and CCF VLSI early career award in 2019. He received the 2nd class prize of Wu Wenjun Award for Artificial Intellegence. He serves as co-chair and TPC member in several international and national conferences, such as MICRO, DATE, ASP-DAC, ITC-Asia, ATS, CFTC, CTC, etc. He is an Associate Editor of IET Computers Digital Techniques, VLSI, the Integration Journal. He is the co-founder of ChinaDA and ACM/SigDA East China Branch.

Reasearch highlights

Prof. Li Jiang has been working on the test and repair architecture of 3D ICs that can dramatically reduce costs, advocating and emphasizing the precious resources sharing mechanism. They optimize the 3D SoC test architecture under test-pin count and thermal dissipation constraints by sharing the test-access-mechanism (TAM) and test wire of pre-bond wafer-level and post-bond package-level tests. They further propose the inter-die spare-sharing technique and the die-matching algorithms to improve the stack yield of 3D stacked memory. This work is nominated as the best paper in ICCAD 2010. Based on this method, they work with TSMC to propose a novel BISR architecture that can cluster and map faulty rows/columns across die to the same spare row/column to enhance the reparability. This series of works have been widely accepted by the mainstream and introduced into the IEEE P1838 standard.

To improve the assembly yield in the TSV fabrication process, they develop a fault model considering TSV coupling effect that has not been carefully investigated before. It leads their attention to a unique phenomenon, i.e., the faulty TSVs can be clustered. Thus, they propose a novel spare-TSV sharing architecture composed of a lightweight switch design, two effective and efficient repair algorithms, and a TSV-grid mapping mechanism that can avoid catastrophic TSV clustering defects.

ReRAM cell needs multiple programming pulses to avoid device programming variation and resistance drifting. To overcome the resulting programming latency and energy, they propose a Self-Terminating Write (STW) circuit that heavily reuses the inherent PIM peripherals (e.g., ADC and Trans-Impedance Amplifier) to obtain 2-bit precision via a single program pulse. This work is the best paper award of DATE 2022.

July 1st, 2022

Fan Chen

Assistant Professor

Indiana University Bloomington

Email:

fc7@iu.edu

Personal webpage

https://homes.luddy.indiana.edu/fc7/

Research interests

Beyond-CMOS Computing, Quantum Machine Learning, Accelerator Architecture for Emerging Applications, Emerging Nonvolatile Memory

Short bio

Fan Chen is an assistant professor in the Department of Intelligent Systems Engineering at the Indiana University Bloomington. Dr. Chen received her Ph.D. from the department of Electrical and Computer Engineering at Duke University. Dr. Chen is a recipient of the 2022 NSF Faculty Early Career Development Program (CAREER) Award, the 2021 Service Recognition Award of Great Lakes Symposium on VLSI (GLSVLSI), the 2019 Cadence Women in Technology Scholarship, the Best Paper Award and the Ph.D. forum Best Poster Award at 2018 Asia and South Pacific Design Automation Conference (ASP-DAC). Dr. Chen serves as the publication chair of ISLPED 2022/2021, chair of SIGDA University Booth at DAC 2022/2021, web and registration chair of GLSVLSI 2022, proceedings chair of ASAP 2021, arrangement chair of GLSVLSI 2021. Dr. Chen also serves on the editorial board of IEEE Circuits and Systems Magazine (CAS-M). She is a technical reviewer for over 30+ international conferences/journals, such as IEEE TC, IEEE TCAS-I, IEEE TNNLS, IEEE D&T, IEEE IoT-J, ACM TACO, ACM TODAES, ACM JETC, etc.

Reasearch highlights

Prof Chen’ research interests are focused on beyond-CMOS computing, quantum machine learning, accelerator architecture for emerging applications. Her latest work on quantum machine learning investigates fundamentally novel quantum equivalent of deep learning frameworks derived from the working principles of quantum computers, paving the way for general-purpose quantum algorithms on noisy intermediate-scale quantum devices. Another notable contribution of Prof. Chen’s work is accelerator architecture designs for emerging applications including deep learning and bioinformatics. The memory and computing requirements of such big-data applications pose significant technical challenges for their adoption in a broader range of services. Prof. Chen investigates how system/architecture/algorithm co-designed domain-specific accelerators can help on performance and energy efficiency. Prof. Chen’s works have been recognized by the academic community and appeared in top conferences, such as HPCA, DAC, ICCAD, DATE, ISLPED, ASP-DAC, and ESWEEK. Her research on “System Support for Scalable, Fast, and Power-Efficient Genome Sequencing” has been honored with the National Science Foundation Faculty Early Career Development CAREER Award.

May 1st, 2022

Kuan-Hsun Chen

Assistant Professor

University of Twente, the Netherlands

Email:

k.h.chen@utwente.nl

Personal webpage

https://people.utwente.nl/k.h.chen

Research interests

Real-Time Embedded Systems, Non-Volatile Memories, Architecture-Aware Software Design, Resource-Constrained Machine Learning

Short bio

Dr.-Ing. Kuan-Hsun Chen is an assistant professor at the Chair of Computer Architecture and Embedded Systems (CAES) for the University of Twente in the Netherlands. He earned his Ph.D. degree (05.2019) in Computer Science (Dr.-Ing.) from TU Dortmund University, Germany with distinction (summa cum laude), and his master’s degree in Computer Science at National Tsing Hua University in Taiwan. He has published more than 40 scientific works in top peer-reviewed journals and international conferences. His key research interests are in design for real-time embedded systems, non-volatile memories, architecture-aware software design, and resource-constrained machine learning. Dr. Chen currently serves as Associate Editor in the journal of AIMS Applied Computing and Intelligence (AIMS-ACI) and Guest Editor for the Journal of Signal Processing Systems (JSPS). He is also a Technical Program Committee (TPC) member for various leading international conferences in the computer science area like Real-Time Systems Symposium (RTSS), International Conference on High Performance Computing, Data, & Analytics (HiPC), and others. He is also a reviewer for many peer-reviewed journals and conferences (TC, TECS, TCPS, RTAS, IROS, ECML PKDD) in computer science. Dr. Chen holds one best student paper award at RTCSA’18, one best paper nomination at DATE’21, and one dissertation award at TU Dortmund University in 2019. He was granted by the German Academic Exchange Service (DAAD) one research project as Principal Investigator and one personal grant for postdoctoral exchange in Japan for the Summer of 2021. He is also a volunteer mentor in the European Space Agency (ESA) Summer of Code in Space (2017) and Google Summer of Code since 2016 for open-source development on a popular real-time operating system, namely RTEMS.

Reasearch highlights

Embedded systems in various safety-critical domains, such as computing systems in automotive and avionic devices, are important for modern society. Due to their intensive interaction with the physical environment, where time naturally progresses, the correctness of the system depends not only on the functional correctness of the delivered results but also on the timeliness of the instant at which these results are delivered. Dr. Chen’s research results cover a wide range of scientific issues in such areas, and two central-most research areas are as follows: Dependable Real-Time Systems: Along with technology shrinking, the presence of hardware faults is growing, which risks the correct system behavior. Against such faults, software tolerance techniques are prominent due to their flexibility. However, their time overhead also makes timeliness a pressing issue. Under this context, three kinds of treatments are studied: 1) In soft real-time systems, occasional deadline misses are acceptable. A series of analyses for the probability of deadline misses are developed. The most effective one is to efficiently derive safe upper bounds on the probability of deadline misses with several magnitude speed-up, in comparison to conventional convolution-based approaches (https://ieeexplore.ieee.org/abstract/document/7993392). 2) By modeling inherent safety margin in applications, soft errors can also be safely ignored in control applications. A runtime adaptive method is thus developed to only compensate when it is necessary while satisfying hard real-time constraints. This work was presented in LCTES’16 and published in ACM SIGPLAN (https://dl.acm.org/doi/abs/10.1145/2980930.2907952). 3) On multi-core systems, several approaches are developed to optimize the system reliability via the deployment of redundant multithreading. A reliability-driven task mapping technique is developed for homogeneous multi-core architectures with reliability and performance heterogeneity, which was published in IEEE Transactions on Computers (https://ieeexplore.ieee.org/abstract/document/7422036). Architecture-Aware Software Design: To unleash the scarce computational power on embedded systems, he focuses on how to exploit a given architecture, especially for data analysis applications, e.g., data mining and machine learning. He develops code generators to automate the optimization of the memory layouts for the tree-based inference model. Given a trained model, the optimized code sessions are generated in C++ to reduce cache misses for various CPU architectures and speed up the runtime. This work is recently published in ACM Transactions on Embedded Computing Systems (https://dl.acm.org/doi/abs/10.1145/3508019). He also works on the system design for non-volatile memories, which feature several advantages like low leakage power, high density, and low unit costs. However, they also impose novel technical constraints, especially limited endurance. His research results on software-based memory analyses, wear-leveling approaches, etc. One highlight is the exploration of energy-aware real-time scheduling for hybrid memory architectures. In this work, a multi-processor procrastination algorithm (HEART) is proposed, based on partitioned earliest-deadline-first (pEDF) scheduling, which facilitates reducing energy consumption by actively enlarging the hibernation time. This work was presented in EMSOFT’21 and published in ACM Transactions on Embedded Computing Systems (https://dl.acm.org/doi/abs/10.1145/3477019).

April 1st, 2022

Can Li

Assistant Professor

The University of Hong Kong

Email:

canl@hku.hk

Personal webpage

http://canlab.hku.hk

Research interests

Neuromorphic computing, nanoelectronics devices, non-volatile memories, software-hardware co-optimization

Short bio

Dr. Can Li is currently an Assistant Professor at the Department of Electrical and Electronic Engineering of the University of Hong Kong, working on analog and neuromorphic computing accelerators based on post-CMOS emerging devices (e.g. memristors), for efficient machine/deep learning, network security, signal processing, etc. Before that, He spent two years at Hewlett Packard Labs in Palo Alto, California, and obtained his Ph.D. from University of Massachusetts, Amherst, and B.S./M.S. from Peking University. He is a recipient of the Early Career Award by HKSAR RGC and the Excellent Young Scientist Fund Award by NSFC.

Reasearch highlights

Can Li has made contributions to the in-memory computing technology based on non-volatile memory devices. At the device level, he fabricated and characterized different resistive switching or memristive devices with different material stacks, including Cu/SiOx/Pt, Pt/SiOx/Pt, Si/SiOx/Si, Ta/HfOx/Pt, etc. The potential of this type of device was also demonstrated by Can Li and colleagues’ work on three-dimensional (3D) stacking and integration (up to eight layers), and ultimate scaling down to 2 nm×2 nm. At the array level, he integrated memristors (2 µm×2 µm and 50 nm×50 nm) with silicon transistors from commercial foundries and demonstrated high-yield and good analog programming ability. At the circuit level, he designed and developed analog circuits for analog content addressable memory in a 6-transistor 2-memristor (6T2M) configuration. Can Li was closely involved in designing, taping out, and evaluating peripheral circuits for matrix multiplication accelerators. At the systems level, he showcased the memristor-based system in potential applications such as artificial intelligence, analog signal/image processing, pattern matching, solving optimization problems, hardware security, etc. Those studies have been documented in many high-profile publications, including Nature Electronics, Nature Machine Intelligence, Nature Nanotechnology, Nature Communications, Advanced Materials, IEDM, etc.

April 1st, 2022

Johann Knechtel

Research Scientist

New York University Abu Dhabi, UAE

Email:

johann@nyu.edu

Personal webpage

https://wp.nyu.edu/johann/

Research interests

Hardware Security, Electronic Design Automation (EDA), 3D Integration, Emerging Technologies, Machine Learning

Short bio

Dr.-Ing. Johann Knechtel is a Research Scientist with the Design for Excellence Lab at New York University (NYU) Abu Dhabi, UAE. In this position, he is acting as Co-PI for multiple research projects and provides lecturing, training, and mentoring to PhD and undergraduate students. Johann received the Dipl.-Ing. degree (M.Sc.) in Information Systems Engineering in 2010 and the Dr.-Ing. degree (Ph.D.) in Computer Engineering (summa cum lauda, with highest honors) in 2014, both from TU Dresden (TUD), Germany. Before joining NYU Abu Dhabi in 2016, Johann was a Postdoctoral Researcher in 2015 at the Masdar Institute of Science and Technology, UAE, where he was affiliated with the Twinlab on “3D Stacked Chips”, hosted by Masdar Institute and TUD and supported by industry and government partners. In 2012 he was with the Chinese University of Hong Kong, China, and in 2010 he was with the University of Michigan, USA. In 2006, he was working as Freelance Software Engineer for Siemens IT Solutions and Services, Germany; in 2006–08 he was working as Research Assistant for Fraunhofer IWS Institute, Dresden, Germany; and in 2008–09 he was working as Embedded Systems Intern for TraceTronic GmbH, Dresden, Germany. In 2017, Johann and his team achieved the 1st place in the CSAW Applied Research Competition. Johann obtained scholarships from the German Academic Exchange Service (DAAD) in 2010, from the German Research Foundation (DFG) in 2010–14, and from the Graduate Academy of TU Dresden in 2014. Johann obtained an NYU Research Enhancement Fund in 2018–21. Johann has (co-)authored around 60 publications, including 15 highlighted and/or invited papers. Johann is an active member of the ACM, including ACM SIGDA, and IEEE. He is serving as peer reviewer for various top-tier ACM and IEEE conferences and journals.

Reasearch highlights

Johann is acting as Co-PI for multiple projects with the common goal of advancing hardware security. Johann’s work involves five PhD students and postdoctoral researchers at NYU Abu Dhabi and also covers collaborations with around 15 researchers and students at prestigious institutions worldwide. Johann’s work is currently focused on the following themes: 1. Security closure for physical design of integrated circuits (ICs); 2. Protection of IC design intellectual property, with advanced techniques proposed for split manufacturing and obfuscation utilizing interconnect fabrics as well as 2.5D and 3D integration; 3. Secure architectures and secure system integration based on chiplets and 2.5D integration; 4. Machine learning-driven security evaluation at design time of defense schemes like split manufacturing and logic locking; 5. Security evaluation of ICs and field-programmable gate arrays (FPGAs) using advanced electro-magnetic field and laser-assisted optical probing; 6. Design-time security evaluation of ICs against side-channel attacks; 7. Security promises and challenges of emerging technologies for various defense schemes; 8. Security-aware electronic design automation (EDA) flows for 2D, 2.5D, and 3D ICs. Johann has successfully published on these and other themes. Recent examples include two invited papers at ICCAD 2021 on security closure for physical design, two invited papers at ISPD 2020–21 on hardware security for and beyond CMOS devices, an invited paper at DATE 2020 on the role of EDA for secure composition of ICs, and invited papers at IOLTS and COINS 2019 on 3D integration as another dimension toward hardware security and on design IP protection, respectively. Furthermore, Johann and colleagues have recently compiled a book “The Next Era in Hardware Security: A Perspective on Emerging Technologies for Secure Electronics,” Springer, 2022, with already 1.7k full-text downloads as of today. Currently, Johann is acting as lead organizer for the first-ever international competition (co-hosted with ISPD 2022) on security closure. For that, research teams from all over the world are hardening the physical layouts of ICs at design time against selected attacks that are executed post-design time. This notion of security closure is quite complex, and besides the interest from the community with this contest and invited papers, Johann and colleagues are also in active discussion with government agencies on that challenge. Earlier, Johann and colleagues from TU Dresden, Germany, Google Inc., and Masdar Institute published a survey paper “Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration” in IPSJ Transactions on System LSI Design Methodology. Since its time of appearance in 2017, i.e., for five years already, this paper is constantly the most viewed article of that journal. In 2012, Johann published his first journal article in IEEE TCAD with colleagues from Michigan University, USA; at the time of appearance, this paper was the most popular article across all of that journal.

March 1st, 2022

Xiaoming Chen

Associate Professor

Institute of Computing Technology,

Chinese Academy of Sciences

Email:

chenxiaoming@ict.ac.cn

Personal webpage

http://people.ucas.edu.cn/~chenxm

Research interests

EDA and computer architecture

Short bio

Xiaoming Chen received the B.S. and Ph.D. degrees in Electronic Engineering from Tsinghua University, in 2009 and 2014, respectively. Since 2017, he has been an associate professor at Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS). Before joining ICT, CAS, he was a postdoctoral research associate in Electrical and Computer Engineering, Carnegie Mellon University from 2014 to 2016, and a visiting assistant professor in Computer Science and Engineering, University of Notre Dame from 2016 to 2017.

His research interests are mainly focused on EDA and computer architecture. He has published about 100 papers in top journals and conference proceedings, including DAC, ICCAD, DATE, HPCA, IEEE TCAD, IEEE TVLSI, IEEE TPDS, etc. He has served as a technical program committee member for DAC, ICCAD, ASP-DAC, GLSVLSI, AsianHOST, VLSI Design, etc. He was awarded the Excellent Young Scientists Fund of National Natural Science Foundation of China in 2021. He received the 2015 EDAA Outstanding Dissertation Award and the 2018 Alibaba DAMO Academy Young Fellow Award. He received one of the two best paper awards in ASP-DAC 2022 and several best paper nominations in ASP-DAC and ISLPED.

Reasearch highlights

Prof. Xiaoming Chen has spent more than 10 years in the EDA trarea. Specifically, he has developed a parallel sparse direct solver named NICSLU that is well suited for SPICE-based circuit simulators. He proposed a series of novel techniques to elevate the performance of solving highly sparse linear systems from circuit simulation applications, including a new matrix ordering method to minimize fill-ins, a hybrid dynamic scheduling method for parallel matrix factorization, a numerically stable pivoting reduction technique, and an adaptive numerical kernel selection method. NICSLU achieves much higher performance than other sparse solvers in circuit simulation applications, and is also generally faster than state-of-the-art GPU-based solvers which are specially designed for circuit matrices. NICSLU has been used in a number of academic studies, EDA tools and power system simulators. Some techniques have been adopted in commercial SPICE tools of a leading EDA company in China. NICSLU is available at https://github.com/chenxm1986/nicslu.

Prof. Chen has also made important contributions in computing-in-memory (CiM) architecture design. He exposed how to utilize the device-level CiM feature of resistive random-access memories (RRAMs) and ferroelectric field-effect transistors (FeFETs) which can act as both storage elements and switch units, to unify the computing and storage resources at the circuit level, to realize interchangeable computing and storage functionalities at the architecture level. In addition, he has investigated the solutions to some fundamental problems in CiM systems, including data coherence, data contention, simulation methodologies, task assignment, etc. He has also explored the CiM feature of RRAMs and FeFETs in various applications, and designed energy-efficient and high-performance accelerators for neural networks, graph processing, linear algebra, and robots.

January 1st, 2022

Kai Ni

Assistant Professor

Rochester Institute of Technology

Email:

kai.ni@rit.edu

Personal webpage

https://www.needskai.org/

Research interests

Emerging Devices for AI Accelerator, Emerging Devices for Unconventioanl Computing

Short bio

Kai Ni received the B.S. degree in Electrical Engineering from University of Science and Technology of China, Hefei, China in 2011, and Ph.D. degree of Electrical Engineering from Vanderbilt University, Nashville, TN, USA in 2016 by working on characterization, modeling, and reliability of III-V MOSFETs. Since then, he became a postdoctoral associate at University of Notre Dame, working on ferroelectric devices for nonvolatile memory and novel computing paradigms. He is now an assistant professor in Electrical & Microelectronic Engineering at Rochester Institute of Technology. He has around 100 publications in top journals and conference proceedings, including Nature Electronics, IEDM, VLSI Symposium, IRPS, EDL, etc. He has served as technical program committee for DAC, DATE, ASPDAC, IRPS, EDTM. His current interests lie in nanoelectronic devices empowering unconventional computing, domain-specific accelerator, and memory technology.

Reasearch highlights

Kai Ni has made important contributions to the development of ferroelectric HfO2 based field effect transistor (FeFET) and its technology applications. On the technology side, he has proposed the ferroelectric metal field effect transistor, which has a metal-ferroelectric-metal-oxide-semiconductor gate stack and has the freedom of optimizing the gate stack, and superlattice structure for multi-level cell. He has developed several models for FeFET explaining different behaviors of FeFET, including a compact model based on the Preisach model of ferroelectric, a Kinetic Monte Carlo model to explain device variation, and a comprehensive model which can capture all the key ferroelectric behaviors. With these models, he also explored the exciting applications of FeFET for in-memory computing. Examples include the crossbar array for matrix-vector multiplication, content addressable memory array for associative search, hardware security circuit, and reconfigurable computing. All these research activities have been published in top journals, and premier conferences, such as IEDM, VLSI Symposium, DAC, DATE, etc.

January 1st, 2022

Christophe Bobda

Professor

University of Florida

Email:

cbobda@ece.ufl.edu

Personal webpage

https://bobda.ece.ufl.edu/

Research interests

Reconfigurable Computing, FPGA, System on Chip Design, Embedded Imaging, Cybersecurity and Robotics

Short bio

Professor Bobda received the License in mathematics from the University of Yaounde, Cameroon, in 1992, the diploma of computer science and the Ph.D. degree in computer science from the University of Paderborn in Germany in 1999 and 2003 respectively. In June 2003 he joined the department of computer science at the University of Erlangen-Nuremberg in Germany as Post doc. Dr. Bobda received the best dissertation award 2003 from the University of Paderborn for his work on synthesis of reconfigurable systems using temporal partitioning and temporal placement. In 2005 Dr. Bobda was appointed assistant professor at the University of Kaiserslautern. There he set the chair for Self-Organizing Embedded Systems that he led until October 2007. From 2007 to 2010 Dr. Bobda was Professor at the University of Potsdam and leader of the working Group Computer Engineering. Upon moving to the US, Dr. Bobda was appointed Professor of computer engineering at the University of Arkansas where he founded the smart embedded systems lab (2010 – 2018). Since 2019, Dr. Boda has been with the University of Florida as Professor of Computer Engineering, leader of the lab smart systems and outreach director of the the Nelms Institute of Connected World.

Reasearch highlights

Professor Christophe Bobda’ research interests lie primarily in the design of smart embedded systems, with emphasis of run-time optimization. He investigates the design and run-time operation of high-performance and adaptive architectures with application in image processing, embedded optimization, security, and control. He recently introduced an event-based split-CNN architecture (ESCA) for running time-critical vision applications with comparatively less memory footprint while consuming low power. ESCA has a dedicated hardware architecture and scheduling of on-chip memory buffering using a split-CNN that reduces memory requirements by splitting the feature maps into small patches and independently executes them. This work received the best short paper of award at FCCM2021. His previous work of “DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices” is nominated among the 23 most significant FPL papers of the last 25 years. His research enables a new paradigm to design adaptive architectures for various applications.

January 1st, 2022

Dayane Alfenas Reis

Postdoctoral Researcher

Notre Dame University

Email:

Dayane.A.Reis.11@nd.edu

Personal webpage

https://sites.google.com/nd.edu/dreis

Research interests

VLSI design, Beyond-CMOS devices, In-memory computing architectures for data-centric applications, Hardware-software codesign, Secure computing

Short bio

Dr. Dayane Reis received her Ph.D. in Computer Science and Engineering from the University of Notre Dame in 2021, where she works as a Postdoctoral Researcher in the Hardware-Software Co-design Lab, under the direction of Dr. Xiaobo Sharon Hu and Dr. Michael Niemier. She also received the MSc. in Electrical Engineering from the Federal University of Minas Gerais, Brazil, in 2016, and the BSc. in Electronic Engineering from the Pontifical Catholic University of Minas Gerais, Brazil, in 2012. Dr. Reis’s research exploit the unique characteristics of beyond CMOS technologies for the design of fast, energy efficient and reliable in-memory computing kernels that can be used in a wide range of data-intensive application scenarios. She is the author of more than 20 articles in journals such as IEEE TVLSI, IEEE TCAD, IEEE Design, and Test, Nature Electronics, as well as renowned conferences including ISLPED, ASP-DAC, ICCAD and DATE. Dr. Reis was one of the two winners of the best paper award at the ACM/IEEE International Symposium on Electronics and Low Power Design in 2018 (ISLPED’18) for her paper “Computing in memory with FeFETs”, and a recipient of the Cadence Women in Technology (WIT) Scholarship 2018/2019, in recognition to her personal history and efforts toward the inclusion of women in STEM fields.

Reasearch highlights

Dr. Dayane Reis’s research investigates the impact of emerging technologies on the design of circuits and architectures for data-centric computing. Furthermore, her research also exploits non-von Neumann architectures – such as those based on the concept of in-memory computing (IMC) – to alleviate the impact of data transfers on a system’s overall performance and energy consumption. She designed the first IMC architecture based on Ferroelectric Field Effect Transistors (FeFETs) for general-purpose computing-in-memory. For this work, she won the Best Paper Award at the ISLPED. Furthermore, she designed a variety of hardware accelerators based on different IMC kernels (i.e., general-purpose computing-in-memory arrays, ternary content addressable memory arrays, etc.) for hardware-software codesign of meta-learning models and cryptography algorithms such as the Advanced Encrypted Standard (AES), and the Brakerski/Fan-Vercauteren scheme for homomorphic encryption. Dr. Reis also participated in the development of a uniform framework for benchmarking IMC architectures based on CMOS and emerging technologies. The framework allows researchers to assess the benefits of analog and digital IMC based on different devices for data-intensive tasks in the domain of machine learning and have wide applicability. Finally, together with collaborators at Purdue University, Dr. Reis proposed and evaluated polymorphic gates based on Black Phosphorus Field-Effect Transistors (BP-FETs) that operate with low voltage supply (up to 0.2V) and are resistant to power supply variations. Such hardware security primitives can be employed in logic obfuscation, having great utility for intellectual property protection.

January 1st, 2022

Pi-Cheng Hsiu

Research Fellow

Academia Sinica

Email:

pchsiu@citi.sinica.edu.tw

Personal webpage

https://www.citi.sinica.edu.tw/~pchsiu

Research interests

Embedded Software and Intermittent Computing

Short bio

Dr. Pi-Cheng Hsiu received the Ph.D. degree in computer science and information engineering from National Taiwan University in 2009. He is currently a Research Fellow (Professor) and the Deputy Director of the Research Center for Information Technology Innovation (CITI), where he leads the Embedded and Mobile Computing Laboratory, and is also a Joint Research Fellow with the Institute of Information Science, Academia Sinica, Taiwan, a Jointly Appointed Professor with the Department of Computer Science and Engineering, National Chi Nan University, and a Jointly Appointed Professor with the College of Electrical Engineering and Computer Science, National Taiwan University. He was a Visiting Scholar with the Department of Computer Science, University of Illinois at Urbana-Champaign, in 2007 and with the Department of Electrical and Computer Engineering, University of Pittsburgh, in 2019. 

Dr. Hsiu constantly publishes papers at the premier venues in embedded systems, real-time systems, and design automation. His works were respectively nominated for the Best Paper Awards at IEEE/ACM CODES+ISSS 2019, 2020, and 2021, of which the last two received the Best Paper Awards in a row. He is a recipient of the 2019 Young Scholars’ Creativity Award of the Foundation for the Advancement of Outstanding Scholarship, the 2019 Exploration Research Award of the Pan Wen Yuan Foundation, and the 2015 Scientific Paper Award of the Y. Z. Hsu Science and Technology Memorial Foundation. He serves as an Associate Editor of the ACM Transactions on Cyber-Physical Systems, Track Co-Chairs of IEEE/ACM ISLPED and ACM SAC, and in the Technical Program Committees of major conferences in his field, including RTSS, RTAS, CODES+ISSS and DAC.

Reasearch highlights

Dr. Hsiu’s research goal is to realize Intermittent Artificial of Things (iAIoT), enabling battery-less IoT devices to intermittently execute deep neural networks (DNN) via ambient power. iAIoT is a novel research direction at the intersection of intermittent computing and deep learning, and once realized, would create innovative applications.

He has led a research team to release a suite of system runtime and libraries, facilitating AI and IoT application developers to easily build low cost, intermittent-aware inference systems. In particular, an intermittent operating system (TCAD’20), which was the first attempt to allow multitasking and task concurrency on intermittent systems, makes complicated intermittent applications increasingly possible. The HAWAII middleware (TCAD’20), which comprises an inference engine and API library, enables hardware accelerated intermittent DNN inference. In addition, the iNAS framework (TECS’21) was the first framework that introduces intermittent execution behavior into neural architecture search to automatically find intermittently-executable DNN models. HAWAII and iNAS received the Best Paper Awards, respectively, for two years in a row at IEEE/ACM CODES+ISSS 2020 and 2021. Such recognition indicates the innovativeness of his research and contributions to the community.