Who’s Who

January 1st, 2022

Dayane Alfenas Reis

Assistant professor

Department of Computer Science and Engineering, University of South Florida

Email:

dayane3@usf.edu

Personal webpage

https://sites.google.com/view/dayane-reis/home

Research interests

VLSI design, Beyond-CMOS devices, In-memory computing architectures for data-centric applications, Hardware-software codesign, Secure computing

Short bio

Dr. Dayane Reis received her Ph.D. in Computer Science and Engineering from the University of Notre Dame in 2021, where she works as a Postdoctoral Researcher in the Hardware-Software Co-design Lab, under the direction of Dr. Xiaobo Sharon Hu and Dr. Michael Niemier. She also received the MSc. in Electrical Engineering from the Federal University of Minas Gerais, Brazil, in 2016, and the BSc. in Electronic Engineering from the Pontifical Catholic University of Minas Gerais, Brazil, in 2012. Dr. Reis’s research exploit the unique characteristics of beyond CMOS technologies for the design of fast, energy efficient and reliable in-memory computing kernels that can be used in a wide range of data-intensive application scenarios. She is the author of more than 20 articles in journals such as IEEE TVLSI, IEEE TCAD, IEEE Design, and Test, Nature Electronics, as well as renowned conferences including ISLPED, ASP-DAC, ICCAD and DATE. Dr. Reis was one of the two winners of the best paper award at the ACM/IEEE International Symposium on Electronics and Low Power Design in 2018 (ISLPED’18) for her paper “Computing in memory with FeFETs”, and a recipient of the Cadence Women in Technology (WIT) Scholarship 2018/2019, in recognition to her personal history and efforts toward the inclusion of women in STEM fields.

Reasearch highlights

Dr. Dayane Reis’s research investigates the impact of emerging technologies on the design of circuits and architectures for data-centric computing. Furthermore, her research also exploits non-von Neumann architectures – such as those based on the concept of in-memory computing (IMC) – to alleviate the impact of data transfers on a system’s overall performance and energy consumption. She designed the first IMC architecture based on Ferroelectric Field Effect Transistors (FeFETs) for general-purpose computing-in-memory. For this work, she won the Best Paper Award at the ISLPED. Furthermore, she designed a variety of hardware accelerators based on different IMC kernels (i.e., general-purpose computing-in-memory arrays, ternary content addressable memory arrays, etc.) for hardware-software codesign of meta-learning models and cryptography algorithms such as the Advanced Encrypted Standard (AES), and the Brakerski/Fan-Vercauteren scheme for homomorphic encryption. Dr. Reis also participated in the development of a uniform framework for benchmarking IMC architectures based on CMOS and emerging technologies. The framework allows researchers to assess the benefits of analog and digital IMC based on different devices for data-intensive tasks in the domain of machine learning and have wide applicability. Finally, together with collaborators at Purdue University, Dr. Reis proposed and evaluated polymorphic gates based on Black Phosphorus Field-Effect Transistors (BP-FETs) that operate with low voltage supply (up to 0.2V) and are resistant to power supply variations. Such hardware security primitives can be employed in logic obfuscation, having great utility for intellectual property protection.

January 1st, 2022

Pi-Cheng Hsiu

Research Fellow (Professor)

Academia Sinica

Email:

pchsiu@citi.sinica.edu.tw

Personal webpage

https://homepage.citi.sinica.edu.tw/pages/pchsiu/

Research interests

Embedded Software and Intermittent Computing

Short bio

Dr. Pi-Cheng Hsiu received the Ph.D. degree in computer science and information engineering from National Taiwan University in 2009. He is currently a Research Fellow (Professor) and the Deputy Director of the Research Center for Information Technology Innovation (CITI), where he leads the Embedded and Mobile Computing Laboratory, and is also a Joint Research Fellow with the Institute of Information Science, Academia Sinica, Taiwan, a Jointly Appointed Professor with the Department of Computer Science and Engineering, National Chi Nan University, and a Jointly Appointed Professor with the College of Electrical Engineering and Computer Science, National Taiwan University. He was a Visiting Scholar with the Department of Computer Science, University of Illinois at Urbana-Champaign, in 2007 and with the Department of Electrical and Computer Engineering, University of Pittsburgh, in 2019. 

Dr. Hsiu constantly publishes papers at the premier venues in embedded systems, real-time systems, and design automation. His works were respectively nominated for the Best Paper Awards at IEEE/ACM CODES+ISSS 2019, 2020, and 2021, of which the last two received the Best Paper Awards in a row. He is a recipient of the 2019 Young Scholars’ Creativity Award of the Foundation for the Advancement of Outstanding Scholarship, the 2019 Exploration Research Award of the Pan Wen Yuan Foundation, and the 2015 Scientific Paper Award of the Y. Z. Hsu Science and Technology Memorial Foundation. He serves as an Associate Editor of the ACM Transactions on Cyber-Physical Systems, Track Co-Chairs of IEEE/ACM ISLPED and ACM SAC, and in the Technical Program Committees of major conferences in his field, including RTSS, RTAS, CODES+ISSS and DAC.

Reasearch highlights

Dr. Hsiu’s research goal is to realize Intermittent Artificial of Things (iAIoT), enabling battery-less IoT devices to intermittently execute deep neural networks (DNN) via ambient power. iAIoT is a novel research direction at the intersection of intermittent computing and deep learning, and once realized, would create innovative applications.

He has led a research team to release a suite of system runtime and libraries, facilitating AI and IoT application developers to easily build low cost, intermittent-aware inference systems. In particular, an intermittent operating system (TCAD’20), which was the first attempt to allow multitasking and task concurrency on intermittent systems, makes complicated intermittent applications increasingly possible. The HAWAII middleware (TCAD’20), which comprises an inference engine and API library, enables hardware accelerated intermittent DNN inference. In addition, the iNAS framework (TECS’21) was the first framework that introduces intermittent execution behavior into neural architecture search to automatically find intermittently-executable DNN models. HAWAII and iNAS received the Best Paper Awards, respectively, for two years in a row at IEEE/ACM CODES+ISSS 2020 and 2021. Such recognition indicates the innovativeness of his research and contributions to the community.

Oct 2021

Yuan-Hao Chang

Research Fellow

Academia Sinica, Taiwan

Email:

johnson@iis.sinica.edu.tw

Personal webpage

http://www.iis.sinica.edu.tw/~johnson/

Research interests

Design automation, Non-volatile Memory, Memory/Storage Systems, Operating Systems, Real-time Systems, Embedded Systems, Computer Systems

Short bio

Yuan-Hao received his Ph.D. in Computer Science from the Department of Computer Science and Information Engineering at National Taiwan University, Taipei, Taiwan. He is currently a Deputy Director and Research Fellow (Professor) of Institute of Information Science (IIS), Academia Sinica, and is also a Jointly Appointed Professor of College of Electrical Engineering and Computer Science, National Taiwan University (NTU), Taipei, Taiwan. Yuan-Hao has published more than 100 research papers, which were mainly published in top journals (including 50+ in premier ACM/IEEE Transactions, e.g., IEEE TC, IEEE TCAD, IEEE TVLSI, ACM TECS, ACM TODAES, and ACM TOS) and top conferences (including 50+ in USENIX OSDI, ACM/IEEE DAC, ACM/IEEE ICCAD, ACM/IEEE ISLPED, ACM/IEEE CODES+ISSS, ACM/IEEE EMSOFT, ACM/IEEE CASES, IEEE RTSS, and IEEE RTAS). His work received 2 best paper awards from top conferences (including ACM/IEEE ISLPED 2020 and ACM/IEEE CODES+ISSS 2019), 4 best paper nominations from top conferences (including ACM/IEEE DAC 2016, ACM/IEEE DAC 2014, ACM/IEEE CODES+ISSS 2014, and ACM/IEEE DAC 2007), 2 best paper awards from important conferences (including IEEE NVMSA 2019 and IEEE IMW 2018), and 1 best paper nomination from important conference ACM/IEEE ASP-DAC 2016. He has also been granted for dozens of US and Taiwan patents.

Yuan-Hao is an associate editor of IEEE Transactions on Emerging Topics in Computing (TETC), ACM Transactions on Storage (TOS), and ACM Transactions on Cyber-Physical Systems (TCPS). He is currently an executive committee member of ACM Special Interest Group on Design Automation (SIGDA) and ACM Special Interest Group on Embedded Systems (SIGBED). He is a steering committee member of IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA). In addition, He served as a program co-chair and a general co-chair of IEEE NVMSA 2017 and 2018 respectively, and a local co-chair of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) 2017. He has also served as a program committee member for many top international conferences (e.g., ACM/IEEE DAC, ACM/IEEE DAC ICCAD, ACM/IEEE ISLPED, IEEE RTSS, IEEE RTAS, ACM/IEEE CODES+ISSS, and IEEE ICDCS).

Reasearch highlights

Yuan-Hao’s most significant contribution lies in the development of design methodologies for reliability enhancement of flash-memory storage systems with performance consideration. He was one of the pioneers to show the importance of wear leveling. He introduced the concept of static wear leveling and provided insights on how to improve the lifetime of flash-memory storage systems in the popular flash management designs. This work was nominated by DAC’07 for the best paper award and technically transferred to companies. His work on low-cost flash-memory products proposed the innovative ideas of “disposable flash memory” and provided solutions (e.g., committing information to resolve the ECC problem) to the software design of highly unreliable flash-memory products. By taking vertical integration into consideration, he further developed a file-system-aware flash management design to optimize the performance of flash storage devices. This is one of the first works to vertically integrate host information with device information. The current open-channel SSDs and zone namespace SSDs also follow the idea of vertically integration. The series of his research works has been the groundwork for developing highly reliable and efficient flash-memory storage systems, and has been adopted and validated on real products.

Another distinctive contribution of Yuan-Hao’s work is on developing HW/SW co-design methodologies to enhance reliability of non-volatile memory (NVM). Yuan-Hao was one of the pioneers to enhance the reliability/endurance of NVM through co-design methodologies. He proposed the concept of “one-memory” with a joint management method to resolve the lifetime issue of NVM. This work received best paper nomination from CODES+ISSS’14. Yuan-Hao further proposed the a constant-cost wear leveling design and provided insights on how to achieve wear-leveling with nearly-zero search cost; this work was one of the first to develop wear-leveling techniques for NVM-based main-memory systems. The series of his research works has been the groundwork to enable NVM as main-memory. Yuan-Hao also worked on developing co-design methodologies to resolve the reliability issue of 3D flash-memory chips. His work on 3D flash-memory was an early work to resolve the disturbance issue of 3D flash-memory. This work proposed a co-design solution with the concept of “virtual block” to reduce the disturbed bit errors with its extended design nominated by DAC’14 for the best paper award. His co-design works for 3D flash-memory have been adopted/validated on real 3D flash-memory chips.

December 1st, 2021

Yi-Chung Chen

Associate Professor

Tennessee State University

Email:

ychen@tnstate.edu

Personal webpage

https://yichungchen84.github.io/

Research interests

Application-specific system, 3-D integration, Heat simulation, NVM, Data pipeline, Deep learning

Short bio

Yi Chung Chen is currently an Assistant Professor in the Department of Electrical and Computer Engineering, Tennessee State University. He received the Ph.D. degree from Electrical and Computer Engineering, University of Pittsburgh, USA in 2014, and the M.S. degree in Electrical and Computer Engineering from New York University, New York in 2011. He has served as TPC member in many conference committees. He has served as committee member of regional and national STEM education committees for silicon and digital system education of underrepresented minorities. He has also served as organizing and technical program committee members of conferences.

Reasearch highlights

Prof. Chen’s has published interdisciplinary papers in the major research fields across computing systems and applications. His research contribution lies in vertical integration of EDA tools for design of application-specific computer system. He investigates data-driven intelligent systems for adaptive, resilient, and expandable operations demanded by critical missions. His research projects are supported by the US AF, the US ARMY, ASEE, and NSF. In addition, Prof. Chen is an acting committee member of semiconductor research and education working group for minority serving institutions. He is on a mission to prepare future semiconductor workforce of underrepresented groups in engineering by building education and research capacity with opensource EDA tools.

December 1st, 2021

Hussam Amrouch

Professor

University of Stuttgart, Germany

Email:

amrouch@iti.uni-stuttgart.de

Personal webpage

https://www.iti.uni-stuttgart.de/en/institute/team/Amrouch/

Research interests

Beyond-CMOS, Beyond von-Neumann Architectures, Neuromorphic Computing, Semiconductor Physics, Machine Learing for CAD

Short bio

Hussam Amrouch is a Jun.-Professor heading the Chair of Semiconductor Test and Reliability (STAR) in the Computer Science, Electrical Engineering Faculty at the University of Stuttgart, Germany as well as he is a Research Group Leader at the Karlsruhe Institute of Technology (KIT), Germany. He earned in 06.2015 his Ph.D. degree in Computer Science (Dr.-Ing.) from KIT with the highest distinction (summa cum laude), which has an acceptance ratio of less than 10% at KIT. After which he had founded the “Dependable Hardware” research group at KIT, which he is still leading until now. In 07.2020, He was appointed at the University of Stuttgart, computer science department, as a Junior Professor leading the research efforts in the area of machine learning for CAD with a special focus on design for testing and reliability for advanced and emerging nanotechnologies.

Reasearch highlights

Prof. Amrouch has published more than 140 multidisciplinary publications (including 55 journals) in the major research areas across the computing stack (semiconductor physics, circuit design, computer-aided design, and computer architecture). His key research interests are focused on beyond-CMOS technologies, emerging memories, and beyond-von Neumann architectures with a special focus on In-Memory Computing, Neuromorphic Computing and AI applications. He received eight times a HiPEAC Paper Award. He also received three Best Paper Award Nominations for his work in reliability; two of them from the Design Automation Conference (DAC’17, DAC’16) and one from the Design, Automation and Test in Europe Conference (DATE’17). He has 10 tutorials and 24 invited talks (including 2 keynotes) in several top international conferences (e.g., DAC, DATE, etc.), universities and companies. He has also organized 9 special sessions in top CAD conferences. He currently serves as Review Editor at the Frontiers in Electronics and Associate Editor Integration, the VLSI Journal. He serves also as Technical Program Committee (TPC) member for many top international conferences in the computer science area like Design Automation Conference (DAC). He is also a reviewer in many top journals in different research fields starting from the system level (e.g., IEEE Transactions on Computers TC) to the circuit level (e.g., IEEE Transactions on Circuits and Systems TCAS-I) all the way down to semiconductor physics (e.g., IEEE Transactions on Electron Devices TED).

December 1st, 2021

Bei Yu

Associate Professor

Chinese University of Hong Kong

Email:

byu@cse.cuhk.edu.hk

Personal webpage

http://www.cse.cuhk.edu.hk/~byu/index.html

Research interests

Physical Design, Mask Optimization, Design Space Exploration, Deep Learning

Short bio

Prof. Bei Yu is currently an Associate Professor in the Department of Computer Science and Engineering, The Chinese University of Hong Kong. He received the Ph.D degree from Electrical and Computer Engineering, University of Texas at Austin, USA in 2014, and the M.S. degree in Computer Science from Tsinghua University, China in 2010. He has served as TPC Chair of ACM/IEEE Workshop on Machine Learning for CAD, and in many journal editorial boards and conference committees. He is Editor of the IEEE TCCPS Newsletter.

Prof. Yu has published more than 200 research papers, mainly in top journals (including 39 IEEE TCAD) and top conferences (including 22 DAC and 29 ICCAD) in the VLSI CAD area. He published the most papers of DAC 2019 (7 papers) and ICCAD 2021 (9 papers) among all scholars around the world. He received seven Best Paper Awards from ASPDAC 2021, ICTAI 2019, Integration, the VLSI Journal in 2018, ISPD 2017, SPIE Advanced Lithography Conference 2016, ICCAD 2013, ASPDAC 2012 and five other Best Paper Award Nominations (DATE 2021, ASPDAC 2019, DAC 2014, ASPDAC 2013, and ICCAD 2011). He also received six awards in ICCAD/ISPD contest awards.

Reasearch highlights

As one of the pioneers, Prof. Yu’s research contribution lies in machine learning for EDA, which is to remarkably improve circuit design efficiency with the aid of machine learning techniques. He investigates generative adversarial network models GAN-OPC (DAC’18, TCAD’20) and DAMO (ICCAD’20, TCAD’21) to improve mask optimization quality and efficiency and even outperform state-of-the-art commercial tool. He is pioneer for new class of research about graph learning and point cloud embedding for EDA. For instance, he proposes graph neural network based learning on netlist-level, and investigates how graph learning model can help on testability, reliability, and manufacturability analysis (published on DAC’19, DAC’20, and TCAD’21). He is the first researcher exploiting deep point cloud embedding concept in VLSI physical design field to construct a routing tree (best paper award at ASPDAC’21). In addition, he proposes active learning (equipped with Gaussian process and neural process) as an advanced learning paradigm for design space exploration in EDA (published on TCAD’19 and TCAD’21).

Another distinctive contribution of Prof. Yu’s work is EDA for deep learning system. The resource consumption of the deep learning models is a major concern regarding the broad deployment on resource-constrained hardware. Prof. Yu investigates a unified approximation framework to compress and accelerate the deep learning models, where the low-rankness and structured sparsity are incorporated for model pruning. This work received the best student paper award from ICTAI’2019. He also proposes to optimize the HLS and TVM deployment strategies of DNN models on FPGA and GPU, cooperated with a set of advanced learning and optimization methodologies (published on 2x DATE’2021, 2x ICCAD’21 and ICCV’21). These methodologies facilitate DNN deployment on resource-constrained hardware with high efficiency and performance.