Who’s Dayane Alfenas Reis
January 1st, 2022
VLSI design, Beyond-CMOS devices, In-memory computing architectures for data-centric applications, Hardware-software codesign, Secure computing
Dr. Dayane Reis received her Ph.D. in Computer Science and Engineering from the University of Notre Dame in 2021, where she works as a Postdoctoral Researcher in the Hardware-Software Co-design Lab, under the direction of Dr. Xiaobo Sharon Hu and Dr. Michael Niemier. She also received the MSc. in Electrical Engineering from the Federal University of Minas Gerais, Brazil, in 2016, and the BSc. in Electronic Engineering from the Pontifical Catholic University of Minas Gerais, Brazil, in 2012. Dr. Reis’s research exploit the unique characteristics of beyond CMOS technologies for the design of fast, energy efficient and reliable in-memory computing kernels that can be used in a wide range of data-intensive application scenarios. She is the author of more than 20 articles in journals such as IEEE TVLSI, IEEE TCAD, IEEE Design, and Test, Nature Electronics, as well as renowned conferences including ISLPED, ASP-DAC, ICCAD and DATE. Dr. Reis was one of the two winners of the best paper award at the ACM/IEEE International Symposium on Electronics and Low Power Design in 2018 (ISLPED’18) for her paper “Computing in memory with FeFETs”, and a recipient of the Cadence Women in Technology (WIT) Scholarship 2018/2019, in recognition to her personal history and efforts toward the inclusion of women in STEM fields.
Dr. Dayane Reis’s research investigates the impact of emerging technologies on the design of circuits and architectures for data-centric computing. Furthermore, her research also exploits non-von Neumann architectures – such as those based on the concept of in-memory computing (IMC) – to alleviate the impact of data transfers on a system’s overall performance and energy consumption. She designed the first IMC architecture based on Ferroelectric Field Effect Transistors (FeFETs) for general-purpose computing-in-memory. For this work, she won the Best Paper Award at the ISLPED. Furthermore, she designed a variety of hardware accelerators based on different IMC kernels (i.e., general-purpose computing-in-memory arrays, ternary content addressable memory arrays, etc.) for hardware-software codesign of meta-learning models and cryptography algorithms such as the Advanced Encrypted Standard (AES), and the Brakerski/Fan-Vercauteren scheme for homomorphic encryption. Dr. Reis also participated in the development of a uniform framework for benchmarking IMC architectures based on CMOS and emerging technologies. The framework allows researchers to assess the benefits of analog and digital IMC based on different devices for data-intensive tasks in the domain of machine learning and have wide applicability. Finally, together with collaborators at Purdue University, Dr. Reis proposed and evaluated polymorphic gates based on Black Phosphorus Field-Effect Transistors (BP-FETs) that operate with low voltage supply (up to 0.2V) and are resistant to power supply variations. Such hardware security primitives can be employed in logic obfuscation, having great utility for intellectual property protection.