Who’s Who

Jan 2024

Jianlie Yang

Associate Professor

Beihang University

Email:

jianlie@buaa.edu.cn

Personal webpage

https://shi.buaa.edu.cn/jianlei/zh_CN/index.htm

Research interests

EDA, Systems and Architectures for AI/DL

Short bio

Prof. Jianlei Yang received the B.S. degree in microelectronics from Xidian University, Xi’an, China, in 2009, and the Ph.D. degree in computer science and technology from Tsinghua University, Beijing, China, in 2014. He is currently an Associate Professor in Beihang University, Beijing, China, with the School of Computer Science and Engineering. From 2014 to 2016, he was a post-doctoral researcher with the Department of ECE, University of Pittsburgh, Pennsylvania, USA. Prof. Jianlei Yang was the recipient of the First/Second place on ACM TAU Power Grid Simulation Contest in 2011/2012. He was a recipient of IEEE ICCD Best Paper Award in 2013, ACM GLSVLSI Best Paper Nomination in 2015, IEEE ICESS Best Paper Award in 2017, ACM SIGKDD Best Student Paper Award in 2020.

Research highlights

His research contributions primarily encompass large-scale integrated circuit simulation and analysis algorithms, emerging memory design and computation paradigms, as well as software-hardware co-design for machine learning and graph learning applications.

• In the field of large-scale circuit simulation solvers, he has tackled the pressing need for efficient and rapid solutions for power integrity analysis in high-performance processor chip designs. His FPS-PCG and AMG-PCG algorithms have significantly enhanced the convergence of power grid solvers [ICCAD’2011/TVLSI’2014]. These accomplishments were acknowledged with honors, including first place in the 2011 TAU Power Grid Simulation Contest and second place in the 2012 TAU Power Grid Transient Simulation Contest. Furthermore, his proposed selective inverse-based vectorless verification techniques have notably improved the efficiency of large-scale vectorless verification of power supply networks [ICCD’2013/TVLSI’2015], earning him the IEEE ICCD Best Paper Award in 2013.
• In the realm of emerging memory design and computation paradigms, he has confronted the power consumption challenges of integrated circuits in the Post-Moore’s Law era. His systematic research has resulted in the development of reliability analysis methods for spin-based memory devices and circuits, establishing theoretical foundations and solutions for non-volatile memory reliability verification [TCAD’2016]. Additionally, his work on spin-based reconfigurable logic has tackled efficiency and reliability challenges in circuit obfuscation methods within the field of chip security [TCAD’2019]. By leveraging the inherent random flipping characteristics of spin devices, he has introduced spin-based random computing circuits for Bayesian inference computation systems, significantly enhancing inference efficiency [ASPDAC’2018/TCAD’2020]. Moreover, his innovative spin-based in-memory computing architecture has addressed data access bottlenecks in graph computing, resulting in substantial improvements in graph computation efficiency [DAC’2020].
• In the domain of software-hardware co-design, he has delved into domain-specific custom computing architectures as a means to enhance computational efficiency. His proposed dataflow optimization techniques involve deeply customizing the dataflow execution patterns of neural network models to augment hardware-friendly characteristics [TC’2022]. He pioneered the early introduction of the dynamic gradient sparsification method to accelerate deep neural network training, in conjunction with specified architecture support for algorithm-hardware co-design [ECCV’2020/DAC’2020]. Furthermore, his dataflow customization methods and dedicated architectures for large-scale visual point cloud processing have mitigated memory access bottlenecks, resulting in substantial enhancements in the speed and energy efficiency of visual computing tasks [DAC’2019/DAC’2022].

July 2023

Jianli Chen

Professor

State Key Laboratory of ASIC and System,
Fudan University

Email:

chenjianli@fudan.edu.cn

Personal webpage

https://sme.fudan.edu.cn/5f/c6/c31141a352198/page.htm

Research interests

Algorithms for VLSI Physical Design

Short bio

Jianli Chen is currently a professor at the State Key Laboratory of ASIC and System, Fudan University. He received the B.Sc. degree in information and computing sciences, the M.Sc. degree in computer application technology, and the Ph.D. degree in applied mathematics, all from Fuzhou University, in 2007, 2009, and 2012, respectively. His research interests include optimization theory and applications, and optimization methods for VLSI physical design automation.

Dr. Chen has received two Best Paper Awards from the International Forum on Operations Research and Control Theory in 2011 and the Design Automation Conference (DAC) in 2017, three Best Paper Award candidates from DAC, and two Best Paper Award candidates from the International Conference on Computer-Aided Design (ICCAD). He and his group were the recipient of the First Place Award at the CAD Contest at ICCAD in 2017, 2018 and 2019, respectively. Dr. Chen has also received multiple government honors and industry awards, such as the Integrated Circuit Early Career Award from China Computer Federation in 2018, the Youth Science Award for Applied Mathematics from China Society for Industrial and Applied Mathematics in 2020, the First Prize of Shanghai Technology Invention Award in 2020, the Special Prize for Excellent Project Award from Shanghai Industry-University-Institute Cooperation in 2021, the First Prize of the Natural Science Award from the Ministry of Education in 2022. He has served as a design automation technical committee of IEEE Council on Electronic Design Automation (CEDA) since January 2018. He is the founder of LEDA Technology, Shanghai, China.

Research highlights

1. Proposed an analytical approach to deal with the NP-hard problem of VLSI mixed-cell-height legalization. The paper ‘Toward Optimal Legalization for Mixed-cell-height Circuit Designs,’ based on this achievement, won the DAC 2017 Best Paper Award.
2. Led the research team to win three champions at the CAD Contest at ICCAD from 2017 to 2019, the 2^nd place in ICCAD’20, the 3rd place in ICCAD’21, and the 1^st place in ISPD Contest 2023. Furthermore, the team’s achievements have become an integral part of the core technology used in LEDA’s products.
3. Developed placement engine, which is capable of efficiently processing tens of millions of cells. This innovation has significantly contributed to the advancement of integrated circuit placement algorithms and has been incorporated into the IEEE CEDA Reference Design Flow (RDF) since 2019.

April 2023

Scott Beamer

Assistant Professor

Department of Computer Science & Engineering, University of California, Santa Cruz

Email:

sbeamer@ucsc.edu

Personal webpage:

https://scottbeamer.net

Research interests

Agile and open-source hardware design, computer architecture, graph processing, and data movement optimization

Short bio

Scott Beamer is an assistant professor of computer science and engineering at the University of California, Santa Cruz. His research interests include agile hardware design, high-performance graph processing, and computer architecture. He has received an NSF CAREER award, the Kaivalya Dixit Distinguished Dissertation Award from SPEC, and best paper awards from the International Parallel & Distributed Processing Symposium (IPDPS) and the International Symposium on Workload Characterization (IISWC). He has a PhD in Computer Science from the University of California, Berkeley, and was formerly a postdoctoral scholar at Lawrence Berkeley National Laboratory.

Research highlights

(1) Accelerating RTL Simulation
Simulation is a crucial tool for hardware design, but the current slow speed of RTL simulation often bottlenecks the whole design process. Dr. Beamer’s work explores techniques to drastically accelerate simulation speed while providing the same cycle-accurate result. These results are released as the open-source ESSENT simulator, which demonstrates both leading single-threaded [DAC20] and parallel [ASPLOS23] performance.
(2) High-Performance Graph Processing
The versatility of the graph abstraction allows it to represent many things from hardware circuits to social networks. Unfortunately, graph applications typically underutilize existing general-purpose compute resources. Dr. Beamer’s work has accelerated graph processing through a variety of means. Algorithmically, he created the direction-optimizing breadth-first search (BFS) algorithm, which is the fastest BFS for low-diameter graphs [SC12] and it is widely used in the Graph500 competition. He carefully analyzed graph workloads with performance counters [IISWC15], and created the GAP benchmark suite which has been used by over 250 publications. His propagation blocking work transforms graph algorithms to increase their spatial locality [IPDPS17].
(3) Monolithically-Integrated Silicon Photonics
Due to the limits of electrical signalling, off-chip bandwidth can be greatly hindered by area or power constraints. Monolithically-integrated silicon photonics provide an amazing opportunity to overcome such limitations for inter-chip communication. Collaborating with device experts, Dr. Beamer designed architectures to best utilize photonics, for CPU to DRAM [ISCA10] and within a single chip [NOCS09].
(4) Agile & Open-Source Hardware Design
With the slowing of Dennard scaling and the corresponding rise in the need for hardware specialization, there is also a corresponding need to reduce the cost and complexity of hardware design. Agile techniques provide a promising way to increase productivity, and Dr. Beamer has created a course on Agile Hardware Design and released all of the content as open source (https://github.com/agile-hw). Releasing tools and hardware designs as open-source can greatly help the community, and Dr. Beamer was an early contributor to the RISC-V project and one of the first users of the Chisel hardware construction language.

March 2023

Ming-Chang Yang

Associate Professor

Department of Computer Science and Engineering, The Chinese University of Hong Kong

Email:

mcyang@cse.cuhk.edu.hk

Personal webpage:

http://www.cse.cuhk.edu.hk/~mcyang/

Research interests

Emerging non-volatile memory and storage technologies, memory and storage systems, and the next-generation memory/storage architecture designs.

Short bio

Ming-Chang Yang is currently an Assistant Professor at the Department of Computer Science and Engineering, The Chinese University of Hong Kong. He received his B.S. degree from the Department of Computer Science at National Chiao-Tung University, Hsinchu, Taiwan, in 2010. He received his Master and Ph.D. degrees (supervised by Professor Tei-Wei Kuo) from the Department of Computer Science and Information Engineering at National Taiwan University, Taipei, Taiwan, in 2012 and 2016, respectively. His primary research interests include emerging non-volatile memory and storage technologies, memory and storage systems, and the next-generation memory/storage architecture designs.

Dr. Yang has published more than 70 research papers, which were mainly published in top journals (e.g., IEEE TC, IEEE TCAD, IEEE TVLSI, and ACM TECS) and top conferences (e.g., USENIX OSDI, USENIX FAST, USENIX ATC, ACM/IEEE DAC, ACM/IEEE ICCAD, ACM/IEEE CODES+ISSS, and ACM/IEEE EMSOFT). He received two best paper awards (from IEEE NVMSA 2019 and ACM/IEEE ISLPED 2020) for his research contributions on emerging non-volatile memory; also, he was awarded TSIA Ph.D. Student Semiconductor Award from Taiwan Semiconductor Industry Association (TSIA) in 2016 because of his research achievements on flash memory.

Research highlights

The main research interest of Dr. Yang’s research group is in embracing emerging memory/storage technologies, including various types of non-volatile memory (NVM) as well as the shingled magnetic recording (SMR) and interlaced magnetic recording (IMR) technologies for the next-generation hard disk drive (HDD), in computer systems.

Particularly, in view of the common read-write asymmetry (in both latency and energy) of NVM, one series of Dr. Yang’s research work attempts to alleviate the side effects caused by such asymmetry via innovating the application and/or algorithm designs. For example, one of their most recent research studies devises a novel dynamic hashing scheme for NVM called SEPH, which exhibits excellent performance scalability, efficiency, and predictability on the real product of NVM (i.e., Intel® Optane™ DCPMM). Also, Dr. Yang’s research group revamps the algorithmic design of random forest, one core algorithm of machine learning (ML), for NVM. This line of study receives particular attention and recognition from the community, including winning two best paper awards from NVMSA 2019 and ISLPED 2020. Moreover, Dr. Yang’s research group is also the pioneer in exploring the memory subsystem design based on an emerging type of NVM called racetrack memory (RTM).

On the other hand, even though the cutting-edge SMR and IMR technologies bring lower cost-per-GB to HDD, they also impose the write amplification problem on HDD, resulting in severe write performance degradation. In light of this, Dr. Yang’s research group introduces a couple of novel data management designs into different system layers for SMR-based or IMR-based HDD. For example, they architect KVIMR, a data management middleware for constructing a cost-effective yet high-throughput LSM-tree based KV store on IMR-based HDD. KVIMR exhibits significant throughput improvement and even excellent compatibility with the mainstream LSM-tree based KV stores (such as RocksDB and LevelDB). In addition, at the block layer, they put forward a novel design called Virtual Persistent Cache (VPC) that adaptively exploits the computing and management resources from the host system to ultimately improve the write responsiveness of SMR-based HDD. Moreover, they realize a firmware design called MAGIC, which shows great potential to close the performance gap between traditional and IMR-based HDDs.

Apart from the system work on adapting emerging memory/storage technologies, Dr. Yang’s research group is also of special interest to data-intensive or data-driven applications. For instance, they aim to optimize the efficiency and practicality of out-of-core graph processing systems, which feature offloading the enormous graph data from memory into storage for better scalability at a low cost. Also, they develop new frameworks for graph representation learning and graph neural networks with significant performance improvements.

February 2023

Wang Ying

Associate Professor

Institute of Computing Technology, Chinese Academy of Sciences.

Email:

wangying2009@ict.ac.cn

Personal webpage

https://wangying-ict.github.io/

Research interests

Domain-Specific chips, processor architecture and design automation

Short bio

Ying Wang is an associate professor in Institute of Computing Technology, Chinese Academy of Sciences. Wang’s research expertise is focused on VLSI testing, reliability and the design automation of domain-specific processors such as accelerators for computer vision, deep learning, graph computing and robotics. His group has conducted pioneering work in the open-source frameworks for automated neural network accelerator generation and customization. He has published more than 30 papers at DAC, and over 120 papers on other IEEE/ACM conferences and journals. He holds over 30 patents related to chip design. Wang is also a co-founder of Jeejio Tech in Beijing, which is granted the Special Start-up Award of the year 2018 by Chinese Academy of Sciences. Among Wang’s honors, it also includes the Young Talent Development Program Awardee from Chinese Association of Science and Technology (as one of the two awardees of computer science in 2016), 2017 CCF Intel outstanding researcher award, 2019 Early Career Award from Chinese Computer Federation and etc. He is the recipient of Under 40 Innovator award of DAC at 2021. Dr. Wang has also received several awards from international conferences, including the winner of System Design Contest at DAC 2018 and IEEE rebooting LPIRC 2016, the Best Paper Award at ITC-Asia 2018, GLSVLSI2021 (2nd place), ICCD 2019, and the best paper of 2011 IEEE Transaction on Computers, as well as the best paper nominee in ASPDAC.

Research highlights

Dr. Wang’s innovative research in the DeepBurning project has significantly contributed to one of the viable approaches toward automatic specialized accelerator generation and is considered one of the representative works in this area, which is to start from the software framework to directly generate a specialized circuit design implemented on FPGA or ASICs. After the initial project of DeepBurning1.0, he continues to pioneer several on-going works including ELNA (DAC2017), Dadu (DAC2018), 3D-Cube (DAC2019), DeepBurning-GL (ICCAD2020) and DeepBurning-Seg (Micro-2022), which also follows the same technical route of automatic hardware accelerator generation but has been extended to different applications and architectures. Also, the DeepBurning series not only develops horizontally to different areas, but also vertically go to the high level processor design stacks including early-stage design parameter exploration, ISA extension and compiler-hardware co-design. In general, his holistic work on this field has attracted considerable attention from different Chinese EDA companies. Based on the agile chip customization technology initiated by Dr. Wang, his company, Jeejio, is able to develop highly-customized chip solutions at a relatively low cost, and help its customers stay competitive in the niche IoT markets. Dr. Wang’s team has proposed the RISC-V compatible Sage architecture that can be used to customize AIoT SoC solution with user-redeemable computing power, for audio/video/image processing capability and also automotive scenarios.

January 2023

Heba Abunahla

Assistant Professor

Quantum and Computer Engineering department, TU Delft, Netherlands.

Email:

Heba.nadhmi@gmail.com

Research interests

• Emerging RRAM devices
• Smart sensors
• Hardware security
• Graphene-based electronics
• CNTs-based electronics
• Neuromorphic computing

Short bio

Heba Abunahla is currently Assistant Professor at the Quantum and Computer Engineering department, Delft University of Technology. Abunahla received the BSc, MSc and PhD degrees (with honors) from United Arab Emirates University, University of Sharjah and Khalifa University, respectively, via competitive scholarship. Prior to joining TU Delft as an Assistant Professor, Abunahla spent over five years as Postdoctoral Fellow and Research Scientist working extensively on the design, fabrication and characterization of emerging memory devices with great emphasis on computing, sensing and security applications.

Abunahla owns two patents, has published one book, and has co-authored over 30 conference and journal papers. In 2017. Abunahla had a collaborative project with University of Adelaide, Australia, on developing novel non-enzymatic glucose sensor. According to her achievements, she received Australian Global Talent Permanent Residency in 2021. Moreover, Abunahla’s innovation of deploying emerging RRAM devices in neuromorphic computing has been selected by Nature-Scientific Reports to be among Top 100 in materials Science. Also, her recent achievement in fabricating RRAM-based tunable filters was selected to be published in the first issue of Innovation@UAE Magazine launched by Ministry of Education.

Abunahla has several awards and competitive scholarships. E.g., she is the recipient of Unique Fellowship for Top Female Academic Scientists – Electrical Engineering, Mathematics & Computer Science (2022) from Delft University of Technology. Abunahla serves as a lead Editor in Frontiers in Neuroscience. She is an active reviewer for several high impact journals and conferences.

Research highlights

Secure intelligent memory and sensors are crucial components in our daily electronic devices and systems. CMOS has been the core technology to provide such requirements for decades. However, the limitations associated to power and area have led to the need for an alternative technology, called Resistive-RAM (RRAM). RRAM devices are able to perform memory and computation in the same cell, which enables in-memory computation feature. Moreover, RRAM can be deployed as a smart sensor due to its ability to change its I-V characteristic against the surrounding environment. Inherit stochasticity in RRAM junctions is also a great asset for security applications.

Abunahla has built a strong expertise in the field of micro-electronics design, modeling, fabrication, and characterization of high-performance and high-density memory devices. Abunahla developed novel RRAM devices that have been uniquely deployed in sensing, computing, security, and communication applications. For instance, Abunahla demonstrated a novel approach to measuring glucose levels for an adult human, and demonstrated the ability to fabricate such biosensor using a simple, low-cost standard photolithography process. In contrast to other sensors, the developed sensor has the ability to accurately measure glucose levels at neutral pH conditions (i.e. pH=7). Abunahla filed a US patent for this device and all the details of the innovation are published by the prestigious Nature Scientific Reports. This work has great commercialization opportunity; being unique and cutting edge in nature, and Abunahla is currently working with her team toward providing lab-on-chip sensing approach based on this technology.

Furthermore, Abunahla has recently innovated flexible memory devices, namely NeuroMem, that can mimic the memorization behavior of the brain. This unique feature makes NeuroMem a potential candidate for emerging in-memory-computing applications. This work is the first to report on the great potential of this technology for Artificial Intelligence (AI) inference for edge devices. Abunahla filed a US patent for this innovation and published the work in the prestigious Nature Scientific Reports. Further, her innovative research in using nanoscale devices for Gamma-ray sensing using Sol-gel/drop-coated micro-think nanomaterials is very unique and has been filed as US patent and published by the prestigious Journal of Materials Chemistry and Physics. Moreover, Abunahla has fabricated novel RRAM-based tunable filters which prove the possibility of tuning RF devices without any localized surface mount device (SMD) element or complex realization technique. In the field of hardware security, Abunahla developed an efficient flexible RRAM-based true random number generation, named SecureMem. The data generated by SecureMem prototype passed all NIST tests without any post-processing or hardware overhead.

December, 2022

Aman Arora

Graduate Fellow

The University of Texas at Austin

Email:

aman.kbm@utexas.edu

Personal webpage

https://amanarora.site

Research interests

Reconfigurable computing, Domain-specific acceleration, Hardware for Machine Learning

Short bio

Aman Arora is a Graduate Fellow and Ph.D. Candidate in the Department of Electrical and Computer Engineering at the University of Texas at Austin. His research vision is to minimize the gap between ASICs and FPGAs in terms of performance and efficiency, and to minimize the gap between CPUs/GPUs and FPGAs in terms of programmability. He imagines a future where FPGAs are first-class citizens in the world of computing and first-choice for accelerating new workloads. His PhD dissertation research focuses on the search for efficient reconfigurable fabrics for Deep Learning (DL) by proposing new DL-optimized blocks for FPGAs. His research has resulted in 11 paper publications in top conferences and journals in the field of reconfigurable computing and computer architecture and design. His work received a Best Paper Award at the IEEE FCCM conference in 2022, and he currently holds a fellowship from the UT Austin Graduate School. His research has been funded by the NSF. Aman has served as a secondary reviewer in top conferences like ACM FPGA (in 2021 and 2022). He is also the leader of the AI+FPGA committee at Open-Source FPGA (OSFPGA) Foundation, where he leads research efforts and organizes training webinars. He has 12 years of experience in the semiconductor industry in design, verification, testing and architecture roles. Most recently, he worked in the GPU Deep Learning architecture team at NVIDIA.

Research highlights

Aman’s past and current research focusses on architecting efficient reconfigurable acceleration substrates (or fabrics) for Deep Learning (DL). With Moore’s law slowing down, the requirements of resource-hungry applications like DL growing & changing rapidly, and climate change already knocking at our doors, this research theme has never been more relevant and important.

Aman has proposed changing the architecture of FPGAs to make them better DL accelerators. He proposed replacing a portion of the FPGA’s programmable logic area with new blocks called Tensor Slices, which are specialized for performing matrix operations like matrix-matrix multiplication and matrix-vector multiplication that are common in DL workloads. The FPGA industry has parallelly developed similar blocks like Intel AI Tensor Block and Achronix Machine Learning Processor.

In addition, Aman proposed adding compute capabilities to the on-chip memory blocks on FPGAs, so they can operate on data without having to move the data to compute units on the FPGA. He was the first to exploit the dual port nature of FPGA BRAMs to design these blocks instead of using technologies that significantly impact the circuitry of the RAM array and degrade its performance. He calls these new blocks CoMeFa RAMs. This work won the Best Paper Award at IEEE FCCM 2022.

Aman also led a team effort spanning three universities – UT Austin, University of Toronto, and University of New Brunswick – to develop an open-source DL benchmark suite called Koios. These benchmarks can be used to perform FPGA architecture and CAD research, and are integrated into VTR, which is the most popular open-source FPGA CAD flow.

Other research projects Aman has worked on or is working on include: (1) developing a parallel reconfigurable spatial acceleration fabric consisting of PIM (Processing-In-Memory) blocks connected using an FPGA-like interconnect, (2) implementing efficient accelerators for Weightless Neural Networks (WNNs) on FPGAs, (3) enabling support for open-source tools in FPGA research tools like COFFE, and (4) using Machine Learning (ML) to perform cross-prediction of power consumption on FPGAs and developing an open-source dataset that can be widely used for such prediction problems.

Aman hopes to start and direct a research lab at a university soon. His future research will straddle the entire stack of computer engineering: programmability at the top, architecture exploration in the middle, and hardware design at the bottom. The research thrusts he plans to focus on are next-gen reconfigurable fabrics, ML and FPGA related tooling, enabling the creation of an FPGA app store, and sustainable acceleration.

Nov 1st, 2022

Xun Jiao

Assistant Professor

Villanova University

Email:

xun.jiao@villanova.edu

Personal webpage

https://vu-detail.github.io/people/jiao

Research interests

Robust Computing, Efficient Computing, AI/Machine Learning, Brain-inspired Computing, Fuzz Testing

Short bio

Xun Jiao is an assistant professor in ECE department of Villanova University. He leads the Dependable, Efficient, and Intelligent Computing Lab (DETAIL). Before that, he obtained his Ph.D. degree from UC San Diego in 2018. He earned a dual first-class Bachelor degree from Joint Program of Queen Mary University of London and Beijing University of Posts and Telecommunications in 2013. His research interests are on robust and efficient computing for intelligent applications such as AI and machine learning. He published 50+ papers in international conferences and journals. He received 6 paper awards/nominations in international conferences such as DATE, EMSOFT, DSD, and SELSE. He is an associate editor of IEEE Trans on CAD, and a TPC member of DAC, ICCAD, ASP-DAC, GLSVLSI, LCTES. His research is sponsored by NSF, NIH, L3Harris, and Nvidia. He has delivered an invited presentation at U.S. Congressional House. He is a recipient of 2022 IEEE Young Engineer of the Year Award (Philadelphia Section).

Research highlights

Robust computing
• With continuous scaling of CMOS technology, circuits are even more susceptible to timing errors caused by microelectronic variations such as voltage and temperature variations, making them a notable threat to circuit/system reliability. Dr. Jiao has adopted a cross-layer approach (circuit-architecture-application) to combat errors/faults originated in hardware. Specifically, Dr. Jiao has pioneered in developing machine learning-based models to model/predict the errors in hardware and take proactive actions such as instruction-based frequency scaling to prevent errors. By exploiting the application-level error resilience of different applications (e.g., AI/machine learning, multimedia), Dr. Jiao has also developed various approximate computing techniques for more efficient execution.

Energy-efficient computing
• Energy efficiency has become a top priority for both high-performance computing systems and resource-constrained embedded systems. Dr. Jiao proposed solutions to this challenge at multiple abstraction levels. He proposed intelligent dynamic voltage and frequency scaling (DVFS) for circuits and systems, as well as designing novel efficient architecture such as in-memory computing and bloom filter to execute emerging workloads such as deep neural networks.

AI/brain-inspired computing
• Hyperdimensional computing (HDC) was introduced as an alternative computational model mimicking the “human brain” at the functionality level. Compared with DNNs, the advantages of HDC include smaller model size, less computation cost, and one/few-shot learning, making it a promising alternative computing paradigm. Dr. Jiao’s work has been pioneering the robustness of HDC against adversarial attacks and hardware errors, which has earned him a best paper nomination at DATE 2022. He also applied HDC to various application domains such as natural language processing, drug discovery, and anomaly detection, which demonstrated promising performance compared to traditional learning methods.

Fuzzing-based secure system
• Cyber-security in the digital age is a first-class concern. The ever-increasing use of digital devices, unfortunately, is facing significant challenges, due to the serious effects of security vulnerabilities. Dr. Jiao has developed a series of vulnerability detection techniques based on fuzzing, and has applied to software, firmware, and hardware. Over 100 previously unknown vulnerabilities are discovered and are reported to the US National Vulnerability Database with unique CVE assignments. He received two best paper nominations from EMSOFT 2019 and 2020.

Sep 1st, 2022

Tsung-Wei Huang

Assistant Professor

University of Utah

Email:

tsung-wei.huang@utah.edu

Personal webpage

https://tsung-wei-huang.github.io/

Research interests

Design automation and high-performance computing.

Short bio

Dr. Tsung-Wei Huang received his B.S. and M.S. degrees from the Department of Computer Science at Taiwan’s National Cheng-Kung University in 2010 and 2011, respectively. He then received his Ph.D. degree from the Department of Electrical and Computer Engineering (ECE) at the University of Illinois at Urbana-Champaign (UIUC) in 2017. He has been researching on high-performance computing systems with application focus on design automation algorithms and machine learning kernels. He has created several open-source software, such as Taskflow and OpenTimer, that are being used by many people. Dr. Huang receives several awards for his research contributions, including ACM SIGDA Outstanding PhD Dissertation Award in 2019, NSF CAREER Award in 2022, Humboldt Research Fellowship Award in 2022. He also received the 2022 ACM SIGDA Service Award for recognizing his community service that engaged students in design automation research.

Research highlights

(1) Parallel Programming Environment: Modern scientific computing relies on a heterogeneous mix of computational patterns, domain algorithms, and specialized hardware to achieve key scientific milestones that go beyond traditional capabilities. However, programming these applications often requires complex expert-level tools and a deep understanding of parallel decomposition methodologies. Our research investigates new programming environments to assist researchers and developers to tackle the implementation complexities of high-performance parallel and heterogeneous programs.

(2) Electronic Design Automation (EDA): The ever-increasing design complexity in VLSI implementation has far exceeded what many existing EDA tools can scale with reasonable design time and effort. A key fundamental challenge is that EDA must incorporate new parallel paradigms comprising manycore CPUs and GPUs to achieve transformational performance and productivity milestones. Our research investigates new computing methods to advance the current state-of-the-art by assisting everyone to efficiently tackle the challenges of designing, implementing, and deploying parallel EDA algorithms on heterogeneous nodes.

(3) Machine Learning Systems: Machine learning has become centric to a wide range of today’s applications, such as recommendation systems and natural language processing. Due to the unique performance characteristics, GPUs are increasingly used for machine learning applications and can dramatically accelerate neural network training and inference. Modern GPUs are fast and are equipped with new programming models and scheduling runtimes that can bring significant yet largely untapped performance benefits to many machine learning applications. Our research investigates novel parallel algorithms and frameworks to accelerate machine learning system kernels with order-of-magnitude performance breakthrough.

Aug 1st, 2022

Mohsen Imani

Assistant Professor

Department of Computer Science,
University of California Irvine

Email:

m.imani@uci.edu

Personal webpage

https://www.ics.uci.edu/~mohseni/

Research interests

Brain-Inspired Computing, Computer Architecture, Embedded Systems

Short bio

Mohsen Imani is an Assistant Professor in the Department of Computer Science at UC Irvine. He is also a director of Bio-Inspired Architecture and Systems Laboratory (BIASLab). He is working on a wide range of practical problems in the area of brain-inspired computing, machine learning, computer architecture, and embedded systems. His research goal is to design real-time, robust, and programmable computing platforms that can natively support a wide range of learning and cognitive tasks on edge devices. Dr. Imani received his Ph.D. from the Department of Computer Science and Engineering at UC San Diego. He has a stellar record of publication with over 120 papers in top conferences/journals. His contribution has led to a new direction in brain-inspired hyperdimensional computing that enables ultra-efficient and real-time learning and cognitive support. His research was also the main initiative in opening up multiple industrial and governmental research programs. Dr. Imani’s research has been recognized with several awards, including the Bernard and Sophia Gordon Engineering Leadership Award, the Outstanding Researcher Award, and the Powell Fellowship Award. He also received the Best Doctorate Research from UCSD, the best paper award in Design Automation and Test in Europe (DATE) in 2022, and several best paper nomination awards at multiple top conferences including Design Automation Conference (DAC) in 2019 and 2020, Design Automation and Test in Europe (DATE) in 2020, and International Conference on Computer-Aided Design (ICCAD) in 2020.

Reasearch highlights

Dr. Imani’s research has been instrumental in developing practical implementations of Hyper-dimensional (HD) computing – a computational technique modeled after the brain. The Hyper-dimensional computing system enabled large-scale learning in real-time, including both training and inference. He has developed such a system by not only accelerating machine learning algorithms in hardware but also redesigning the algorithms themselves using strategies that more closely model the ultimate efficient learning machine: the human brain. HD computing is motivated by the observation that the key aspects of human memory, perception, and cognition can be explained by the mathematical properties of high-dimensional spaces. It thereby models the human memory using points of a high-dimensional space, that is, with hypervectors (tens of thousand dimensions.) These points can be manipulated under a formal algebra to represent semantic relationships between objects, and thus we can devise various cognitive solutions which memorize and learn from the relation of data. HD computing also mimics several desirable properties of the human brain including robustness to noise and failure of memory cells, and one-shot learning which does not require a gradient-based algorithm. Dr. Imani exploited these key principles of brain functionalities to create cognitive platforms. The platforms include (1) novel HD algorithms supporting classification and clustering which represent the most popular categories of algorithms used regularly by professional data scientists, (2) novel HD hardware accelerators capable of up to three orders of magnitude improvement in energy efficiency relative to GPU implementations, and (3) an integrated software infrastructure that makes it easy for users to integrate HD computing as a part of systems, and that enables secure distributed learning on encrypted information using HD computing. The software contributions are backed by efficient hardware acceleration in GPU, FPGA, and processing in-memory. Dr. Imani leveraged the memory-centric nature of HD computing to develop efficient hardware/software infrastructure for a highly-parallel PIM acceleration. In HD computing, hypervectors have holographic distribution, where the information is uniformly distributed over a large number of dimensions. This makes HD computing significantly robust to the failure of an individual memory component (Robust to ∼30% failure in the hardware). In particular, Dr. Imani exploited this robustness to design an approximate in-memory associative search that checks the similarity of hypervectors in about tens of nano-seconds, while providing orders of magnitude improvement in energy efficiency as compared to today’s exact processors.