Who’s Scott Beamer
Department of Computer Science & Engineering, University of California, Santa Cruz
Agile and open-source hardware design, computer architecture, graph processing, and data movement optimization
Scott Beamer is an assistant professor of computer science and engineering at the University of California, Santa Cruz. His research interests include agile hardware design, high-performance graph processing, and computer architecture. He has received an NSF CAREER award, the Kaivalya Dixit Distinguished Dissertation Award from SPEC, and best paper awards from the International Parallel & Distributed Processing Symposium (IPDPS) and the International Symposium on Workload Characterization (IISWC). He has a PhD in Computer Science from the University of California, Berkeley, and was formerly a postdoctoral scholar at Lawrence Berkeley National Laboratory.
(1) Accelerating RTL Simulation
Simulation is a crucial tool for hardware design, but the current slow speed of RTL simulation often bottlenecks the whole design process. Dr. Beamer’s work explores techniques to drastically accelerate simulation speed while providing the same cycle-accurate result. These results are released as the open-source ESSENT simulator, which demonstrates both leading single-threaded [DAC20] and parallel [ASPLOS23] performance.
(2) High-Performance Graph Processing
The versatility of the graph abstraction allows it to represent many things from hardware circuits to social networks. Unfortunately, graph applications typically underutilize existing general-purpose compute resources. Dr. Beamer’s work has accelerated graph processing through a variety of means. Algorithmically, he created the direction-optimizing breadth-first search (BFS) algorithm, which is the fastest BFS for low-diameter graphs [SC12] and it is widely used in the Graph500 competition. He carefully analyzed graph workloads with performance counters [IISWC15], and created the GAP benchmark suite which has been used by over 250 publications. His propagation blocking work transforms graph algorithms to increase their spatial locality [IPDPS17].
(3) Monolithically-Integrated Silicon Photonics
Due to the limits of electrical signalling, off-chip bandwidth can be greatly hindered by area or power constraints. Monolithically-integrated silicon photonics provide an amazing opportunity to overcome such limitations for inter-chip communication. Collaborating with device experts, Dr. Beamer designed architectures to best utilize photonics, for CPU to DRAM [ISCA10] and within a single chip [NOCS09].
(4) Agile & Open-Source Hardware Design
With the slowing of Dennard scaling and the corresponding rise in the need for hardware specialization, there is also a corresponding need to reduce the cost and complexity of hardware design. Agile techniques provide a promising way to increase productivity, and Dr. Beamer has created a course on Agile Hardware Design and released all of the content as open source (https://github.com/agile-hw). Releasing tools and hardware designs as open-source can greatly help the community, and Dr. Beamer was an early contributor to the RISC-V project and one of the first users of the Chisel hardware construction language.