Jan 2024

Jianlie Yang

Associate Professor

Beihang University

Email:

jianlie@buaa.edu.cn

Personal webpage

https://shi.buaa.edu.cn/jianlei/zh_CN/index.htm

Research interests

EDA, Systems and Architectures for AI/DL

Short bio

Prof. Jianlei Yang received the B.S. degree in microelectronics from Xidian University, Xi’an, China, in 2009, and the Ph.D. degree in computer science and technology from Tsinghua University, Beijing, China, in 2014. He is currently an Associate Professor in Beihang University, Beijing, China, with the School of Computer Science and Engineering. From 2014 to 2016, he was a post-doctoral researcher with the Department of ECE, University of Pittsburgh, Pennsylvania, USA. Prof. Jianlei Yang was the recipient of the First/Second place on ACM TAU Power Grid Simulation Contest in 2011/2012. He was a recipient of IEEE ICCD Best Paper Award in 2013, ACM GLSVLSI Best Paper Nomination in 2015, IEEE ICESS Best Paper Award in 2017, ACM SIGKDD Best Student Paper Award in 2020.

Research highlights

His research contributions primarily encompass large-scale integrated circuit simulation and analysis algorithms, emerging memory design and computation paradigms, as well as software-hardware co-design for machine learning and graph learning applications.

• In the field of large-scale circuit simulation solvers, he has tackled the pressing need for efficient and rapid solutions for power integrity analysis in high-performance processor chip designs. His FPS-PCG and AMG-PCG algorithms have significantly enhanced the convergence of power grid solvers [ICCAD’2011/TVLSI’2014]. These accomplishments were acknowledged with honors, including first place in the 2011 TAU Power Grid Simulation Contest and second place in the 2012 TAU Power Grid Transient Simulation Contest. Furthermore, his proposed selective inverse-based vectorless verification techniques have notably improved the efficiency of large-scale vectorless verification of power supply networks [ICCD’2013/TVLSI’2015], earning him the IEEE ICCD Best Paper Award in 2013.
• In the realm of emerging memory design and computation paradigms, he has confronted the power consumption challenges of integrated circuits in the Post-Moore’s Law era. His systematic research has resulted in the development of reliability analysis methods for spin-based memory devices and circuits, establishing theoretical foundations and solutions for non-volatile memory reliability verification [TCAD’2016]. Additionally, his work on spin-based reconfigurable logic has tackled efficiency and reliability challenges in circuit obfuscation methods within the field of chip security [TCAD’2019]. By leveraging the inherent random flipping characteristics of spin devices, he has introduced spin-based random computing circuits for Bayesian inference computation systems, significantly enhancing inference efficiency [ASPDAC’2018/TCAD’2020]. Moreover, his innovative spin-based in-memory computing architecture has addressed data access bottlenecks in graph computing, resulting in substantial improvements in graph computation efficiency [DAC’2020].
• In the domain of software-hardware co-design, he has delved into domain-specific custom computing architectures as a means to enhance computational efficiency. His proposed dataflow optimization techniques involve deeply customizing the dataflow execution patterns of neural network models to augment hardware-friendly characteristics [TC’2022]. He pioneered the early introduction of the dynamic gradient sparsification method to accelerate deep neural network training, in conjunction with specified architecture support for algorithm-hardware co-design [ECCV’2020/DAC’2020]. Furthermore, his dataflow customization methods and dedicated architectures for large-scale visual point cloud processing have mitigated memory access bottlenecks, resulting in substantial enhancements in the speed and energy efficiency of visual computing tasks [DAC’2019/DAC’2022].