Who’s Bei Yu

December 1st, 2021

Bei Yu

Associate Professor

Chinese University of Hong Kong

Email:

byu@cse.cuhk.edu.hk

Personal webpage

http://www.cse.cuhk.edu.hk/~byu/index.html

Research interests

Physical Design, Mask Optimization, Design Space Exploration, Deep Learning

Short bio

Prof. Bei Yu is currently an Associate Professor in the Department of Computer Science and Engineering, The Chinese University of Hong Kong. He received the Ph.D degree from Electrical and Computer Engineering, University of Texas at Austin, USA in 2014, and the M.S. degree in Computer Science from Tsinghua University, China in 2010. He has served as TPC Chair of ACM/IEEE Workshop on Machine Learning for CAD, and in many journal editorial boards and conference committees. He is Editor of the IEEE TCCPS Newsletter.

Prof. Yu has published more than 200 research papers, mainly in top journals (including 39 IEEE TCAD) and top conferences (including 22 DAC and 29 ICCAD) in the VLSI CAD area. He published the most papers of DAC 2019 (7 papers) and ICCAD 2021 (9 papers) among all scholars around the world. He received seven Best Paper Awards from ASPDAC 2021, ICTAI 2019, Integration, the VLSI Journal in 2018, ISPD 2017, SPIE Advanced Lithography Conference 2016, ICCAD 2013, ASPDAC 2012 and five other Best Paper Award Nominations (DATE 2021, ASPDAC 2019, DAC 2014, ASPDAC 2013, and ICCAD 2011). He also received six awards in ICCAD/ISPD contest awards.

Reasearch highlights

As one of the pioneers, Prof. Yu’s research contribution lies in machine learning for EDA, which is to remarkably improve circuit design efficiency with the aid of machine learning techniques. He investigates generative adversarial network models GAN-OPC (DAC’18, TCAD’20) and DAMO (ICCAD’20, TCAD’21) to improve mask optimization quality and efficiency and even outperform state-of-the-art commercial tool. He is pioneer for new class of research about graph learning and point cloud embedding for EDA. For instance, he proposes graph neural network based learning on netlist-level, and investigates how graph learning model can help on testability, reliability, and manufacturability analysis (published on DAC’19, DAC’20, and TCAD’21). He is the first researcher exploiting deep point cloud embedding concept in VLSI physical design field to construct a routing tree (best paper award at ASPDAC’21). In addition, he proposes active learning (equipped with Gaussian process and neural process) as an advanced learning paradigm for design space exploration in EDA (published on TCAD’19 and TCAD’21).

Another distinctive contribution of Prof. Yu’s work is EDA for deep learning system. The resource consumption of the deep learning models is a major concern regarding the broad deployment on resource-constrained hardware. Prof. Yu investigates a unified approximation framework to compress and accelerate the deep learning models, where the low-rankness and structured sparsity are incorporated for model pruning. This work received the best student paper award from ICTAI’2019. He also proposes to optimize the HLS and TVM deployment strategies of DNN models on FPGA and GPU, cooperated with a set of advanced learning and optimization methodologies (published on 2x DATE’2021, 2x ICCAD’21 and ICCV’21). These methodologies facilitate DNN deployment on resource-constrained hardware with high efficiency and performance.


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