Who’s Li Jiang
July 1st, 2022
Compute-in-memory, Neuromorphic Computing, Domain Specific Architecture for AI, Database, networking etc.
Li Jiang received the B.S. degree from the Dept. of CS&E, Shanghai Jiao Tong University in 2007, the MPhil, and the Ph.D. degree from the Dept. of CS&E, the Chinese University of Hong Kong in 2010 and 2013, respectively. He has published more than 80 peer-review papers in top-tier computer architecture, EDA and AI/Database conferences and journals, including ISCA, MICRO, DAC, ICCAD, AAAI, ICCV, SigIR, TC, TCAD, TPDS and etc. He received the Best Paper Award in DATE’22, Best Paper Nomination in ICCAD10, and DATE21. According to the IEEE Digital Library, five articles ranked in the top 5 of citations of all papers collected at its conferences. Some of the achievements have been introduced into the IEEE P1838 standard, and several technologies have been in commercial use in cooperation with TSMC, Huawei, and Alibaba.
He got the best Ph.D. Dissertation award in ATS 2014, and he was in the final list of TTTC’s E. J. McCluskey Doctoral Thesis Award. He received ACM Shanghai Rising Star award and CCF VLSI early career award in 2019. He received the 2nd class prize of Wu Wenjun Award for Artificial Intellegence. He serves as co-chair and TPC member in several international and national conferences, such as MICRO, DATE, ASP-DAC, ITC-Asia, ATS, CFTC, CTC, etc. He is an Associate Editor of IET Computers Digital Techniques, VLSI, the Integration Journal. He is the co-founder of ChinaDA and ACM/SigDA East China Branch.
Prof. Li Jiang has been working on the test and repair architecture of 3D ICs that can dramatically reduce costs, advocating and emphasizing the precious resources sharing mechanism. They optimize the 3D SoC test architecture under test-pin count and thermal dissipation constraints by sharing the test-access-mechanism (TAM) and test wire of pre-bond wafer-level and post-bond package-level tests. They further propose the inter-die spare-sharing technique and the die-matching algorithms to improve the stack yield of 3D stacked memory. This work is nominated as the best paper in ICCAD 2010. Based on this method, they work with TSMC to propose a novel BISR architecture that can cluster and map faulty rows/columns across die to the same spare row/column to enhance the reparability. This series of works have been widely accepted by the mainstream and introduced into the IEEE P1838 standard.
To improve the assembly yield in the TSV fabrication process, they develop a fault model considering TSV coupling effect that has not been carefully investigated before. It leads their attention to a unique phenomenon, i.e., the faulty TSVs can be clustered. Thus, they propose a novel spare-TSV sharing architecture composed of a lightweight switch design, two effective and efficient repair algorithms, and a TSV-grid mapping mechanism that can avoid catastrophic TSV clustering defects.
ReRAM cell needs multiple programming pulses to avoid device programming variation and resistance drifting. To overcome the resulting programming latency and energy, they propose a Self-Terminating Write (STW) circuit that heavily reuses the inherent PIM peripherals (e.g., ADC and Trans-Impedance Ampliﬁer) to obtain 2-bit precision via a single program pulse. This work is the best paper award of DATE 2022.