January 1st, 2022

Kai Ni

Assistant Professor

Rochester Institute of Technology

Email:

kai.ni@rit.edu

Personal webpage

https://www.needskai.org/

Research interests

Emerging Devices for AI Accelerator, Emerging Devices for Unconventioanl Computing

Short bio

Kai Ni received the B.S. degree in Electrical Engineering from University of Science and Technology of China, Hefei, China in 2011, and Ph.D. degree of Electrical Engineering from Vanderbilt University, Nashville, TN, USA in 2016 by working on characterization, modeling, and reliability of III-V MOSFETs. Since then, he became a postdoctoral associate at University of Notre Dame, working on ferroelectric devices for nonvolatile memory and novel computing paradigms. He is now an assistant professor in Electrical & Microelectronic Engineering at Rochester Institute of Technology. He has around 100 publications in top journals and conference proceedings, including Nature Electronics, IEDM, VLSI Symposium, IRPS, EDL, etc. He has served as technical program committee for DAC, DATE, ASPDAC, IRPS, EDTM. His current interests lie in nanoelectronic devices empowering unconventional computing, domain-specific accelerator, and memory technology.

Reasearch highlights

Kai Ni has made important contributions to the development of ferroelectric HfO2 based field effect transistor (FeFET) and its technology applications. On the technology side, he has proposed the ferroelectric metal field effect transistor, which has a metal-ferroelectric-metal-oxide-semiconductor gate stack and has the freedom of optimizing the gate stack, and superlattice structure for multi-level cell. He has developed several models for FeFET explaining different behaviors of FeFET, including a compact model based on the Preisach model of ferroelectric, a Kinetic Monte Carlo model to explain device variation, and a comprehensive model which can capture all the key ferroelectric behaviors. With these models, he also explored the exciting applications of FeFET for in-memory computing. Examples include the crossbar array for matrix-vector multiplication, content addressable memory array for associative search, hardware security circuit, and reconfigurable computing. All these research activities have been published in top journals, and premier conferences, such as IEDM, VLSI Symposium, DAC, DATE, etc.