Who’s Johann Knechtel
April 1st, 2022
Hardware Security, Electronic Design Automation (EDA), 3D Integration, Emerging Technologies, Machine Learning
Dr.-Ing. Johann Knechtel is a Research Scientist with the Design for Excellence Lab at New York University (NYU) Abu Dhabi, UAE. In this position, he is acting as Co-PI for multiple research projects and provides lecturing, training, and mentoring to PhD and undergraduate students. Johann received the Dipl.-Ing. degree (M.Sc.) in Information Systems Engineering in 2010 and the Dr.-Ing. degree (Ph.D.) in Computer Engineering (summa cum lauda, with highest honors) in 2014, both from TU Dresden (TUD), Germany. Before joining NYU Abu Dhabi in 2016, Johann was a Postdoctoral Researcher in 2015 at the Masdar Institute of Science and Technology, UAE, where he was affiliated with the Twinlab on “3D Stacked Chips”, hosted by Masdar Institute and TUD and supported by industry and government partners. In 2012 he was with the Chinese University of Hong Kong, China, and in 2010 he was with the University of Michigan, USA. In 2006, he was working as Freelance Software Engineer for Siemens IT Solutions and Services, Germany; in 2006–08 he was working as Research Assistant for Fraunhofer IWS Institute, Dresden, Germany; and in 2008–09 he was working as Embedded Systems Intern for TraceTronic GmbH, Dresden, Germany. In 2017, Johann and his team achieved the 1st place in the CSAW Applied Research Competition. Johann obtained scholarships from the German Academic Exchange Service (DAAD) in 2010, from the German Research Foundation (DFG) in 2010–14, and from the Graduate Academy of TU Dresden in 2014. Johann obtained an NYU Research Enhancement Fund in 2018–21. Johann has (co-)authored around 60 publications, including 15 highlighted and/or invited papers. Johann is an active member of the ACM, including ACM SIGDA, and IEEE. He is serving as peer reviewer for various top-tier ACM and IEEE conferences and journals.
Johann is acting as Co-PI for multiple projects with the common goal of advancing hardware security. Johann’s work involves five PhD students and postdoctoral researchers at NYU Abu Dhabi and also covers collaborations with around 15 researchers and students at prestigious institutions worldwide. Johann’s work is currently focused on the following themes: 1. Security closure for physical design of integrated circuits (ICs); 2. Protection of IC design intellectual property, with advanced techniques proposed for split manufacturing and obfuscation utilizing interconnect fabrics as well as 2.5D and 3D integration; 3. Secure architectures and secure system integration based on chiplets and 2.5D integration; 4. Machine learning-driven security evaluation at design time of defense schemes like split manufacturing and logic locking; 5. Security evaluation of ICs and field-programmable gate arrays (FPGAs) using advanced electro-magnetic field and laser-assisted optical probing; 6. Design-time security evaluation of ICs against side-channel attacks; 7. Security promises and challenges of emerging technologies for various defense schemes; 8. Security-aware electronic design automation (EDA) flows for 2D, 2.5D, and 3D ICs. Johann has successfully published on these and other themes. Recent examples include two invited papers at ICCAD 2021 on security closure for physical design, two invited papers at ISPD 2020–21 on hardware security for and beyond CMOS devices, an invited paper at DATE 2020 on the role of EDA for secure composition of ICs, and invited papers at IOLTS and COINS 2019 on 3D integration as another dimension toward hardware security and on design IP protection, respectively. Furthermore, Johann and colleagues have recently compiled a book “The Next Era in Hardware Security: A Perspective on Emerging Technologies for Secure Electronics,” Springer, 2022, with already 1.7k full-text downloads as of today. Currently, Johann is acting as lead organizer for the first-ever international competition (co-hosted with ISPD 2022) on security closure. For that, research teams from all over the world are hardening the physical layouts of ICs at design time against selected attacks that are executed post-design time. This notion of security closure is quite complex, and besides the interest from the community with this contest and invited papers, Johann and colleagues are also in active discussion with government agencies on that challenge. Earlier, Johann and colleagues from TU Dresden, Germany, Google Inc., and Masdar Institute published a survey paper “Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration” in IPSJ Transactions on System LSI Design Methodology. Since its time of appearance in 2017, i.e., for five years already, this paper is constantly the most viewed article of that journal. In 2012, Johann published his first journal article in IEEE TCAD with colleagues from Michigan University, USA; at the time of appearance, this paper was the most popular article across all of that journal.