Author: Yibo Lin

March 1st, 2022

Xiaoming Chen

Associate Professor

Institute of Computing Technology,

Chinese Academy of Sciences

Email:

chenxiaoming@ict.ac.cn

Personal webpage

http://people.ucas.edu.cn/~chenxm

Research interests

EDA and computer architecture

Short bio

Xiaoming Chen received the B.S. and Ph.D. degrees in Electronic Engineering from Tsinghua University, in 2009 and 2014, respectively. Since 2017, he has been an associate professor at Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS). Before joining ICT, CAS, he was a postdoctoral research associate in Electrical and Computer Engineering, Carnegie Mellon University from 2014 to 2016, and a visiting assistant professor in Computer Science and Engineering, University of Notre Dame from 2016 to 2017.

His research interests are mainly focused on EDA and computer architecture. He has published about 100 papers in top journals and conference proceedings, including DAC, ICCAD, DATE, HPCA, IEEE TCAD, IEEE TVLSI, IEEE TPDS, etc. He has served as a technical program committee member for DAC, ICCAD, ASP-DAC, GLSVLSI, AsianHOST, VLSI Design, etc. He was awarded the Excellent Young Scientists Fund of National Natural Science Foundation of China in 2021. He received the 2015 EDAA Outstanding Dissertation Award and the 2018 Alibaba DAMO Academy Young Fellow Award. He received one of the two best paper awards in ASP-DAC 2022 and several best paper nominations in ASP-DAC and ISLPED.

Reasearch highlights

Prof. Xiaoming Chen has spent more than 10 years in the EDA trarea. Specifically, he has developed a parallel sparse direct solver named NICSLU that is well suited for SPICE-based circuit simulators. He proposed a series of novel techniques to elevate the performance of solving highly sparse linear systems from circuit simulation applications, including a new matrix ordering method to minimize fill-ins, a hybrid dynamic scheduling method for parallel matrix factorization, a numerically stable pivoting reduction technique, and an adaptive numerical kernel selection method. NICSLU achieves much higher performance than other sparse solvers in circuit simulation applications, and is also generally faster than state-of-the-art GPU-based solvers which are specially designed for circuit matrices. NICSLU has been used in a number of academic studies, EDA tools and power system simulators. Some techniques have been adopted in commercial SPICE tools of a leading EDA company in China. NICSLU is available at https://github.com/chenxm1986/nicslu.

Prof. Chen has also made important contributions in computing-in-memory (CiM) architecture design. He exposed how to utilize the device-level CiM feature of resistive random-access memories (RRAMs) and ferroelectric field-effect transistors (FeFETs) which can act as both storage elements and switch units, to unify the computing and storage resources at the circuit level, to realize interchangeable computing and storage functionalities at the architecture level. In addition, he has investigated the solutions to some fundamental problems in CiM systems, including data coherence, data contention, simulation methodologies, task assignment, etc. He has also explored the CiM feature of RRAMs and FeFETs in various applications, and designed energy-efficient and high-performance accelerators for neural networks, graph processing, linear algebra, and robots.

January 1st, 2022

Kai Ni

Assistant Professor

Rochester Institute of Technology

Email:

kai.ni@rit.edu

Personal webpage

https://www.needskai.org/

Research interests

Emerging Devices for AI Accelerator, Emerging Devices for Unconventioanl Computing

Short bio

Kai Ni received the B.S. degree in Electrical Engineering from University of Science and Technology of China, Hefei, China in 2011, and Ph.D. degree of Electrical Engineering from Vanderbilt University, Nashville, TN, USA in 2016 by working on characterization, modeling, and reliability of III-V MOSFETs. Since then, he became a postdoctoral associate at University of Notre Dame, working on ferroelectric devices for nonvolatile memory and novel computing paradigms. He is now an assistant professor in Electrical & Microelectronic Engineering at Rochester Institute of Technology. He has around 100 publications in top journals and conference proceedings, including Nature Electronics, IEDM, VLSI Symposium, IRPS, EDL, etc. He has served as technical program committee for DAC, DATE, ASPDAC, IRPS, EDTM. His current interests lie in nanoelectronic devices empowering unconventional computing, domain-specific accelerator, and memory technology.

Reasearch highlights

Kai Ni has made important contributions to the development of ferroelectric HfO2 based field effect transistor (FeFET) and its technology applications. On the technology side, he has proposed the ferroelectric metal field effect transistor, which has a metal-ferroelectric-metal-oxide-semiconductor gate stack and has the freedom of optimizing the gate stack, and superlattice structure for multi-level cell. He has developed several models for FeFET explaining different behaviors of FeFET, including a compact model based on the Preisach model of ferroelectric, a Kinetic Monte Carlo model to explain device variation, and a comprehensive model which can capture all the key ferroelectric behaviors. With these models, he also explored the exciting applications of FeFET for in-memory computing. Examples include the crossbar array for matrix-vector multiplication, content addressable memory array for associative search, hardware security circuit, and reconfigurable computing. All these research activities have been published in top journals, and premier conferences, such as IEDM, VLSI Symposium, DAC, DATE, etc.

January 1st, 2022

Christophe Bobda

Professor

University of Florida

Email:

cbobda@ece.ufl.edu

Personal webpage

https://bobda.ece.ufl.edu/

Research interests

Reconfigurable Computing, FPGA, System on Chip Design, Embedded Imaging, Cybersecurity and Robotics

Short bio

Professor Bobda received the License in mathematics from the University of Yaounde, Cameroon, in 1992, the diploma of computer science and the Ph.D. degree in computer science from the University of Paderborn in Germany in 1999 and 2003 respectively. In June 2003 he joined the department of computer science at the University of Erlangen-Nuremberg in Germany as Post doc. Dr. Bobda received the best dissertation award 2003 from the University of Paderborn for his work on synthesis of reconfigurable systems using temporal partitioning and temporal placement. In 2005 Dr. Bobda was appointed assistant professor at the University of Kaiserslautern. There he set the chair for Self-Organizing Embedded Systems that he led until October 2007. From 2007 to 2010 Dr. Bobda was Professor at the University of Potsdam and leader of the working Group Computer Engineering. Upon moving to the US, Dr. Bobda was appointed Professor of computer engineering at the University of Arkansas where he founded the smart embedded systems lab (2010 – 2018). Since 2019, Dr. Boda has been with the University of Florida as Professor of Computer Engineering, leader of the lab smart systems and outreach director of the the Nelms Institute of Connected World.

Reasearch highlights

Professor Christophe Bobda’ research interests lie primarily in the design of smart embedded systems, with emphasis of run-time optimization. He investigates the design and run-time operation of high-performance and adaptive architectures with application in image processing, embedded optimization, security, and control. He recently introduced an event-based split-CNN architecture (ESCA) for running time-critical vision applications with comparatively less memory footprint while consuming low power. ESCA has a dedicated hardware architecture and scheduling of on-chip memory buffering using a split-CNN that reduces memory requirements by splitting the feature maps into small patches and independently executes them. This work received the best short paper of award at FCCM2021. His previous work of “DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices” is nominated among the 23 most significant FPL papers of the last 25 years. His research enables a new paradigm to design adaptive architectures for various applications.

January 1st, 2022

Dayane Alfenas Reis

Assistant professor

Department of Computer Science and Engineering, University of South Florida

Email:

dayane3@usf.edu

Personal webpage

https://sites.google.com/view/dayane-reis/home

Research interests

VLSI design, Beyond-CMOS devices, In-memory computing architectures for data-centric applications, Hardware-software codesign, Secure computing

Short bio

Dr. Dayane Reis received her Ph.D. in Computer Science and Engineering from the University of Notre Dame in 2021, where she works as a Postdoctoral Researcher in the Hardware-Software Co-design Lab, under the direction of Dr. Xiaobo Sharon Hu and Dr. Michael Niemier. She also received the MSc. in Electrical Engineering from the Federal University of Minas Gerais, Brazil, in 2016, and the BSc. in Electronic Engineering from the Pontifical Catholic University of Minas Gerais, Brazil, in 2012. Dr. Reis’s research exploit the unique characteristics of beyond CMOS technologies for the design of fast, energy efficient and reliable in-memory computing kernels that can be used in a wide range of data-intensive application scenarios. She is the author of more than 20 articles in journals such as IEEE TVLSI, IEEE TCAD, IEEE Design, and Test, Nature Electronics, as well as renowned conferences including ISLPED, ASP-DAC, ICCAD and DATE. Dr. Reis was one of the two winners of the best paper award at the ACM/IEEE International Symposium on Electronics and Low Power Design in 2018 (ISLPED’18) for her paper “Computing in memory with FeFETs”, and a recipient of the Cadence Women in Technology (WIT) Scholarship 2018/2019, in recognition to her personal history and efforts toward the inclusion of women in STEM fields.

Reasearch highlights

Dr. Dayane Reis’s research investigates the impact of emerging technologies on the design of circuits and architectures for data-centric computing. Furthermore, her research also exploits non-von Neumann architectures – such as those based on the concept of in-memory computing (IMC) – to alleviate the impact of data transfers on a system’s overall performance and energy consumption. She designed the first IMC architecture based on Ferroelectric Field Effect Transistors (FeFETs) for general-purpose computing-in-memory. For this work, she won the Best Paper Award at the ISLPED. Furthermore, she designed a variety of hardware accelerators based on different IMC kernels (i.e., general-purpose computing-in-memory arrays, ternary content addressable memory arrays, etc.) for hardware-software codesign of meta-learning models and cryptography algorithms such as the Advanced Encrypted Standard (AES), and the Brakerski/Fan-Vercauteren scheme for homomorphic encryption. Dr. Reis also participated in the development of a uniform framework for benchmarking IMC architectures based on CMOS and emerging technologies. The framework allows researchers to assess the benefits of analog and digital IMC based on different devices for data-intensive tasks in the domain of machine learning and have wide applicability. Finally, together with collaborators at Purdue University, Dr. Reis proposed and evaluated polymorphic gates based on Black Phosphorus Field-Effect Transistors (BP-FETs) that operate with low voltage supply (up to 0.2V) and are resistant to power supply variations. Such hardware security primitives can be employed in logic obfuscation, having great utility for intellectual property protection.

January 1st, 2022

Pi-Cheng Hsiu

Research Fellow (Professor)

Academia Sinica

Email:

pchsiu@citi.sinica.edu.tw

Personal webpage

https://homepage.citi.sinica.edu.tw/pages/pchsiu/

Research interests

Embedded Software and Intermittent Computing

Short bio

Dr. Pi-Cheng Hsiu received the Ph.D. degree in computer science and information engineering from National Taiwan University in 2009. He is currently a Research Fellow (Professor) and the Deputy Director of the Research Center for Information Technology Innovation (CITI), where he leads the Embedded and Mobile Computing Laboratory, and is also a Joint Research Fellow with the Institute of Information Science, Academia Sinica, Taiwan, a Jointly Appointed Professor with the Department of Computer Science and Engineering, National Chi Nan University, and a Jointly Appointed Professor with the College of Electrical Engineering and Computer Science, National Taiwan University. He was a Visiting Scholar with the Department of Computer Science, University of Illinois at Urbana-Champaign, in 2007 and with the Department of Electrical and Computer Engineering, University of Pittsburgh, in 2019. 

Dr. Hsiu constantly publishes papers at the premier venues in embedded systems, real-time systems, and design automation. His works were respectively nominated for the Best Paper Awards at IEEE/ACM CODES+ISSS 2019, 2020, and 2021, of which the last two received the Best Paper Awards in a row. He is a recipient of the 2019 Young Scholars’ Creativity Award of the Foundation for the Advancement of Outstanding Scholarship, the 2019 Exploration Research Award of the Pan Wen Yuan Foundation, and the 2015 Scientific Paper Award of the Y. Z. Hsu Science and Technology Memorial Foundation. He serves as an Associate Editor of the ACM Transactions on Cyber-Physical Systems, Track Co-Chairs of IEEE/ACM ISLPED and ACM SAC, and in the Technical Program Committees of major conferences in his field, including RTSS, RTAS, CODES+ISSS and DAC.

Reasearch highlights

Dr. Hsiu’s research goal is to realize Intermittent Artificial of Things (iAIoT), enabling battery-less IoT devices to intermittently execute deep neural networks (DNN) via ambient power. iAIoT is a novel research direction at the intersection of intermittent computing and deep learning, and once realized, would create innovative applications.

He has led a research team to release a suite of system runtime and libraries, facilitating AI and IoT application developers to easily build low cost, intermittent-aware inference systems. In particular, an intermittent operating system (TCAD’20), which was the first attempt to allow multitasking and task concurrency on intermittent systems, makes complicated intermittent applications increasingly possible. The HAWAII middleware (TCAD’20), which comprises an inference engine and API library, enables hardware accelerated intermittent DNN inference. In addition, the iNAS framework (TECS’21) was the first framework that introduces intermittent execution behavior into neural architecture search to automatically find intermittently-executable DNN models. HAWAII and iNAS received the Best Paper Awards, respectively, for two years in a row at IEEE/ACM CODES+ISSS 2020 and 2021. Such recognition indicates the innovativeness of his research and contributions to the community.

December 1st, 2021

Yi-Chung Chen

Associate Professor

Tennessee State University

Email:

ychen@tnstate.edu

Personal webpage

https://yichungchen84.github.io/

Research interests

Application-specific system, 3-D integration, Heat simulation, NVM, Data pipeline, Deep learning

Short bio

Yi Chung Chen is currently an Assistant Professor in the Department of Electrical and Computer Engineering, Tennessee State University. He received the Ph.D. degree from Electrical and Computer Engineering, University of Pittsburgh, USA in 2014, and the M.S. degree in Electrical and Computer Engineering from New York University, New York in 2011. He has served as TPC member in many conference committees. He has served as committee member of regional and national STEM education committees for silicon and digital system education of underrepresented minorities. He has also served as organizing and technical program committee members of conferences.

Reasearch highlights

Prof. Chen’s has published interdisciplinary papers in the major research fields across computing systems and applications. His research contribution lies in vertical integration of EDA tools for design of application-specific computer system. He investigates data-driven intelligent systems for adaptive, resilient, and expandable operations demanded by critical missions. His research projects are supported by the US AF, the US ARMY, ASEE, and NSF. In addition, Prof. Chen is an acting committee member of semiconductor research and education working group for minority serving institutions. He is on a mission to prepare future semiconductor workforce of underrepresented groups in engineering by building education and research capacity with opensource EDA tools.