Ph.D. Forum@DAC 2022

The Ph.D. Forum at the Design Automation Conference is a poster session hosted by ACM SIGDA and IEEE CEDA for Ph.D. students to present and discuss their dissertation research with people in the EDA community. It has become one of the premier forums for Ph.D. students in design automation to get feedback on their research and to connect with other members of the community. It also enables both, academicians and industry, to see the best graduating students in one place. Presentations are selected through a scientific evaluation by an expert committee consisting of academia and industry. The forum is open to all members of the design automation community and is free-of-charge. It is co-located with DAC, but a DAC registration is not required in order to attend this event.

Submission Process

In order to select the presentations to be featured at the DAC Ph.D. Forum, we are seeking contributions from students who are currently working on their Ph.D. or have recently completed their Ph.D. Corresponding applications have to be submitted through EasyChair and need to include the following two documents:

  • A two-page PDF abstract of the dissertation (in two-column format, using 10-11 pt. fonts and single-spaced lines), including name, institution, advisor, contact information, estimated (or actual) graduation date, whether the work has been presented at the ASP-DAC Ph.D. Forum or the DATE Ph.D. Forum, as well as figures, and bibliography (if applicable). The two-page limit on the abstract will be strictly enforced: any material beyond the second page will be truncated before sending to the reviewers. Please include a description of the supporting paper, including the publication forum. A list of all papers authored or co-authored by the student, related to the dissertation topic and included in the two-page abstract, will strengthen the submission.
  • A published (or accepted) paper, in support of the submitted dissertation abstract. The paper must be related to the dissertation topic and the publication forum must have a valid ISBN number. It will be helpful, but is not required, to include your name and the publication forum on the first page of the paper. Papers on topics unrelated to the dissertation abstract or not yet accepted will not be considered during the review process.

Please include the supporting paper with the abstract in one PDF file and submit the single file (there are many free utilities available online which can merge multiple PDF files into a single file if necessary). Then, please submit your application through the following link:

Important Dates

  • Abstract Submission: March 13, 2022
  • Notification Date: May 8, 2022
  • Forum Presentation Date: July 12, 2022 in San Francisco


All submitters must satisfy the following eligibility constraints:

  • Dissertation topic must be relevant to the DAC community.
  • Students with at least one published or accepted conference, symposium or journal paper.
  • Students within 1-2 years of dissertation completion and students who have completed their dissertation during the 2021-2022 academic year. Students closer to graduation will have higher priority since the rest of the students can attend a future Ph.D. Forum with more mature results.
  • Students who have presented previously at the DATE and ASP-DAC Ph.D. forums are eligible, but will be less likely to receive travel assistance.
  • Previous DAC SIGDA Ph.D. forum presenters are not eligible.
  • Students having a conflict of interests with one of the (co-)chairs and/or a member of the evaluation committee are allowed to submit. The submission will then be handled by different chairs/members and the entire evaluation will be completely blind to the anyone with a CoI.

Furthermore, it is strongly recommended to consider the following remarks:

  • The abstract is the key part of your submission. Write the abstract for someone familiar with your technical area, but entirely unfamiliar with your work. Clearly indicate the motivation of your Ph.D. dissertation topic, the uniqueness of your approach, as well as the potential impact your approach may have on the topic.
  • Proper spelling, grammar, and coherent organization are critical: remember that the two pages may be the only information about yourself and your PhD research available to the reviewers.

Travel Support and Best Presentation Award

All presentations selected to be presented at the DAC Ph.D. Forum are eligible to apply for some travel support as well as for getting awarded with a Best Presentation Award. Corresponding information on how to apply for travel support will be provided later to all accepted presenters (however, please note that travel support can only be given to a selected amount of presenters and will only cover a fraction of the actually needed travel costs). The Best Presentation Award is selected by a dedicated committee at the Ph.D. Forum (taking the submission as well as the actual presentation into account). The same CoI guidelines as for submission evaluation apply.


For questions not addressed on this page, please send an e-mail to Robert Wille ( Please include “DAC Ph.D Forum” in the subject line of your email.

Sponsored By

Organizers Guide

ACM/SIGDA Guide to Running or Starting a Conference, Symposium, or Workshop

Revised on May 1, 2020

ACM/SIGDA sponsors a number of conferences, symposia, and workshops, which will be referred to generically as events. The event staff are almost always volunteers, and those involved change on a yearly basis. The purpose of this guide is to give a short overview of how events are run, make you aware of services that ACM and SIGDA can provide, and to help simplify the entire process.

This guide is divided into four sections. First is the “financial” aspect of running an event: contracts with hotels, registration, etc. Second is the “administrative” component: selecting a program committee, setting up a timeline, handling paper submissions and reviews, creating and archiving the event web site, and passing control to the next set of organizers. Third is a checklist and timeline, to give an idea of when various tasks should be done. The last part is about the travel grant.
Financial View
SIGDA is a non-profit professional society–there is no expectation that an event (particularly a new one) will return a large surplus. Having some positive revenue, however, is desirable. The bulk of funds that are used to support student travel, reduced student registrations, online access to DA literature, salary for permanent staff, insurance coverage, among other things, comes from conference revenue. SIGDA membership fees provide almost no revenue.
Cosponsorship and In Cooperation
Most events are cosponsored by some branch of the IEEE; some events have other cosponsors. Generally, sponsorship implies financial and legal responsibility for the event. That includes providing insurance, accepting liability for contracts and covering any deficit the conference might incur. If the conference should have a surplus, the sponsor or co-sponsor will receive a portion of that surplus based on their percentage of sponsorship. Co-sponsorship percentages rarely change; both ACM and IEEE are interested in having good cooperation between the societies, and by sharing both risks and rewards across the societies, service is improved for the members. Dual sponsorship also broadens the audience for any advertising, improving overall attendance. In some cases, a group may be “in cooperation” — which implies that they see value in the technical program and wish to lend their name to the event without taking on any financial or legal responsibility.

TMRF — Technical Meeting Request Form
A TMRF is a large spreadsheet that details the expected attendance, registration costs, hotel costs, printing costs, and so forth. The objective is to determine if the event is financially viable, and in keeping with prior years. The organizers of an event will need to file a TMRF, and receive approval, before ACM will accept any financial responsibility. One common concern is with respect to some additional fees in the TMRF based on total expenditures. These fees go to cover ACM insurance and liability expenses, and help cover the salaries of the permanent staff at ACM.

Care should be taken when preparing a TMRF; try to keep all costs and projected revenues within reason–in some cases, approval has been delayed due to budget concerns. We stress again that there is no requirement for an event (particularly a new one) to turn a profit, although this is preferable. If an event is profitable, it enables SIGDA to fund other activities, to support events in new areas, and to weather short term losses without sacrificing member services.

ACM Support Staff
ACM employs a number of permanent staff to assist in planning and running an event. In particular, the staff has data on the following.

  • Other events in a given city, and on a given date. Hotel prices may be extremely high if you are planning your event in a town that is hosting a major activity.
  • Listings of hotels in a given town, with rough estimates on the number of attendees they can support, the types of conference rooms available, etc.
  • Obviously, having a successful event will require good location at a time the attendees find convenient. Consulting the ACM staff on this is highly recommended. The ACM staff involved with supporting events can be found on our Who’s Who page and ACM’s SIG volunteer resources page.

Never sign any contract personally. If a disaster occurs, a hotel may hold you responsible for all charges. For example, a conference scheduled to be held a few days after the 9/11 terrorist attack was cancelled. The hotel that was to hold the event lost many room bookings, which was charged back to the sponsoring societies, costing them thousands of dollars. ACM and SIGDA are prepared to accept this type of financial liability. As an event organizer, you should not put yourself in this position.

We recommend that you allow the ACM staff to do the bulk of the negotiation with the hotel or conference center. They are familiar with industry practices, know typical rates, and can use the membership of ACM as leverage for better deals. The staff will keep you informed, and will work to find arrangements that are to your satisfaction.

Allowing early registration through the web is highly recommended; this is a good way to get an early estimate on attendance. ACM can support electronic registration, but must charge some fees to cover related expenses and the time required for the support staff.

There are several ways to handle on-site registration: you may have either volunteer staff or a professional organization, and you may wish to accept cash, checks, or credit cards. If you accept credit cards, billing immediately will require phone access, equipment, and coordination with a credit agency. We would recommend instead simply recording the credit card number manually, and then having ACM process the charges after the event.

If the event is relatively small, we highly recommend finding volunteers to man the registration desk; professional conference management can be quite expensive

Executive Committee
Most events have an “executive committee” consiting of a general chair, program committee chair, publications chair, and publicity chair. Larger events may have more positions. In most cases, there is a progression of staff through the positions, allowing new members to gain experience before taking control of an event.

Program Committee
For paper review, a program committee should be formed. We encourage a balance of academic and industry representatives. Selection of committee members should be done carefully: a well-respected group will improve the public perception of accepted papers, encourage good research groups to submit papers, and will improve attendance.

We recommend setting a timeline for all tasks related to the event. By setting the timeline, all committee members will know when certain tasks must be done, and will be able to plan accordingly. At the end of this document we show a sample timeline that contains common tasks. Specific dates obviously depend on the event itself. Carefully adjusting the dates to fit in with other events is beneficial. For example, it might be possible to arrange a program committee meeting to follow a widely attended conference, which reduces the cost of attending the meeting and improves committee members’ participation. When possible, advertising should be scheduled to coincide with similar events.

Paper Submission, Review, and Selection
Paper submission should be performed electronically; this greatly simplifies the submission and review process. Supported file formats (PDF, PostScript, DOC, text, etc.) are at the discretion of the program committee, although we suggest that PDF be the preferred format. ACM has style guidelines for proceedings and journal papers, and these should be referenced on any call for papers or submission web site.

There are a number of conference paper management software packages. At one point, ACM investigated supporting one in-house. Each program committee seemed to have a specific package that they were quite loyal to, making centralized support impractical. If your program committee does not have a specific preference, check with ACM staff to see if there is a supported package.

Web based conference software generally supports online review submission. We suggest sending periodic “warning” emails to reviewers, letting them know the review deadlines. Without these reminders, many reviewers may wait until the last minute, resulting in low-quality reviews.

Paper selection should be performed by the program committee in a timely fashion. A fast turn-around on submissions will benefit authors, and increase the number of submitted papers.

Proceedings — Printed and Electronic
The print version of the proceedings will require coordination with the printer. There will be deadlines for final camera-ready paper submissions, table of contents, etc. Plan for some authors being a few days late with submissions, and allow for unexpected delays.

Generally, workshops do not have “published” proceedings. Discuss with the ACM staff if the event material should be considered as a publication. For workshops, many authors may be willing to discuss preliminary results, as long as it does not preclude them from publishing the work in a larger venue.

ACM/SIGDA supports online access to all sponsored event material. It can be made available through the ACM portal, the SIGDA web site, and on annual SIGDA publication compendiums. Part of the revenue from successful conferences has allowed SIGDA to subsidize this publication, making all material available free of charge. For events co-sponsored with IEEE, the material is likely still available free of charge; IEEE and ACM have been cooperating actively to make publications as widely available as possible.

Creation and Archival of a Web Site
ACM provides free-of-charge web hosting and web site archival for sponsored events. Even domain registration fees can be covered. Funding for this activity is derived from budget surpluses from successful sponsored events.

If the web hosting for your event is not currently handled by ACM, contact the staff, and they will assist in setting things up.

Handoff to the Next Organizers
Perhaps the most important task for an executive committee is making arrangements to hand off the event to a new group. The next executive committee will need to know attendance, number of submissions, acceptance rate, planned and actual expenses, and any comments from the attendees. We recommend having the next set of organizers identified early–perhaps by the time of the event–giving enough time for them to prepare and have success for the next year.
We would suggest filling in dates for the following events as soon as possible, and then distributing the checklist to the executive committee. This should help committee members from missing important task deadlines, and makes sure that no one is “in the dark.”

  • Contact ACM staff for preliminary event planning.
  • Finalize the event executive committee.
  • Recruit technical program committee members.
  • Establish event website.
  • Identify event location and venue; ACM staff members should be able to help.
  • Submit TMRF to ACM.
  • Publish “Call for Papers” deadline in print.
  • Publish “Call for Papers” electronically.
  • Establish and publish paper submission deadline.
  • Assign papers to reviewers.
  • Review submission deadline.
  • Call meeting of the Technical Program Committee.
  • Print deadline for “Call for Participation.”
  • Notify authors.
  • Have papers ready for camera-ready paper deadline.
  • Distribute electronic call for participation.
  • Begin accepting conference registrations.
  • Identify executive committee members for next year.
  • Event.
  • Collect statistics on event for ACM and next organizers.
  • Hand over control to the next committee.

Travel grants:

  1. If the conference event is solely financially sponsored by the ACM SIGDA, or is jointly financially sponsored by ACM SIGDA and other organizations, the conference organizer is generally suggested to include travel grants into the conference budget. In this case, the travel grant will be handled by the event organizer;
  2. For any reason that 1 cannot be implemented, the participants of the conference can apply for ACM SIGDA travel grants directly from the ACM SIGDA. In this case, the travel grants will be handled by the ACM SIGDA, or handled by the conference organizer authorized by the ACM SIGDA.

CADathlon 2018@ICCAD

SIGDA’s CADathlon 2018 at ICCAD

Sunday, Nov. 4, 2018  8 am – 5 pm, Hilton San Diego Resort & Spa,  San Diego, CA


Welcome to the CADathlon @ ICCAD

The CADathlon is a challenging, all-day, programming competition focusing on practical problems at the forefront of Computer-Aided Design,
and Electronic Design Automation in particular. The contest emphasizes the knowledge of algorithmic techniques for CADapplications,
problem-solving and programming skills, as well as teamwork.
In its 15th year as the “Olympic games of EDA,” the contest brings together the best and the brightest of the next generation of CAD
professionals. It gives academia and the industry a unique perspective on challenging problems and rising stars, and it also helps attract
top graduate students to the EDA field.
The contest is open to two-person teams of graduate students specializing in CAD and currently full-time enrolled in a Ph.D. granting
institution in any country. Students are selected based on their academic backgrounds and their relevant EDA programming experiences.
Partial or full travel grants are provided to qualifying students. CADathlon competition consists of six problems in the following areas:

  • Circuit Design & Analysis
  • Physical Design & Design for Manufacturability
  • Logic & High-Level Synthesis
  • System Design & Analysis
  • Functional Verification & Testing
  • Future technologies (Bio-EDA, Security, AI, etc.)

More specific information about the problems and relevant research papers will be released on the Internet one week prior to the
competition. The writers and judges that construct and review the problems are experts in EDA from both academia and industry. At the
contest, students will be given the problem statements and example test data, but they will not have the judges’ test data. Solutions
will be judged on correctness and efficiency. Where appropriate, partial credit might be given.
The team that earns the highest score is declared the winner. In addition to handsome trophies, the first place and the second place teams
receive cash award, and the contest winners will be announced at the ICCAD Opening Session on Monday morning and celebrated
at the ACM/SIGDA Dinner and Member Meeting on Monday evening.

Global Education Partner:



SIGDA Live is a series of webinars, launched monthly or bi-monthly, on topics (either technical or non-technical) of general interest to the SIGDA community. The talks in general fall on the last Wednesday of a month, and last about 45 minutes plus 15 minutes Q&A. Speaker and topic nominations are welcome and should be sent to All past talks are archived through our Youtube channel at: Each year we recognize one speaker with the “Most Influential Speaker of the Year” award.

OrganizersYiyu Shi (University of Notre Dame), Qinru Qiu (Syracuse University)

Technical supportBei Yu (Chinese University of Hong Kong)

Coming Up Next:

  • Prof. Hai “Helen” Li (Duke University)
  • March 28 (Wednesday) 9am Eastern Standard Time
  • Talk title: Brain Inspired Computing: The Extraordinary Voyages in Known and Unknown Worlds
  • Abstract:Human brain is the most sophisticated organ that nature ever builds. Building a machine that can function like a human brain, indubitably, is the ultimate dream of a computer architect. Although we have not yet fully understood the working mechanism of human brains, the part that we have learned in past seventy years already guided us to many remarkable successes in computing applications, e.g., artificial neural network and machine learning. The recently emerged research on “neuromorphic computing”, which stands for hardware acceleration of brain-inspired computing, has become one of the most active areas in computer engineering. The talk will start with a background introduction of neuromorphic computing, followed by examples of hardware acceleration schemes of learning and neural network algorithms and memristor-based computing engine. I will also share our prospects on the future technology challenges and advances of neuromorphic computing.
  • Bio: Hai “Helen” Li received the B.S. (1998) and M.S. (2000) degrees from Tsinghua University, Beijing, China, and the Ph.D. degree (2004) from the Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA. She is currently Clare Boothe Luce Associate Professor with the Department of Electrical and Computer Engineering at Duke University, Durham, NC, USA. She was with Qualcomm Inc., San Diego, CA, USA, Intel Corporation, Santa Clara, CA, Seagate Technology, Bloomington, MN, USA, the Polytechnic Institute of New York University, Brooklyn, NY, USA, and the University of Pittsburgh, Pittsburgh, PA, USA. She has authored or co-authored over 200 technical papers published in peer-reviewed journals and conferences and holds 70+ granted U.S. patents. She authored a book entitled Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing (CRC Press, 2011). Her current research interests include memory design and architecture, neuromorphic architecture for brain-inspired computing systems, and architecture/circuit/device cross-layer optimization for low power and high performance. Dr. Li serves as an Associate Editor of TVLSI, TCAD, TODAES, TMSCS, TECS, CEM, TCAS-II and the IET Cyber-Physical Systems: Theory & Applications. She has served as organization committee and technical program committee members for over 30 international conference series. She received the NSF CAREER Award (2012), the DARPA YFA Award (2013), TUM-IAS Hans Fisher Fellowship from Germany (2017), seven best paper awards and another seven best paper nominations. Dr. Li is a senior member of IEEE and a distinguished member of ACM.
  • News release: TBD

Please register here if you wish to attend the talk (required). The link of the talk will be sent in due course to the registrants only.


DASS at DAC 2018

The Design Automation Summer School (DASS) is a one-day intensive course on research and development in design automation (DA). Each topic in this course will be covered by a distinguished speaker who will define the topic, describe recent accomplishments, and indicate remaining challenges. Interactive discussions and follow-up activities among the participants will be used to reinforce and expand upon the lessons. This program is intended to introduce and outline emerging challenges, and to foster creative thinking in the next generation of EDA engineers. Simultaneously, they also help the students hone their problem solving, programming, and teamwork skills, in addition to fostering long-term collégial relationships. The 2018 SIGDA Design Automation Summer School is co-hosted by A. Richard Newton Young Fellowship Program at ACM/IEEE Design Automation Conference (DAC). DASS program will be co-hosted by DAC RNYS program and will be held on Sunday June 24, 2018 at Room 30003, Moscone Center West, from 9 a.m. to 6 p.m. in San Francisco, California. Richard Newton Young Student Fellowship Welcome breakfast is held at the same room from 7:30 am to 8:30 am. All the students receiving the fellowship (excluding the mentors) are required to attend DASS event.
The DASS event complements other educational and professional development activities in design automation including outreach projects such as the SIGDA University Booth, the CADathlon, and the Design Automation Conference (DAC) Ph.D. forum that have met with tremendous success over the past decade. Note that there is no separate call for participation for DASS. Attending DASS is mandatory for all the students receiving the Richard Newton Young Fellowship. The DASS final program will be available in late April 2018.
Organizing Committee:

SIGDA advisory committee for DASS:

DASS Schedule

  • Date: Sunday June 24, 2018
  • Time: 7:30am – 6:00pm
  • Location: Room 3003, Moscone Center West, San Francisco, California

The detailed schedule is listed below:

TimeSession titleSpeakersTitle
7:30-9:00 amBreakfast and RNYF Networking
9:00-11:00 amIn-Memory ComputationsOnur Mutlu (ETH Zürich)Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation
10:00-10:15 amCoffee Break
11:00am-12:00pmNeuro-Inspired LearningKaushik Roy (Purdue University)Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems
12:00-1:00 pmLunch
1:00-2:00 pmEDASani Nassif (Radyalis)From EDA to ’42’
2:00-3:00 pmEDAKunal Ghosh (VSD)An overview of RISC-V CPU Core implementation and sign-off using EDA management system
3:00-4:00 pmEDASeetharam Narasimhan (Intel)Security Evaluation of System-on-Chip (SoC) Products
4:00-4:30 pmCoffee Break
4:30-6:00 pm Laleh Behjat (University of Calgary)Give a Winning Presentation: From Idea to Delivery
6:00 – OnwardReception and Networking: Welcome Reception Level 3 Lobby

Invited Talks

  • Title: Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation
    Spaeker: Onur Mutlu (ETH Zürich)
    Abstract: Today’s systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in systems that cause performance, scalability and energy bottlenecks: 1) data access from memory is already a key bottleneck as applications become more data-intensive and memory bandwidth and energy do not scale well, 2) energy consumption is a key constraint in especially mobile and server systems, 3) data movement is very expensive in terms of bandwidth, energy and latency, much more so than computation. These trends are especially severely-felt in the data-intensive server and energy-constrained mobile systems of today. At the same time, conventional memory technology is facing many scaling challenges in terms of reliability, energy, and performance. As a result, memory system architects are open to organizing memory in different ways and making it more intelligent, at the expense of slightly higher cost. The emergence of 3D-stacked memory plus logic as well as the adoption of error correcting codes inside the latest DRAM chips are an evidence of this trend. In this lecture, I will discuss some recent research that aims to practically enable computation close to data. After motivating trends in applications as well as technology, we will discuss at least two promising directions: 1) performing massively-parallel bulk operations in memory by exploiting the analog operational properties of DRAM, with low-cost changes, 2) exploiting the logic layer in 3D-stacked memory technology in various ways to accelerate important data-intensive applications. In both approaches, we will discuss relevant cross-layer research, design, and adoption challenges in devices, architecture, systems, applications, and programming models. Our focus will be the development of in-memory processing designs that can be adopted in real computing platforms and real data-intensive applications, spanning machine learning, graph processing and genome analysis, at low cost. We will also discuss and describe simulation and evaluation infrastructures that can enable exciting and forward-looking research in future memory systems, including Ramulator and SoftMC.
    Biography: Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the William D. and Nancy W. Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, and bioinformatics. He is especially interested in interactions across domains and between applications, system software, compilers, and microarchitecture, with a major current focus on memory and storage systems. A variety of techniques he, together with his group and collaborators, have invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. His industrial experience spans starting the Computer Architecture Group at Microsoft Research (2006-2009), and various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, faculty partnership awards from various companies, a healthy number of best paper or “Top Pick” paper recognitions at various computer systems and architecture venues, and the ACM Fellow recognition “for contributions to computer architecture research, especially in memory systems.” His computer architecture course lectures and materials are freely available on YouTube, and his research group makes software artifacts freely available online. For more information, please see his webpage at
  • Title: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems
    Speaker: Kaushik Roy (Purdue University)
    Abstract: Advances in machine learning, notably deep learning, have led to computers matching or surpassing human performance in several cognitive tasks including vision, speech and natural language processing. However, implementation of such neural algorithms in conventional “von-Neumann” architectures are several orders of magnitude more energy expensive than the biological brain. Hence, we need fundamentally new approaches to sustain exponential growth in performance at high energy-efficiency beyond the end of the CMOS roadmap in the era of ‘data deluge’ and emergent data-centric applications. Exploring the new paradigm of computing necessitates a multi-disciplinary approach: exploration of new learning algorithms inspired from neuroscientific principles, developing network architectures best suited for such algorithms, new hardware techniques to achieve orders of improvement in energy consumption, and nanoscale devices that can closely mimic the neuronal and synaptic operations of the brain leading to a better match between the hardware substrate and the model of computation. In this presentation, I will discuss recent developments in CMOS and non-CMOS devices and architectures for implementing brain-inspired hardware. Implementation of different neural operations with varying degrees of bio-fidelity (from “non-spiking” to “spiking” networks) and implementation of on-chip learning mechanisms (Spike-Timing Dependent Plasticity) will be discussed. Additionally, we also show probabilistic neural and synaptic computing platforms that can leverage the underlying stochastic device physics of spin-devices due to thermal noise. System-level simulations indicate ~100x improvement in energy consumption for spin-based neural computing over a corresponding CMOS implementation across different computing workloads. Complementary to the above efforts, I will also present different learning algorithms including stochastic learning with one-bit synapses that greatly reduces the storage/bandwidth requirement while maintaining competitive accuracy, and adaptive online learning that efficiently utilizes the limited memory and resource constraints to learn new information without catastrophically forgetting already learnt data.
    Biography: Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. He also the director of the center for brain-inspired computing (C-BRIC) funded by SRC/DARPA. His research interests include neuromorphic and emerging computing models, neuro-mimetic devices, spintronics, device-circuit-algorithm co-design for nano-scale Silicon and non-Silicon technologies, and low-power electronics. Dr. Roy has published more than 700 papers in refereed journals and conferences, holds 18 patents, supervised 75 PhD dissertations, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award (Charles Doeser Award), Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD Vannevar Bush Faculty Fellow (2014-2019), Semiconductor Research Corporation Aristotle award in 2015, and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay) and Global Foundries visiting Chair at National University of Singapore. He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings — Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.
  • Title: From EDA to ’42’
    Speaker: Sani Nassif (Radyalis)
    Abstract: No field in Engineering has had the sustained exponential that was Moore’s Law. One of the outcomes is a rich culture of “using computers to automate the design of computers”, namely EDA, which has had to rapidly adapt to ever larger complexity. But with Moore’s era now over, it is time to apply the energy of the EDA community to other areas. This talk will explore the application of EDA techniques and knowhow to the area of Cancer Radiation Therapy, and specific technical problems that are of great interest to the Oncologists will be related to EDA and other areas of work like Big Data.
    Biography: Sani received his Bachelors degree with Honors from the American University of Beirut in 1980, and his Masters and PhD degrees from Carnegie-Mellon University in 1981 and 1986 respectively. He then worked for ten years at Bell Laboratories in the general area of technology CAD, focusing on various aspects of design and technology coupling including device modeling, parameter extraction, worst case analysis, design optimization and circuit simulation. While at Bell Labs, working under Larry Nagel -the original author of Spice, he led a large team in the development of an in-house circuit simulator, named Celerity, which became the main circuit simulation tool at Bell Labs. In January 1996, he joined the then newly formed IBM Austin Research Laboratory (ARL), which was founded with a specific focus on research for the support of IBM’s Power computer systems. After twelve years of management, he stepped down to focus on technical work again with an emphasis on applying techniques developed in the VLSI-EDA area to IBM’s Smarter Planet initiative. In January 2014 Sani founded Radyalis, a company focused on applying VLSI-EDA techniques to the field of Cancer Radiation Therapy. Sani has authored one book, many book chapters, and numerous conference and journal publications. He has delivered many tutorials at top conferences and has received Best Paper awards from TCAD, ICCAD, DAC, ISQED, ICCD and SEMICON, authored invited papers to ISSCC, IEDM, IRPS, ISLPED, HOTCHIPS, and CICC. He has given Keynote and Plenary presentations at Sasimi, ESSCIRC, BMAS, SISPAD, SEMICON, VLSI-SOC, PATMOS, NMI, ASAP, GLVLSI, TAU, ISVLSI and DATE. He is an IEEE Fellow, was a member of the IBM Academy of Technology, a member of the ACM and the AAAS, and an IBM master inventor with more than 75 patents. He was the president of the IEEE Council on EDA (CEDA) for 2014 and 2015.
  • Title: An overview of RISC-V CPU Core implementation and sign-off using EDA management system
    Speaker: Kunal Ghosh (VSD)
    A good backend/full flow session
    VSDFlow is a ‘plug-n-play’ EDA management system, built for chip designers to implement their ideas and convert to GDSII. ‘Plug-n-Play’ refers to switching between any eda tools, for eg. user can plug Cadence Genus for synthesis, Synopsys ICC for PNR and Tempus for sign-off STA. The output report will provide a QOR of entire design, which forms the starting point for design analysis. In this session, we will present how this management system works, how other tools (like Qflow and Opentimer) can be plugged in, and the full flow results on medium sized designs like picoRV32 – a RISC-V cpu core that implements RV32I instruction set
    VSD stands for VLSI System Design (name of our company)
    More references…
    Students can download for free, though there is a online course as well
    ‘vsdflow’ – A plug-n-play EDA management system (EMS)
    Kunal Ghosh, VLSI System Design Corp. Pvt. Ltd.
    Qflow: A flexible open source tool flow for digital synthesis of ASIC designs R. Timothy Edwards,
    Opentimer: An open-source high-performance timing analysis tool for large designs
    Tsung-wei Huang, Martin Wong, UIUC
    Biography: Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm’s Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.
  • Title: Security Evaluation of System-on-Chip (SoC) Products
    Speaker: Seetharam Narasimhan (Intel)
    Abstract: With the rapid proliferation of computation and connectivity in a wide variety of devices, ranging from the edge to the cloud, we are rapidly entering the era of the Internet of Things. However, underlying the desire to have all things smart and connected is the overarching fear of security breaches and loss of privacy, which are also becoming commonplace news. Security is no longer considered as an after-thought during the design and development lifecycle of System-on-Chip (SoC) products. In this talk, we shall focus on the hardware security aspects of SoCs and how a systematic evaluation at different stages of the product lifecycle (architecture, design implementation and validation) can help reduce the risk of security vulnerabilities. Proper threat modeling and iterative security-oriented design reviews can be powerful tools in preventing security loopholes, while pre- and post-silicon security validation can be used to detect any implementation issues which lead to security vulnerabilities. We shall use synthetic examples to examine how automated frameworks and evaluation tools can help in finding these issues early and mitigating their impact. We shall also highlight the challenges and research opportunities in this field.
    Biography: Seetharam Narasimhan is a Security Researcher (architect) at the Security Center of Excellence, Platform Architecture Group of Intel Corporation, Hillsboro, Oregon, USA. He has a Ph.D. in Computer Engineering from Case Western Reserve University (USA) and a B.E. (Hons.) in Electronics and Telecommunication Engineering from Jadavpur University (India). His research interests include: Hardware Security, Ultralow power and reliable nanoscale circuits, as well as Bio-medical circuits and systems. He is the co-author of three book chapters, and more than 40 publications in international journals and conferences of repute.
  • Title: Give a Winning Presentation: From Idea to Delivery
    Speaker: Laleh Behjat (University of Calgary)
    Biography: Dr. Laleh Behjat is a Professor in the department of Electrical and Computer Engineering, Schulich School of Engineering, University of Calgary. She joined the University of Calgary in 2002. Dr. Behjat’s research focus is on developing EDA techniques for physical design and application of large scale optimization in EDA. Her research team has won several awards including 1st and 2nd places in ISPD 2014 and ISPD 2015 High Performance Routability Driven Placement Contests and 3rd place in DAC Design Perspective Challenge in 2015. She is an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and Optimization in Engineering from Springer. Dr. Behjat has been developing new and innovative methods to teach EDA to students. Her work has been published in American Society of Engineering Education (ASEE) and Grace Hopper Celebration of Women in Engineering. She won the University of Calgary, Electrical and Computer Engineering Graduate Educator Award in 2015. Dr. Behjat received the Women in Engineering and Geoscience Award from APEGA in 2015 in recognition of her work in promoting gender and diversity in engineering.


System Design Contest at DAC 2022

Please refer to the official webpage.

The DAC System Design Contest focuses on low-power object detection on an embedded FPGA system. Contestants will receive a training dataset provided by DJI, and a hidden dataset will be used to evaluate the performance of the designs in terms of accuracy and power. Contestants will compete to create the best performing design on a Ultra 96 v2 FPGA board. Grand cash awards will be given to the top three teams. The award ceremony will be held at the 2022 IEEE/ACM Design Automation Conference.

Contest Organizers

Jeff GoedersBrigham Young University
Callie HaoGeorgia Institute of Technology
Cheng ZhuoZhejiang University
Naveen PurushothamXilinx