DASS at DAC 2018

The Design Automation Summer School (DASS) is a one-day intensive course on research and development in design automation (DA). Each topic in this course will be covered by a distinguished speaker who will define the topic, describe recent accomplishments, and indicate remaining challenges. Interactive discussions and follow-up activities among the participants will be used to reinforce and expand upon the lessons. This program is intended to introduce and outline emerging challenges, and to foster creative thinking in the next generation of EDA engineers. Simultaneously, they also help the students hone their problem solving, programming, and teamwork skills, in addition to fostering long-term collégial relationships. The 2018 SIGDA Design Automation Summer School is co-hosted by A. Richard Newton Young Fellowship Program at ACM/IEEE Design Automation Conference (DAC). DASS program will be co-hosted by DAC RNYS program and will be held on Sunday June 24, 2018 at Room 30003, Moscone Center West, from 9 a.m. to 6 p.m. in San Francisco, California. Richard Newton Young Student Fellowship Welcome breakfast is held at the same room from 7:30 am to 8:30 am. All the students receiving the fellowship (excluding the mentors) are required to attend DASS event.
 
The DASS event complements other educational and professional development activities in design automation including outreach projects such as the SIGDA University Booth, the CADathlon, and the Design Automation Conference (DAC) Ph.D. forum that have met with tremendous success over the past decade. Note that there is no separate call for participation for DASS. Attending DASS is mandatory for all the students receiving the Richard Newton Young Fellowship. The DASS final program will be available in late April 2018.
 
Organizing Committee:

• Yier Jin (Univ. of Central Florida, Gainesville, FL) (yier.jin@eecs.ucf.edu)
• Muhammad Shafique (TU Wien, Vienna, Austria) (muhammad.shafique@tuwien.ac.at)
• Jaytita Das (Intel Corp., Hillsboro, OR) (jayita.365@gmail.com)

 
SIGDA advisory committee for DASS:

• Yiran Chen (Duke University) (yiran.chen@duke.edu)

DASS Schedule

• Date: Sunday June 24, 2018
• Time: 7:30am – 6:00pm
• Location: Room 3003, Moscone Center West, San Francisco, California

The detailed schedule is listed below:

 
Invited Talks

• Title: Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation
  Spaeker: Onur Mutlu (ETH Zürich)
  Abstract: Today’s systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in systems that cause performance, scalability and energy bottlenecks: 1) data access from memory is already a key bottleneck as applications become more data-intensive and memory bandwidth and energy do not scale well, 2) energy consumption is a key constraint in especially mobile and server systems, 3) data movement is very expensive in terms of bandwidth, energy and latency, much more so than computation. These trends are especially severely-felt in the data-intensive server and energy-constrained mobile systems of today. At the same time, conventional memory technology is facing many scaling challenges in terms of reliability, energy, and performance. As a result, memory system architects are open to organizing memory in different ways and making it more intelligent, at the expense of slightly higher cost. The emergence of 3D-stacked memory plus logic as well as the adoption of error correcting codes inside the latest DRAM chips are an evidence of this trend. In this lecture, I will discuss some recent research that aims to practically enable computation close to data. After motivating trends in applications as well as technology, we will discuss at least two promising directions: 1) performing massively-parallel bulk operations in memory by exploiting the analog operational properties of DRAM, with low-cost changes, 2) exploiting the logic layer in 3D-stacked memory technology in various ways to accelerate important data-intensive applications. In both approaches, we will discuss relevant cross-layer research, design, and adoption challenges in devices, architecture, systems, applications, and programming models. Our focus will be the development of in-memory processing designs that can be adopted in real computing platforms and real data-intensive applications, spanning machine learning, graph processing and genome analysis, at low cost. We will also discuss and describe simulation and evaluation infrastructures that can enable exciting and forward-looking research in future memory systems, including Ramulator and SoftMC.
  Biography: Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the William D. and Nancy W. Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, and bioinformatics. He is especially interested in interactions across domains and between applications, system software, compilers, and microarchitecture, with a major current focus on memory and storage systems. A variety of techniques he, together with his group and collaborators, have invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. His industrial experience spans starting the Computer Architecture Group at Microsoft Research (2006-2009), and various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, faculty partnership awards from various companies, a healthy number of best paper or “Top Pick” paper recognitions at various computer systems and architecture venues, and the ACM Fellow recognition “for contributions to computer architecture research, especially in memory systems.” His computer architecture course lectures and materials are freely available on YouTube, and his research group makes software artifacts freely available online. For more information, please see his webpage at http://people.inf.ethz.ch/omutlu/.
   
• Title: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems
  Speaker: Kaushik Roy (Purdue University)
  Abstract: Advances in machine learning, notably deep learning, have led to computers matching or surpassing human performance in several cognitive tasks including vision, speech and natural language processing. However, implementation of such neural algorithms in conventional “von-Neumann” architectures are several orders of magnitude more energy expensive than the biological brain. Hence, we need fundamentally new approaches to sustain exponential growth in performance at high energy-efficiency beyond the end of the CMOS roadmap in the era of ‘data deluge’ and emergent data-centric applications. Exploring the new paradigm of computing necessitates a multi-disciplinary approach: exploration of new learning algorithms inspired from neuroscientific principles, developing network architectures best suited for such algorithms, new hardware techniques to achieve orders of improvement in energy consumption, and nanoscale devices that can closely mimic the neuronal and synaptic operations of the brain leading to a better match between the hardware substrate and the model of computation. In this presentation, I will discuss recent developments in CMOS and non-CMOS devices and architectures for implementing brain-inspired hardware. Implementation of different neural operations with varying degrees of bio-fidelity (from “non-spiking” to “spiking” networks) and implementation of on-chip learning mechanisms (Spike-Timing Dependent Plasticity) will be discussed. Additionally, we also show probabilistic neural and synaptic computing platforms that can leverage the underlying stochastic device physics of spin-devices due to thermal noise. System-level simulations indicate ~100x improvement in energy consumption for spin-based neural computing over a corresponding CMOS implementation across different computing workloads. Complementary to the above efforts, I will also present different learning algorithms including stochastic learning with one-bit synapses that greatly reduces the storage/bandwidth requirement while maintaining competitive accuracy, and adaptive online learning that efficiently utilizes the limited memory and resource constraints to learn new information without catastrophically forgetting already learnt data.
  Biography: Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. He also the director of the center for brain-inspired computing (C-BRIC) funded by SRC/DARPA. His research interests include neuromorphic and emerging computing models, neuro-mimetic devices, spintronics, device-circuit-algorithm co-design for nano-scale Silicon and non-Silicon technologies, and low-power electronics. Dr. Roy has published more than 700 papers in refereed journals and conferences, holds 18 patents, supervised 75 PhD dissertations, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award (Charles Doeser Award), Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD Vannevar Bush Faculty Fellow (2014-2019), Semiconductor Research Corporation Aristotle award in 2015, and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay) and Global Foundries visiting Chair at National University of Singapore. He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings — Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.
   
• Title: From EDA to ’42’
  Speaker: Sani Nassif (Radyalis)
  Abstract: No field in Engineering has had the sustained exponential that was Moore’s Law. One of the outcomes is a rich culture of “using computers to automate the design of computers”, namely EDA, which has had to rapidly adapt to ever larger complexity. But with Moore’s era now over, it is time to apply the energy of the EDA community to other areas. This talk will explore the application of EDA techniques and knowhow to the area of Cancer Radiation Therapy, and specific technical problems that are of great interest to the Oncologists will be related to EDA and other areas of work like Big Data.
  Biography: Sani received his Bachelors degree with Honors from the American University of Beirut in 1980, and his Masters and PhD degrees from Carnegie-Mellon University in 1981 and 1986 respectively. He then worked for ten years at Bell Laboratories in the general area of technology CAD, focusing on various aspects of design and technology coupling including device modeling, parameter extraction, worst case analysis, design optimization and circuit simulation. While at Bell Labs, working under Larry Nagel -the original author of Spice, he led a large team in the development of an in-house circuit simulator, named Celerity, which became the main circuit simulation tool at Bell Labs. In January 1996, he joined the then newly formed IBM Austin Research Laboratory (ARL), which was founded with a specific focus on research for the support of IBM’s Power computer systems. After twelve years of management, he stepped down to focus on technical work again with an emphasis on applying techniques developed in the VLSI-EDA area to IBM’s Smarter Planet initiative. In January 2014 Sani founded Radyalis, a company focused on applying VLSI-EDA techniques to the field of Cancer Radiation Therapy. Sani has authored one book, many book chapters, and numerous conference and journal publications. He has delivered many tutorials at top conferences and has received Best Paper awards from TCAD, ICCAD, DAC, ISQED, ICCD and SEMICON, authored invited papers to ISSCC, IEDM, IRPS, ISLPED, HOTCHIPS, and CICC. He has given Keynote and Plenary presentations at Sasimi, ESSCIRC, BMAS, SISPAD, SEMICON, VLSI-SOC, PATMOS, NMI, ASAP, GLVLSI, TAU, ISVLSI and DATE. He is an IEEE Fellow, was a member of the IBM Academy of Technology, a member of the ACM and the AAAS, and an IBM master inventor with more than 75 patents. He was the president of the IEEE Council on EDA (CEDA) for 2014 and 2015.
   
• Title: An overview of RISC-V CPU Core implementation and sign-off using EDA management system
  Speaker: Kunal Ghosh (VSD)
  Abstract:
  A good backend/full flow session
  VSDFlow is a ‘plug-n-play’ EDA management system, built for chip designers to implement their ideas and convert to GDSII. ‘Plug-n-Play’ refers to switching between any eda tools, for eg. user can plug Cadence Genus for synthesis, Synopsys ICC for PNR and Tempus for sign-off STA. The output report will provide a QOR of entire design, which forms the starting point for design analysis. In this session, we will present how this management system works, how other tools (like Qflow and Opentimer) can be plugged in, and the full flow results on medium sized designs like picoRV32 – a RISC-V cpu core that implements RV32I instruction set
  VSD stands for VLSI System Design (name of our company)
  More references
  https://www.vlsisystemdesign.com/wp-content/uploads/2017/10/conference_p…
  Students can download for free, though there is a online course as well
  ‘vsdflow’ – A plug-n-play EDA management system (EMS)
  Kunal Ghosh, VLSI System Design Corp. Pvt. Ltd.
  Qflow: A flexible open source tool flow for digital synthesis of ASIC designs R. Timothy Edwards, eFabless.com
  Opentimer: An open-source high-performance timing analysis tool for large designs
  Tsung-wei Huang, Martin Wong, UIUC
  Biography: Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm’s Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.
   
• Title: Security Evaluation of System-on-Chip (SoC) Products
  Speaker: Seetharam Narasimhan (Intel)
  Abstract: With the rapid proliferation of computation and connectivity in a wide variety of devices, ranging from the edge to the cloud, we are rapidly entering the era of the Internet of Things. However, underlying the desire to have all things smart and connected is the overarching fear of security breaches and loss of privacy, which are also becoming commonplace news. Security is no longer considered as an after-thought during the design and development lifecycle of System-on-Chip (SoC) products. In this talk, we shall focus on the hardware security aspects of SoCs and how a systematic evaluation at different stages of the product lifecycle (architecture, design implementation and validation) can help reduce the risk of security vulnerabilities. Proper threat modeling and iterative security-oriented design reviews can be powerful tools in preventing security loopholes, while pre- and post-silicon security validation can be used to detect any implementation issues which lead to security vulnerabilities. We shall use synthetic examples to examine how automated frameworks and evaluation tools can help in finding these issues early and mitigating their impact. We shall also highlight the challenges and research opportunities in this field.
  Biography: Seetharam Narasimhan is a Security Researcher (architect) at the Security Center of Excellence, Platform Architecture Group of Intel Corporation, Hillsboro, Oregon, USA. He has a Ph.D. in Computer Engineering from Case Western Reserve University (USA) and a B.E. (Hons.) in Electronics and Telecommunication Engineering from Jadavpur University (India). His research interests include: Hardware Security, Ultralow power and reliable nanoscale circuits, as well as Bio-medical circuits and systems. He is the co-author of three book chapters, and more than 40 publications in international journals and conferences of repute.
   
• Title: Give a Winning Presentation: From Idea to Delivery
  Speaker: Laleh Behjat (University of Calgary)
  Biography: Dr. Laleh Behjat is a Professor in the department of Electrical and Computer Engineering, Schulich School of Engineering, University of Calgary. She joined the University of Calgary in 2002. Dr. Behjat’s research focus is on developing EDA techniques for physical design and application of large scale optimization in EDA. Her research team has won several awards including 1st and 2nd places in ISPD 2014 and ISPD 2015 High Performance Routability Driven Placement Contests and 3rd place in DAC Design Perspective Challenge in 2015. She is an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and Optimization in Engineering from Springer. Dr. Behjat has been developing new and innovative methods to teach EDA to students. Her work has been published in American Society of Engineering Education (ASEE) and Grace Hopper Celebration of Women in Engineering. She won the University of Calgary, Electrical and Computer Engineering Graduate Educator Award in 2015. Dr. Behjat received the Women in Engineering and Geoscience Award from APEGA in 2015 in recognition of her work in promoting gender and diversity in engineering.