SESSION: Keynote Address

Session details: Keynote Address

  • Chu

Challenges and Opportunities in Automotive, Industrial, and IoT Physical Design

  • Hill
    Anthony M.

Taping out modern, complex SOCs presents a myriad of challenges in physical design.
Doing so for demanding markets such as automotive, industrial, and IoT multiplies
that complexity. In this talk we will take a broad look across the physical design

SESSION: Finding the Golden Tree in the Forest!

Session details: Finding the Golden Tree in the Forest!

  • Yeap

Wot the L: Analysis of Real versus Random Placed Nets, and Implications for Steiner Tree Heuristics

  • Kahng
    Andrew B.

The NP-hard Rectilinear Steiner Minimum Tree (RSMT) problem has been studied in the
VLSI physical design literature for well over three decades. Fast estimators of RSMT
cost (which reflects routed wirelength) are a required ingredient of modern physical

Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees

  • Alpert
    Charles J.

The Prim-Dijkstra (PD ) construction [1] was first presented over 20 years ago as a way to efficiently
trade off between shortest-path and minimum-wirelength routing trees. This approach
has stood the test of time, having been integrated into leading …

Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid

  • Lin
    Sheng-En David

Given a set of pins, a Rectilinear Steiner Minimum Tree (RSMT) connects the pins using
only rectilinear edges with the minimum wirelength. RSMT construction is heavily used
at various design steps such as floorplanning, placement, routing, and …

SESSION: FPGA Special Session

Session details: FPGA Special Session

  • Das

Challenges in Large FPGA-based Logic Emulation Systems

  • Hung
    William N.N.

Functional verification is an important aspect of electronic design automation. Traditionally,
simulation at the register transfer-level has been the mainstream functional verification
approach. Formal verification and various static analysis checkers …

Flexibility: FPGAs and CAD in Deep Learning Acceleration

  • Chiu
    Gordon R.

Deep learning inference has become the key workload to accelerate in our AI-powered
world. FPGAs are an ideal platform for the acceleration of deep learning inference
by combining low-latency performance, power-efficiency, and flexibility. This paper

Exploration and Tradeoffs of different Kernels in FPGA Deep Learning Applications

  • Delaye

In the field of deep learning, efficient computational hardware has come to the forefront
of the large scale implementation and deployment of many applications. In the process
of designing hardware, various characteristics of hardware platforms have …

Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source
CGRA-ME Framework

  • Chin
    S. Alexander

We describe an open-source software framework,CGRA-ME, for the modeling and exploration
of coarse-grained reconfigurable architectures (CGRAs). CGRAs are programmable hardware
devices having large ALU-like logic blocks, and datapath bus-style inter-…

SESSION: Design Flow and Power Grid Optimization

Session details: Design Flow and Power Grid Optimization

  • Iyer

Concurrent High Performance Processor Design: From Logic to PD in Parallel

  • Stok

The design of a high-performance processor in an advanced technology node is a highly
concurrent process. While most SoCs are designed with (fairly) stable IP, several
trends are driving the design of the micro-architecture, the logic and the physical

Towards a VLSI Design Flow Based on Logic Computation and Signal Distribution

  • Reis

This paper discusses directions for a VLSI design flow based on a novel paradigm of
local logic computation and global signal distribution. In the last years there has
been an increasing effort to perform a better integration between logic synthesis
and …

Power Grid Reduction by Sparse Convex Optimization

  • Ye

With the dramatic increase in the complexity of modern integrated circuits (ICs),
direct analysis and verification of IC power distribution networks (PDNs) have become
extremely computationally expensive. Various power grid reduction methods are …

SESSION: Statistical and Machine Learning-Based CAD

Session details: Statistical and Machine Learning-Based CAD

  • Kissiov

Machine Learning Applications in Physical Design: Recent Results and Directions

  • Kahng
    Andrew B.

In the late-CMOS era, semiconductor and electronics companies face severe product
schedule and other competitive pressures. In this context, electronic design automation
(EDA) must deliver “design-based equivalent scaling” to help continue essential …

Machine Learning for Feature-Based Analytics

  • Wang

Applying machine learning in Electronic Design Automation (EDA) has received growing
interests in recent years. One approach to analyze data in EDA applications can be
called feature-based analytics. In this context, the paper explains the inadequacy
of …

Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning

  • Lin

Lithography simulation is one of the key steps in physical verification, enabled by
the substantial optical and resist models. A resist model bridges the aerial image
simulation to printed patterns. While the effectiveness of learning-based solutions

SESSION: Three Shades of Placement!

Session details: Three Shades of Placement!

  • Shinnerl

Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs

  • Ku
    Bon Woong

The recent advancement of wafer bonding technology offers fine-grained and silicon-space
overhead-free 3D interconnections in face-to-face (F2F) bonded 3D ICs. In this paper,
we propose a full-chip RTL-to-GDSII physical design solution to build high-…

Analog Placement Constraint Extraction and Exploration with the Application to Layout

  • Xu

In analog/mixed-signal (AMS) integrated circuits (ICs), most of the layout design
efforts are still handled manually, which is time-consuming and error-prone. Given
the previous high-quality manual layouts containing valuable design expertise of …

Pin Assignment Optimization for Multi-2.5D FPGA-based Systems

  • Kuo

Advanced 2.5D FPGAs with larger logic capacity and higher pin counts compared to conventional
FPGAs are commercially available. Some multi-FPGA systems have already utilized 2.5D
FPGAs. Commercial 2.5D FPGA consists of multiple dies connected through an …

SESSION: Commemoration for Professor Te Chiang Hu

Session details: Commemoration for Professor Te Chiang Hu

  • Kahng
    Andrew B.

Influence of Professor T. C. Hu’s Works on Fundamental Approaches in Layout

  • Kahng
    Andrew B.

Professor T. C. Hu has made numerous pioneering and fundamental contributions in combinatorial
algorithms, mathematical programming and operations research. His seminal 1985 IEEE
book VLSI Circuit Layout: Theory and Design, coedited with Prof. E. S. Kuh,…

Tree Structures and Algorithms for Physical Design

  • Cheng

Tree structures and algorithms provide a fundamental and powerful data abstraction
and methods for computer science and operations research. In particular, they enable
significant advancement of IC physical design techniques and design optimization.
For …

Pioneer Research on Mathematical Models and Methods for Physical Design

  • Chu

In the inaugural International Symposium on Physical Design (ISPD) at 1997, Prof.
Te Chiang Hu has delivered the keynote address “Physical Design: Mathematical Models
and Methods” [1]. Without any question, Prof. Hu has made a lot of foundational and

Theory and Algorithms of Physical Design

  • Cheng

SESSION: Interconnect Optimization and Detailed Routing Contest Results

Session details: Interconnect Optimization and Detailed Routing Contest Results

  • Yan

Interconnect Optimization Considering Multiple Critical Paths

  • Hu

Interconnect optimization, including buffer insertion and Steiner tree construction,
continues to be a pillar technology that largely determines overall chip performance.
Buffer insertion algorithms in published literature are mostly focused on …

Interconnect Physical Optimization

  • Janac
    K. Charles

The SoC Interconnect is one of the most important IPs in modern chips as it is the
logical and physical instantiation of an SoC architecture and carries virtually all
the SoC data. Interconnect IPs have to carry non-coherent, cache coherent, subsystem

ISPD 2018 Initial Detailed Routing Contest and Benchmarks

  • Mantik

In advanced technology nodes, detailed routing becomes the most complicated and runtime
consuming stage. To spur detailed routing research, ISPD 2018 initial detailed routing
contest is hosted and it is the first ISPD contest on detailed routing …

SESSION: How to Make Your Foundry Happier?

Session details: How to Make Your Foundry Happier?

  • Hu

The Pressing Need for Electromigration-Aware Physical Design

  • Lienig

Electromigration (EM) is becoming a progressively intractable design challenge due
to increased interconnect current densities. It has changed from something designers
“should” think about to something they “must” think about, i.e., it is now a definite

On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple
Patterning Techniques

  • Lvov

The continued delay of higher resolution alternatives for lithography, such as EUV,
is forcing the continued adoption of multi-patterning solutions in new technology
nodes, which include triple and quadruple patterning using several lithography-etch

Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale

  • Viera
    Raphael A.C.

Designing secure integrated systems requires methods and tools dedicated to simulating
that early design stages’ the effects of laser-induced transient faults maliciously
injected by attackers. Existing methods for simulation of laser-induced transient

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