SESSION: Welcome and Keynote Address

Technology Options for Beyond-CMOS

  • Young

CMOS integrated circuit technology for computation is at an inflexion point. Although
this is the technology which has enabled the semiconductor industry to make vast progress
over the past 30-plus years, it is expected to see challenges going beyond …

SESSION: Machine Learning in EDA

The Quest for The Ultimate Learning Machine

  • Dubey

Traditionally, there has been a division of labor between computers and humans where
all forms of number crunching and bit manipulations are left to computers; whereas,
intelligent decision-making is left to us humans. We are now at the cusp of a major

Deep Learning in the Enhanced Cloud

  • Chung

Deep Learning has emerged as a singularly critical technology for enabling human-like
intelligence in online services such as Azure, Office 365, Bing, Cortana, Skype, and
other high-valued scenarios at Microsoft. While Deep Neural Networks (DNNs) have …

Bilinear Lithography Hotspot Detection

  • Zhang

Advanced semiconductor process technologies are producing various circuit layout patterns,
and it is essential to detect and eliminate problematic ones, which are called lithography
hotspots. These hotspots are formed due to light diffraction and …

Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine

  • Chan
    Wei-Ting J.

Design rule check (DRC) violations after detailed routing prevent a design from being
taped out. To solve this problem, state-of-the-art commercial EDA tools global-route
the design to produce a global-route congestion map; this map is used by the …

SESSION: Monday Afternoon Keynote

Pushing the boundaries of Moore’s Law to transition from FPGA to All Programmable

  • Bolsens

Since their inception, FPGAs have changed significantly in their capacity and architecture.
The devices we use today are called upon to solve problems in mixed-signal, high-speed
communications, signal processing and compute acceleration that early …

POSTER SESSION: Invited Poster Presentation

How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library

  • Fontana

Similarly to game engines, physical design tools must handle huge amounts of data.
Although the game industry has been employing modern software development concepts
such as data-oriented design, most physical design tools still relies on object-…

Rsyn: An Extensible Physical Synthesis Framework

  • Flach

Due to the advanced stage of development on EDA science, it has been increasingly
difficult to implement realistic software infrastructures in academia so that new
problems and solutions are tested in a meaningful and consistent way. In this paper
we …

SESSION: Nontraditional Physical Design Challenges

Research Challenges in Security-Aware Physical Design

  • Karri

The presentation will discuss security techniques such as IC camouflaging and logic

Challenges and Opportunities: From Near-memory Computing to In-memory Computing

  • Khoram

The confluence of the recent advances in technology and the ever-growing demand for
large-scale data analytics created a renewed interest in a decades-old concept, processing-in-memory
(PIM). PIM, in general, may cover a very wide spectrum of compute …

Physical Design Considerations of One-level RRAM-based Routing Multiplexers

  • Tang

Resistive Random Access Memory(RRAM) technology opens the opportunity for granting both high-performance and low-power
features to routing multiplexers. In this paper, we study the physical design considerations
related to RRAM-based routing …

Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits

  • Xu

High-performance analog integrated circuits usually require minimizing critical parasitic
loading, which can be modeled by the critical net wire length in the layout stage.
In order to reduce post-layout circuit performance degradation, critical net …

SESSION: Tuesday Keynote Address

Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling

  • Lu

In the advanced process technologies of 7nm and beyond, the semiconductor industry
faces several new challenges: (1) aggressive chip area scaling with economically feasible
process technology development, (2) sufficient performance enhancement of …

SESSION: Clock and Timing

Modern Challenges in Constructing Clocks

  • Alpert
    Charles J.

Clock Tree Construction based on Arrival Time Constraints

  • Ewetz

There are striking differences between constructing clock trees based on dynamic implied
skew constraints and based on static arrival time constraints. Dynamic implied skew
constraints allow the full timing margins to be utilized, but the constraints …

A Fast Incremental Cycle Ratio Algorithm

  • Wu

In this paper, we propose an algorithm to quickly find the maximum cycle ratio (MCR)
on an incrementally changing directed cyclic graph. Compared with traditional MCR
algorithms which have to recalculate everything from scratch at each incremental …

iTimerM: Compact and Accurate Timing Macro Modeling for Efficient Hierarchical Timing Analysis

  • Lee

As designs continue to grow in size and complexity, EDA paradigm shifts from flat
to hierarchical timing analysis. In this paper, we propose compact and accurate timing
macro modeling, which is the key to achieve efficient and accurate hierarchical …

SESSION: Routability Considerations

DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment

  • Ou

Directed self-assembly (DSA) is a promising solution for fabrication of contacts and
vias for advanced technology nodes. In this paper, we study a DSA aware detailed routing
problem, where DSA guiding pattern assignment and guiding pattern double …

Automatic Cell Layout in the 7nm Era

  • Cremer

Multi patterning technology used in 7nm technology and beyond imposes more and more
complex design rules on the layout of cells. The often non local nature of these new
design rules is a great challenge not only for human designers but also for existing

Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells

  • Shi

We study the impact of using 3D monolithic (3DM) standard cells on improving detailed
routability and pin access. We propose a design flow which transforms standard rows
of single-tier “2D” cells into rows of standard 3DM cells folded into two tiers. …

SESSION: Commemoration for Professor Satoshi Goto

The Spirit of in-house CAD Achieved by the Legend of Master “Prof. Goto” and his Apprentices

  • Nakamura

In this paper, a legend story to develop CAD algorithms and CAD/EDA tools for NEC’s
in-house use is described. About 30 years ago, since there are few commercial CAD
tools, ICT vendors had to develop their own CAD tools to enhance the performance of

Generalized Force Directed Relaxation with Optimal Regions and Its Applications to
Circuit Placement

  • Chang
    Yao Wen

This paper introduces popular algorithmic paradigms for circuit placement, presents
Goto’s classical placement framework based on the generalized force directed relaxation
(GFDR) method with an optimal region (OR) formulation and its impacts on modern …

100x Evolution of Video Codec Chips

  • Zhou

In the past two decades, there has been tremendous progress in video compression technologies.
Meanwhile, the use of these technologies, along with the ever-increasing demand for
emerging ultra-high-definition applications greatly challenges the design …

Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond

  • Kang

Innovations and advancements on physical design (PD) in the past half century significantly
contribute to the progresses of modern VLSI designs. While “Moore’s Law” and “Dennard
Scaling” have become slowing down recently, physical design society …

Past, Present and Future of the Research

  • Goto

SESSION: Optimization and Placement

Interesting Problems in Physical Synthesis

  • Ho

It is a misperception that the Chinese have the same word for crisis as opportunity.
Despite that, a technical crisis does present opportunities for researchers and practitioners
to solve interesting problems. In this talk we point out two crises: …

Pin Accessibility-Driven Detailed Placement Refinement

  • Ding

The significantly increased number of routing design rules at sub-20nm nodes has made
pin access one of the most critical challenges in detailed routing. Resolving pin
access issues in detailed routing stage may be too late due to the fixed pin …

A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing
Maximum Movement

  • Karimpour Darav

The standard-cell placement legalization problem has become critical due to increasing
design rule complexity and design utilization at 16nm and lower technology nodes.
An ideal legalization approach should preserve the quality of the input placement
in …


CAD Opportunities with Hyper-Pipelining

  • Iyer
    Mahesh A.

Hyper-pipelining is a design technique that results in significant performance and
throughput improvements in latency-insensitive designs. Modern FPGA architectures
like Intel’s Stratix®10 feature a revolutionary register-rich HyperFlex? core fabric

An Effective Timing-Driven Detailed Placement Algorithm for FPGAs

  • Dhar

In this paper, we propose a new timing-driven detailed placement technique for FPGAs
based on optimizing critical paths. Our approach extends well beyond the previously
known critical path optimization approaches and explores a significantly larger …

Clock-Aware FPGA Placement Contest

  • Yang

Modern FPGA device contains complex clocking architecture on top of FPGA logic fabric.
To best utilize FPGA clocking architecture, both FPGA designers and EDA tool developers
need to understand the clocking architecture and design best methodology/…