ACM/IEEE A. Richard Newton Technical Impact Award in EDA

Description

The ACM/IEEE A. Richard Newton Technical Impact Award honors an individual or group of individuals for an outstanding technical contribution within the scope of electronic design automation, as evidenced by a peer-reviewed paper published at least ten years prior to the presentation of the award (i.e., published before July 2015). The award recognizes work whose long-term influence has had a significant and lasting impact on the EDA field.

The award includes a USD 1,500 honorarium to be shared among the authors, along with a plaque for each author. The award is jointly funded by the IEEE Council on Electronic Design Automation and the ACM Special Interest Group on Design Automation (SIGDA).

The award is presented annually at the Design Automation Conference (DAC).

Historical Background

A. Richard Newton, one of the foremost pioneers and leaders of the electronic design automation field, passed away on 2 January 2007 at the age of 55. He served as Professor and Dean of the College of Engineering at the University of California, Berkeley.

Dr. Newton was educated at the University of Melbourne, where he received his bachelor’s degree in 1973 and master’s degree in 1975. In the early 1970s, he began working on SPICE, a circuit simulation program originally developed by Larry Nagel and Donald Pederson, enabling fast and accurate analysis of complex electronic circuits. He earned his Ph.D. in electrical engineering and computer sciences from UC Berkeley in 1978.

For his research and entrepreneurial contributions to the EDA industry, Dr. Newton received the Phil Kaufman Award in 2003. He was elected to the National Academy of Engineering in 2004 and to the American Academy of Arts and Sciences in 2006. He was a member of the Association for Computing Machinery and a Fellow of the Institute of Electrical and Electronics Engineers.

Basis for Judging

The primary consideration for this award is the impact of the nominated work on technology, industry, education, and practicing designers and engineers in electronic design automation. Impact may include inspiring subsequent research, influencing industrial practice, or achieving widespread adoption in real-world systems.

Eligibility

The nominated paper must have undergone peer review prior to publication and must be an archived conference or journal publication published by or available through ACM or IEEE. The paper must be a seminal work in which an original idea was first introduced. Follow-up papers and extended descriptions may be cited in the nomination, but the award is given for the initial original contribution.

Nomination Package

The nomination package should include a one-page nomination letter describing the impact of the nominated paper, evidence supporting that impact, a brief biography of the nominator, up to three endorsement letters, and a copy of the nominated paper. All materials should be combined into a single PDF file.

Schedule

The nomination deadline for the 2025 ACM/IEEE A. Richard Newton Technical Impact Award was 21 March 2025, and the nomination process for the 2025 award is now closed.

Please stay tuned for the call for nominations for the 2026 award, which will be announced through SIGDA communication channels.

Past Awardees

2024Mircea Stan and Wayne Burleson“Bus-Invert Coding for Low-Power I/O”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 3, No. 1, pp. 49-58, March 1995.
2023Moshe Vardi and Pierre Wolper“An Automata-Theoretic Approach to Automatic Program Verification”, in the proceedings of the 1st Symposium on Logic in Computer Science, 1986.
2022Ricardo Telichevesky, Kenneth S. Kundert, and Jacob K. White“Efficient Steady-State Analysis based on Matrix-Free Krylov-Subspace Methods”, in the proceedings of the 32nd Design Automation Conference, 1995.
2021John A. Waicukauski, Eric Lindbloom, Barry K. Rosen, and Vijay S. Iyengar“Transition Fault Simulation,” IEEE Design & Test of Computers, Vol. 4, no. 2, April 1987
2020Luca Benini and Giovanni De Micheli“Networks on Chips: A New SoC Paradigm,” IEEE Computer, pp. 70-78, January 2002.
2019E. B. Eichelberger and T. W. Williams“A Logic Design Structure for LSI Testability,” in the proceedings of the 14th Design Automation Conference, 1977.
2018Hans Eisenmann and Frank M. Johannes“Generic Global Placement and Floorplanning,” in the proceedings of the 35th Design Automation Conference, 1998.
2017Matthew W. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, and Sharad Malik“Chaff: Engineering an Efficient SAT Solver,” in the proceedings of the 38st Design Automation Conference, 2001.
2016Chandu Visweswariah, Kaushik Ravindran, Kerim Kalafala, Steven G. Walker, and Sambasivan Narayan“First-Order Incremental Block-Based Statistical Timing Analysis,” in the proceedings of the 41st Design Automation Conference, 2004.
2015Blaise Gassend, Dwaine Clarke, Marten van Dijk, and Srinivas Devadas“Silicon Physical Random Functions,” in the proceedings of the 9th ACM Conference on Computer and Communications Security (CCS), 2002.
2014Subhasish Mitra and Kee Sup Kim“X-compact: an efficient response compaction technique for test cost reduction,” IEEE International Test Conference, 2002.
2013Keith Nabors and Jacob White“FastCap: A multipole accelerated 3-D capacitance extraction program,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 10, Issue 11 (1991): 1447-1459.
2012Altan Odabasioglu, Mustafa Celik, and Larry Pileggi“PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Aug., 1998.
2011Jason Cong and Eugene Ding“FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jan., 1994.
2010Randal Bryant“Graph-based algorithms for Boolean function manipulation” IEEE Transactions on Computers, Aug., 1986.
2009Robert K. Brayton, Richard Rudell, Alberto Sangiovanni-Vincentelli, and Albert R. Wang“MIS: A Multiple-Level Logic Optimizations System,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Nov., 1997.