Participants and Topics

The Ph. D. forum at DAC is hosted by SIGDA during their member meeting on Tuesday, June 22, 7-9, immediately after and adjacent to the DAC Cocktail party. Please join us then to prereview the students' work and to share with them your feedback. The forum is OPEN to all members of the DA community.

Thanks for the help of many reviewers who provided valuable feedback in evaluating the '99 submissions. The forum was organized by Soha Hassoun, Tufts University.

 

Power Estimation &Low Power Design	Analog, Logic,  & Behavioral Synthesis	Physical Design	Interconnect & Component Modeling
Rita Yu Chen David Garrett	Naga Dhanwada Balakrishna Kumthekar Jinan Lou Luc Semeria Tyler Thorp	Patrick Hung Gi-Joon Nam	Chris Chu Youxin Gao Alessandra Nardi David Pan

Power Estimation & Low Power Design

• Rita Yu Chen, Penn State University
  • Title:  Architectural Level Power Estimation for System-on-a-Chip
  • Advisor: Mary Jane Irwin
  • URL: www.cse.psu.edu/~yuchen
    
    
• David Garrett, University of Virginia
  • Title:  CMOS Circuits with Reduced Dynamic Power Consumption
  • Advisor: Mircea Stan
  • URL: csis.ee.virginia.edu/~dcg3w

• Naga Shyamala R. Dhanwada, University of Cincinnati
  • Title:  Constraint Transformation Techniques for the Synthesis of Analog Systems
  • Advisor: Ranga Vemuri
  • URL: www.ececs.uc.edu/~nagu

   
   

• Balakrishna Kumthekar, University of Colorado, Boulder.
  • Title:  Structural and Functional Flexibilities for Power Optimization in FPGAs
  • Advisor: Fabio Somenzi
  • URL: vlsi.colorado.edu/~kumtheka

   
   

• Jinan Lou, University of Southern California
  • Title:  Integration of Logical and Physical Designs for Deep Submicron Circuits
  • Advisor:  Massoud Pedram
  • URL: atrak.usc.edu/~jlou

   
   

• Luc Semeria, Stanford University
  • Title:  Hardware synthesis from C/C++ models
  • Advisor:  Giovanni De Micheli
  • URL: azur.stanford.edu/~lucs/

   
   

• Tyler Thorp, University of Washington
  • Title:  Synthesis of Dynamic Circuits
  • Advisor:  Carl Sechen
  • URL: twolf.ee.washington.edu/~thorp

   
   

• Patrick Hung, Stanford University
  • Title:  Floorplanning for GHz Processors
  • Advisor:  Michael J. Flynn
  • URL: umunhum.stanford.edu/~hung/research/

   
   

• Gi-Joon Nam, University of Michigan
  • Title:  An Exploration of Physical Design Problems Via Boolean Satisfiability (SAT)
  • Advisor: Karem A. Sakallah
  • URL: www.eecs.umich.edu/~criteria

   
   

• Chris Chong-Nuen Chu, The University of Texas at Austin
  • Title:  Interconnect optimization for high-performance VLSI
  • Advisor: Martin D. F. Wong
  • URL: www.cs.utexas.edu/users/cnchu

   
   

• Youxin Gao, University of Texas at Austin
  • Title:  Interconnect Optimization in Deep Submicron VLSI Design
  • Advisor: Martin D.F. Wong
  • URL: www.cs.utexas.edu/users/gao

   
   

• Alessandra Nardi, Padova University, Italy
  • Title:  Realistic Worst Case Modeling Of Deep Sub-Micron CMOS Technologies
  • Advisor:  E. Zanoni
  • URL: www.dei.unipd.it

   
   

• David Zhigang Pan, UCLA
  • Title:  Interconnect Synthesis and Planning for High-Performance IC Designs
  • Advisor:  Jason Cong
  • URL: cadlab.cs.ucla.edu/~pan

   
   

• Steven Bashford, University of Dortmund, Germany
  • Title:  Constraint Driven Code Generation for Embedded Processors
  • Advisor: Peter Marwedel
  • URL: ls12-www.informatik.uni-dortmund.de/

   
   

• Bilung Lee, University of California, Berkeley
  • Title:  Specification and Design of Reactive Systems Using Finite State Machines
  • Advisor: Edward A. Lee
  • URL: ptolemy.eecs.berkeley.edu/~bilung

   
   

• Jianwen Zhu, University of California, Irvine
  • Title:  Behavioral Synthesis from an Extensible Object Oriented Language
  • Advisor:  Daniel D. Gajski
  • URL: www.ics.uci.edu/~jzhu

   
   

• Yumin Zhang, University of Notre Dame
  • Title:  Register Allocation For Low Power
  • Advisor: Xiaobo (Sharon) Hu, Danny Z. Chen
  • URL: www.nd.edu/~yzhang1

   
   

• Klaus Harbich, University of Hanover, Germany
  • Title:  Delay Optimized Hardware Implementation of Structural RT-level Circuit Descriptions into Heterogeneous SRAM-Based FPGA-Arrays
  • Advisor: Erich Barke
  • URL: www.ims.uni-hannover.de/~harbich 
     
• Jian Shen, the University of Texas at Austin
  • Title:  Effective Techniques for Processor Validation and Test
  • Advisor: Jacob A. Abraham
  • URL: www.ece.utexas.edu/~jshen

• Ric Chung-Yang Huang, University of California at Santa Barbara
  • Title:  RTL Design Verification
  • Advisor: Kwang-Ting (Tim) Cheng
  • URL: yellowstone.ece.ucsb.edu/~ric

   
   

• In-Ho Moon, University of Colorado at Boulder
  • Title:  Approximation and Don't Cares for Model Checking
  • Advisor:  Fabio Somenzi
  • URL: vlsi.colorado.edu/~mooni

   
   

• Shipra Panda, Carnegie Mellon University
  • Title:  Directed Simulation Using Trajectory Evaluation
  • Advisor:  Randal Bryant
  • URL: www.ece.cmu.edu/~spanda

   
   

• Miroslav N. Velev, Carnegie Mellon University
  • Title:  Formal Verification of Modern Microprocessors by Correspondence Checking
  • Advisor: Randy Bryant
  • URL: www.ece.cmu.edu/~mvelev