CADathlon 2022 Problem References

P1: “Memory controller enhancement via exploiting locality,” 

[1] S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, J. D. Owens, “Memory Access Scheduling”, ISCA ’00: pp 128-138.


P2: “Triple Patterning Aware Detailed Placement”

[1] Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles Alpert and David Z. Pan, “Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.34, no.5, pp.726-739, 2015.

P3: “Modularity optimization for synchronous block diagram”

[1] Peng Deng, Qi Zhu, Marco Di Natale, and Haibo Zeng, “Task Synthesis for Latency-sensitive Synchronous Block Diagram,” SIES 2014.

P4: ” Reliability-Driven Mixed-Precision Navigation”

[1] A. Mahmoud, T. Tambe, T. Aloui, D. Brooks and G. -Y. Wei, “GoldenEye: A Platform for Evaluating Emerging Numerical Data Formats in DNN Accelerators,” 2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2022, pp. 206-214, doi: 10.1109/DSN53405.2022.00031.

P5: “

Verifiable Execution of Deep Neural Networks”

[1] Zahra Ghodsi, Tianyu Gu, Siddharth Garg, “SafetyNets: Verifiable Execution of Deep Neural Networks on an Untrusted Cloud”, In Advances in Neural Information Processing Systems, 2017. 

P6: “Deciphering Secret Key for Provably-Secure Logic Locking Techniques” 

[1] S. Patnaik, N. Limaye and O. Sinanoglu, “Hide and Seek: Seeking the (Un)-Hidden Key in Provably-Secure Logic Locking Techniques,” in IEEE Transactions on Information Forensics and Security (TIFS), vol. 17, pp. 3290-3305, 2022, DOI: 10.1109/TIFS.2022.3207361

[2] M. Yasin, B. Mazumdar, J.V. Rajendran, and O. Sinanoglu, “SARLock: SAT attack resistant logic locking,” 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2016, pp. 236-241, DOI: 10.1109/HST.2016.7495588

[3] Y. Xie and A. Srivastava, “Anti-SAT: Mitigating SAT Attack on Logic Locking,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 2, pp. 199-207, Feb. 2019, DOI: 10.1109/TCAD.2018.2801220

[4] K. Shamsi, T. Meade, M. Li, D. Z. Pan, and Y. Jin, “On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes,” in IEEE Transactions on Information Forensics and Security (TIFS), vol. 14, no. 2, pp. 347-359, Feb. 2019, DOI: 10.1109/TIFS.2018.2850319

P7: “Timing-driven layer assignment in global routing”

[1]D. Liu, B. Yu, S. Chowdhury and D. Z. Pan, “Incremental layer assignment for critical path timing,” 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, pp. 1-6, doi: 10.1145/2897937.2898033.