SESSION: Keynote

Session details: Keynote

  • Bustany

Fusion: The Dawn of the Hyperconvergence Era in EDA

  • Krishnamoorthy

Hyperconvergence is a software-centric architecture which has disrupted the datacenter
industry in a dramatic way by bringing the disparate areas of compute, storage and
networking into a single system. A hyperconverged system allows the integrated …

SESSION: New Advances in Placement

Session details: New Advances in Placement

  • Yang

How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization

  • Netto

Machine learning has been used to improve the predictability of different physical
design problems, such as timing, clock tree synthesis and routing, but not for legalization.
Predicting the outcome of legalization can be helpful to guide incremental …

Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing

  • Chang

As the wide adoption of FinFET technology in mass production, dynamic power becomes
the bottleneck to achieving low power. Therefore, clock power reduction is crucial
in modern IC design. Register clustering can effectively save clock power because
of …

Device Layer-Aware Analytical Placement for Analog Circuits

  • Xu

The layouts of analog/mixed-signal (AMS) integrated circuits (ICs) are dramatically
different from their digital counterparts. AMS circuit layouts usually include a variety
of devices, including transistors, capacitors, resistors, and inductors. A …

Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement

  • Li

Modern circuit designs often contain standard cells of different row heights to meet
various design requirements. Due to the higher interference among heterogeneous cell
structures, the legalization problem for mixed-cell-height standard cells becomes

SESSION: FPGA Special Session: Advances in Adaptable Heterogeneous Computing and Acceleration
for Big Data

Session details: FPGA Special Session: Advances in Adaptable Heterogeneous Computing
and Acceleration for Big Data

  • Iyer

FPGA-based Computing in the Era of AI and Big Data

  • Nurvitadhi

The continued rapid growth of data, along with advances in Artificial Intelligence
(AI) to extract knowledge from such data, is reshaping the computing ecosystem landscape.
With AI becoming an essential part of almost every end-user application, our …

Advances in Adaptable Computing

  • Gupta

Recent technical challenges have forced the industry to explore options beyond the
conventional “one size fits all” CPU scalar processing solution. Very large vector
processing (DSP, GPU) solves some problems, but it runs into traditional scaling …

Improving Programmability and Efficiency of Large-Scale Graph Analytics for FPGA Platforms

  • Ozdal
    Muhammet Mustafa

Large-scale graph analytics has gained importance due to emergence of new applications
in different contexts such as web, social networks, and computational biology. It
is known that typical CPU/GPU implementations for sparse graph applications cannot

SESSION: Routing in All Forms

Session details: Routing in All Forms

  • Madden

Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under
Boolean Constraints

  • Ryzhenko

In this paper, we propose a routing flow for nets within a standard cell that generates
layout of standard cells without any design rule violations. Design rules, density
rules for metal fill, and pin-access requirements are modeled via Boolean formulas

PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed

  • Truppel

Optical Networks-on-Chip (ONoCs) are a promising solution for high-performance multi-core
integration with better latency and bandwidth than traditional Electrical NoCs. Wavelength-routed
ONoCs (WRONoCs) offer yet additional performance guarantees. …

Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the
3D Hanan Grid for Monolithic 3D IC Routing

  • Lin
    Sheng-En David

Monolithic three-dimensional~(3D) integration enables stacking multiple ultra-thin
silicon tiers in a single package, thereby providing smaller footprint area, shorter
wirelength, higher performance, and lower power consumption than conventional planar

ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques

  • Park

Routability diagnosis has increasingly become the bottleneck in detailed routing for
sub-10nm technology due to the limited tracks, high density, and complex design rules. The
conventional ways to examine the routability of detailed routing are ILP- and …

SESSION: Keynote

Session details: Keynote

  • Menezes

A Perspective on Security and Trust Requirements for the Future

  • Plaks

As integrated circuit manufacturing becomes increasingly global and the availability
of domestically produced advanced transistor nodes shrinks, security vulnerabilities
within the supply chain become a significant issue for IC defense applications. In

SESSION: Patterning and Machine Learning

Session details: Patterning and Machine Learning

  • Young

Declarative Language for Geometric Pattern Matching in VLSI Process Rule Modeling

  • Suto

This paper presents a formal (machine readable) declarative language developed for
the specific reason of modeling physical design process rules of any complexity. Case
studies are presented on synthetic as well as industry known design rules of simple

Electromigration-Aware Interconnect Design

  • Sapatnekar
    Sachin S.

Electromigration (EM) is seen as a growing problem in recent and upcoming technology
nodes, and affects a wider variety of wires (e.g., power grid, clock/signal nets),
circuits (e.g., digital, analog, mixed-signal), and systems (e.g., mobile, server,

Toward Intelligent Physical Design: Deep Learning and GPU Acceleration

  • Ren

Deep learning (DL) has achieved tremendous success in computer vision, natural language
processing and gaming. Would DL help push physical design toward a more intelligent
paradigm to meet the post-Moore era design automation challenges? We will discuss

Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon

  • Chang

Multiple patterning lithography (MPL) divides a layout into several masks and manufactures
them by a series of exposure and etching steps. As technology advances, MPL is still
indispensable because of its cost effectiveness and hybrid lithography …

SESSION: Cyber-Physical Systems

Session details: Cyber-Physical Systems

  • Groeneveld

From Electronic Design Automation to Automotive Design Automation

  • Lin

Advanced driver assistance systems (ADAS), autonomous functions, and connected applications
bring a revolution to automotive systems, but they also make automotive design, especially
software and electronics, more complex than ever. The complexity …

Enterprise-wide AI-enabled Digital Transformation

  • Maasoumy

Having solved the data integration problem, we discuss how convergence of 4 technology
vectors, namely Big Data, Artificial Intelligence, Cloud Computing, and Internet of
Things (IoT) has, for the first time, enabled us to solve a class of problems …

Secure and Trustworthy Cyber-Physical System Design: A Cross-Layer Perspective

  • Nuzzo

This talk discusses some of the design challenges posed by cyber-physical system security
at different abstraction layers, from algorithm design to the realization of trusted
hardware platforms. We introduce two design problems, namely, detecting sensor …

SESSION: Lifetime Achievement Award Tribute to Professor Alberto Sangiovanni-Vicentelli

Session details: Lifetime Achievement Award Tribute to Professor Alberto Sangiovanni-Vicentelli

  • Nuzzo

The Slow Start of Fast Spice: A Brief History of Timing

  • White
    Jacob K.

The list of Professor Alberto Sangiovanni-Vincentelli’s research contributions is
astounding in length and breadth, yet does not entirely capture what this author believes
is his true genius. In so many areas of computer-aided design, Sangiovanni-…

Basic and Advanced Researches in Logic Synthesis and their Industrial Contributions

  • Fujita

We first present historical view on the techniques for two-level and multi-level logic
optimizations, and discuss the practical issues with respect to them. Then the techniques
for sequential optimizations are briefly reviewed. Based on them, a new …

From Electronic Design Automation to Cyber-Physical System Design Automation: A Tale of Platforms and Contracts

  • Nuzzo

This paper reflects on the design challenges posed by cyber-physical systems, what
distinguishes cyber-physical system design from large-scale integrated circuit design,
and what could be the opportunities for the design automation community. The paper

My 50-Year Journey from Punched Cards to Swarm Systems

  • Sangiovanni Vincentelli

The article is a reflection onmy journey during the development of the EDA field,
from its early days to its explosive growth and present maturity. The two special
issues of the Solid State Circuit Society Magazine “Corsi e Ricorsi: Alberto Sangiovanni

SESSION: Lifetime Achievement Award Dinner Banquet Keynote

Freedom From Choice and the Power of Models: in Honor of Alberto Sangiovanni-Vincentelli

  • Lee
    Edward A.

Discovery, invention, and design are all about models. When we say “Joseph Priestly
discovered oxygen in 1774,” we do not mean that Priestly dug up a canister of oxygen,
recognized it as something new, and released it, for the first time, into the air.

SESSION: Physical Design – Where are we going?

Session details: Physical Design – Where are we going?

  • Cheng

Analog Layout Synthesis: Are We There Yet?

  • Mangalagiri

Over the past decade, spurred by advances in mobile computing, there has been a fundamental
shift in computing needs of consumer applications. There has been an industry-wide
transition from highly CPU-centric to a peripheral-centric, connectivity and …

Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling – A Fast and Effective

  • Sharma

Recent work has established Lagrangian relaxation (LR) based gate sizing as state-of-the-art
providing the best power reduction with low run time. Gate sizing has limited potential
to reduce the power when the timing constraints are tight. By adjusting …

Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM
Yield Analysis

  • Shi

Statistical circuit simulation is exhibiting increasing importance for memory circuits
under process variation. It is challenging to accurately estimate the extremely low
failure probability as it becomes a high-dimensional and multi-failure-region …

SESSION: Detailed Routing Contest Results

Session details: Detailed Routing Contest Results

  • Chinnery

ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules

  • Liu

Detailed routing becomes the most complicated and runtime consuming stage in the physical
design flow as technology nodes advance. Due to the inaccessibility of advanced routing
rules and industrial designs, it is hard to conduct detailed routing …