SESSION: Keynote 1

Session details: Keynote 1

  • Coskun

Why Is It So Hard to Make Secure Chips?

  • Witteman

Chip security has long been the domain of smart cards. These microcontrollers are
specifically designed to thwart many different attacks in order to deliver typical
security functions as payment cards, electronic passports, and access cards. With
the …

SESSION: Keynote 2

Session details: Keynote 2

  • Han

Design and Implementation of Real-Time Multi-sensor Vision Systems

  • Leblebici

Implementation of high performance multi-camera / multi-sensor imaging systems that
are required to produce real-time video output pose a large number of unique challenges
to conventional digital design based on general-purpose processors or GPUs. In …

SESSION: Keynote 3

Session details: Keynote 3

  • Margala

Medical Device Security: The First 165 Years

  • Fu

Today, it would be difficult to find medical device technology that does not critically
depend on computer software. Network connectivity and wireless communication has transformed
the delivery of patient care. The technology often enables patients to …

SESSION: Keynote 4

Session details: Keynote 4

  • Behjat

VLSI Design Methods for Low Power Embedded Encryption

  • Verbauwhede

Intelligent things, medical devices, vehicles and factories, all part of cyberphysical
systems, will only be secure if we can build devices that can perform the mathematically
demanding cryptographic operations in an efficient way. Unfortunately, many …

SESSION: Session 1: VLSI Circuits 1

Session details: Session 1: VLSI Circuits 1

  • Navabi

High-Speed Polynomial Multiplier Architecture for Ring-LWE Based Public Key Cryptosystems

  • Du

Many lattice-based cryptosystems are based on the security of the Ring learning with
errors (Ring-LWE) problem. The most critical and computationally intensive operation
of these Ring-LWE based cryptosystems is polynomial multiplication. In this paper,

Reduced Overhead Gate Level Logic Encryption

  • Juretus

Untrusted third-parties are found throughout the integrated circuit (IC) design flow
resulting in potential threats in IC reliability and security. Threats include IC
counterfeiting, intellectual property (IP) theft, IC overproduction, and the insertion

A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File

  • Junsangsri

This paper presents the design of a non-volatile register file using cells made of
a SRAM and a Programmable Metallization Cell (PMC). The proposed cell is a symmetric
8T2P (8-transistors, 2PMC) design; it utilizes three control lines to ensure the …

A Clockless Sequential PUF with Autonomous Majority Voting

  • Xu

Physical unclonable functions (PUFs) leverage minute silicon process variations to
produce device-tied secret keys. The energy and area costs of creating keys from PUFs
can far exceed the costs of the basic PUF circuits alone. Minimizing the end-to-end

SESSION: Session 2: VLSI and Test

Session details: Session 2: VLSI and Test

  • Qian

Area-Efficient Error-Resilient Discrete Fourier Transformation Design using Stochastic

  • Yuan

Discrete Fourier Transformation (DFT)/Fast Fourier Transformation (FFT) are the widely
used techniques in numerous modern signal processing applications. In general, because
of their inherent multiplication-intensive characteristics, the hardware …

Concurrent Error Detection for Reliable SHA-3 Design

  • Luo

Cryptographic systems are vulnerable to random errors and injected faults. Soft errors
can inadvertently happen in critical cryptographic modules and attackers can inject
faults into systems to retrieve the embedded secret. Different schemes have been …

Secure Model Checkers for Network-on-Chip (NoC) Architectures

  • Boraten

As chip multiprocessors (CMPs) are becoming more susceptible to process variation,
crosstalk, and hard and soft errors, emerging threats from rogue employees in a compromised
foundry are creating new vulnerabilities that could undermine the integrity of …

Parameter-importance based Monte-Carlo Technique for Variation-aware Analog Yield

  • kondamadugula

The Monte-Carlo method is the method of choice for accurate yield estimation. Standard
Monte-Carlo methods suffer from a huge computational burden even though they are very
accurate. Recently a Monte-Carlo method was proposed for the parametric yield …

SESSION: Session 3: VLSI Design 1

Session details: Session 3: VLSI Design 1

  • Thapliyal

Low Energy Sketching Engines on Many-Core Platform for Big Data Acceleration

  • Kulkarni

Almost 90% of the data available today was created within the last couple of years,
thus Big Data set processing is of utmost importance. Many solutions have been investigated
to increase processing speed and memory capacity, however I/O bottleneck is …

Low-Power Manycore Accelerator for Personalized Biomedical Applications

  • Page

Wearable personal health monitoring systems can offer a cost effective solution for
human healthcare. These systems must provide both highly accurate, secured and quick
processing and delivery of vast amount of data. In addition, wearable biomedical …

Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs

  • Dofe

New hardware security threats are identified in emerging three-dimensional (3D) integrated
circuits (ICs) and potential countermeasures are introduced. Trigger and payload mechanisms
for future 3D hardware Trojans are predicted. Furthermore, a novel, …

Real-Time Analysis for Wormhole NoC: Revisited and Revised

  • Xiong

The network delay upper-bound analysis problem is of fundamental importance to real-time
applications in Network-on-Chip (NoC). In the paper, we revisit a state-of-the-art
analysis model for real-time communication in wormhole NoC with priority-based …

SESSION: Session 4: CAD 1

Session details: Session 4: CAD 1

  • Adegbija

A New Methodology for Noise Sensor Placement Based on Association Rule Mining

  • Hung

Due to near-threshold computing nowadays, voltage emergency is threatening our design
margins very seriously. Noise sensors are inserted in order to prevent various integrity
issues from happening during runtime. In this work, we use a new technique …

MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router

  • Jia

In modern VLSI design, manufacturing yield and chip performance are seriously affected
by via failure. Redundant via insertion is an effective technique recommended by foundries
to deal with the via failure. However, due to the extreme scaling of …

Modular Placement for Interposer based Multi-FPGA Systems

  • Mao

Novel device with multiple FPGAs on-chip based on interposer interconnection has emerged
to resolve the IOs limit and improve the inter-FPGA communication delay. However,
new challenges arise for the placement on such architecture. Firstly, existing …

A Parallel Random Walk Solver for the Capacitance Calculation Problem in Touchscreen

  • Xu

In this paper, a random walk based solver is presented which calculates the capacitances
for verifying the touchscreen design. To suit the complicated conductor geometries
in touchscreen structures, we extend the floating random walk (FRW) method for …

POSTER SESSION: Poster Session 1

Session details: Poster Session 1

  • Moreshet

Real-Time Hardware Stereo Matching Using Guided Image Filter

  • Yang

Stereo matching is a key step in stereo vision systems that require high accurate
depth information and real-time processing of high definition image streams. This
work presents a high-accuracy hardware implementation for the stereo matching based
on …

Computing Complex Functions using Factorization in Unipolar Stochastic Logic

  • Liu

This paper addresses computing complex functions using unipolar stochastic logic.
Stochastic computing requires simple logic gates and is inherently fault-tolerant.
Thus, these structures are well suited for nanoscale CMOS technologies. Implementations

DCC: Double Capacity Cache Architecture for Narrow-Width Values

  • Imani

Modern caches are designed to hold 64-bits wide data, however a proportion of data
in the caches continues to be narrow width. In this paper, we propose a new cache
architecture which increases the effective cache capacity up to 2X for the systems
with …

Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating
Voltage Improvement using Recovery Techniques

  • Batra

In advanced technology nodes, the process variations deteriorate SRAM performance
and greatly affect yield. It is necessary to formulate yield estimation models to
optimize SRAMs and effectively trade-off area, performance and robustness. We propose

Asynchronous High Speed Serial Links Analysis using Integrated Charge for Event Detection

  • Dalakoti

We present a metric for event detection, targeted for the analysis of CMOS asynchronous
serial data links. Our metric is used to analyze signaling strategies that allow for
coincident or nearly coincident detection of both data and event timing. The …

Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level

  • Wei

A hybrid memory cell usually consists of a Static Random Access Memory (SRAM) and
an embedded Dynamic Random Access Memory (eDRAM) cell; hybrid cells are particularly
suitable for cache design. A novel hybrid cache memory scheme (that has also non-…

A Sampling Clock Skew Correction Technique for Time-Interleaved SAR ADCs

  • Prashanth

A technique for sampling clock skew correction by adjusting the delay in the input
signal to each channel in a time-interleaved (TI) ADC is proposed. A proof-of-concept
TI ADC employing this technique was implemented in a 65 nm CMOS process. The four-…

Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers

  • Wang

Circuit obfuscation techniques have been proposed to conceal circuit’s functionality
in order to thwart reverse engineering (RE) attacks to integrated circuits (IC). We
believe that a good obfuscation method should have low design complexity and low …

Task-Resource Co-Allocation for Hotspot Minimization in Heterogeneous Many-Core NoCs

  • Reza
    Md Farhadur

To fully exploit the massive parallelism of many cores, this work tackles the problem
of mapping large-scale applications onto heterogeneous on-chip networks (NoCs) to
minimize the peak workload for energy hotspot avoidance. A task-resource co-…

Guiding Power/Quality Exploration for Communication-Intense Stream Processing

  • Tabkhi

In this paper, we explore the power/quality trade-off for streaming applications with
a shift from the computation to the communication aspects of the design. The paper
proposes a systematic exploration methodology to formulate and traverse power/…

SESSION: Session 5: Low Power 1

Session details: Session 5: Low Power 1

  • Savidis

Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture

  • Tenace

The key characteristics of the next generation of ICs for wearable applications include
high integration density, small area, low power consumption, high energy-efficiency,
reliability and enhanced mechanical properties like stretchability and …

A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance

  • Sannena

In this paper, two timing error masking flip-flops have been proposed, which are immune
to metastability. The proposed flip-flops exploit the concept of either delayed data
or pulse based approach to detect timing errors. The timing violations are …

Exploring Configurable Non-Volatile Memory-based Caches for Energy-Efficient Embedded

  • Adegbija

Non-volatile memory (NVM) technologies have recently emerged as alternatives to traditional
SRAM-based cache memories, since NVMs offer advantages such as non-volatility, low
leakage power, fast read speed, and high density. However, NVMs also have …

Multiple Attempt Write Strategy for Low Energy STT-RAM

  • Park

In this paper, we demonstrate an energy-reduction strategy that exploits the stochastic
switching characteristics of STT-RAM write operation and propose a multiple-attempt
write technique needed for it. In contrast to the traditional approach which uses

SESSION: Special Session 1: IoT Security: Issues, Innovations and Interplays

Session details: Special Session 1: IoT Security: Issues, Innovations and Interplays

  • Bhunia

Secret Sharing and Multi-user Authentication: From Visual Cryptography to RRAM Circuits

  • Arafin
    Md Tanvir

In this era of Internet of Things (IoT), connectivity exists everywhere, among everything
(including people) at all times. Therefore, security, trust, and privacy become crucial
to the design and implementation of IoT devices [12]. However, it is …

Defense Systems and IoT: Security Issues in an Era of Distributed Command and Control

  • Palmer

Security Meets Nanoelectronics for Internet of Things Applications

  • Rose
    Garrett S.

The internet of things (IoT) is quickly emerging as the next major domain for embedded
computer systems. Although the term IoT could be defined in a variety of different
ways, IoT always encompasses typically ordinary devices (e.g., thermostats and …

Tracking Data Flow at Gate-Level through Structural Checking

  • Le

The rapid growth of Internet-of-things and other electronic devices make a huge impact
on how and where data travel. The confidential data (e.g., personal data, financial
information) that travel through unreliable channels can be exposed to attackers.

SESSION: Session 6: Test 2

Session details: Session 6: Test 2

  • Yu

Design of Error-Resilient Logic Gates with Reinforcement Using Implications

  • Han

Operating circuits in the sub-threshold region can save power, but at the cost of
higher susceptibility to noise. This paper analyzes various gate-level error-mitigation
designs appropriate for sub-threshold circuits. Previous works have proposed a …

Reducing Soft-error Vulnerability of Caches using Data Compression

  • Mittal

With ongoing chip miniaturization and voltage scaling, particle strike-induced soft
errors present increasingly severe threat to the reliability of on-chip caches. In
this paper, we present a technique to reduce the vulnerability of caches to soft-…

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation

  • Bian

As technology further scales semiconductor devices, aging-induced device degradation
has become one of the major threats to device reliability. In addition, aging mechanisms
like the negative bias temperature instability (NBTI) is known to be sensitive …

Enhancing Fault Emulation of Transient Faults by Separating Combinational and Sequential
Fault Propagation

  • Nyberg

We present a fault emulation environment capable of injecting single and multiple
transient faults in sequential as well as combinational logic. It is used to perform
fault injection campaigns during design verification of security circuits such as

SESSION: Session 7: VLSI Circuits 2

Session details: Session 7: VLSI Circuits 2

  • Li

A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and

  • Choi

In this paper, a novel on-chip impedance calibration methodology for a LPDDR4 (low
power double data rate) application is proposed. The background calibration operates
to compensate mismatches and variations of the output NMOS drivers from process and

A General Sign Bit Error Correction Scheme for Approximate Adders

  • Zhou

Approximate computing is an emerging design technique for error-tolerant applications.
As adders are the key building blocks in many applications, approximate adders have
been widely studied recently. However, existing approximate adders may introduce …

RRAM Refresh Circuit: A Proposed Solution To Resolve The Soft-Error Failures For HfO2/Hf 1T1R RRAM Memory

  • Tosson
    Amr M.S.

RRAM-based memory is a promising emerging technology for both on-chip and stand-alone
non-volatile data storage in advanced technologies. In addition to its small dimensions,
the RRAM device has many technological advantages including its low-…

Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs

  • Patel

The physical dimensions of standard cells constrain the dimensions of power networks,
affecting the on-chip power noise. An exploratory modeling methodology is presented
for estimating power noise in advanced technology nodes. The models are evaluated

8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design

  • Abdelwahed
    Amr M.S. Tosson

With continuous and aggressive technology scaling, suppressing the stand-by power
is among the top priorities for SRAM design. Switching off the less-frequently accessed
blocks is an efficient way to reduce the stand-by power, provided that the …

SESSION: Session 8: Emerging 1

Session details: Session 8: Emerging 1

  • Yuan

Polynomial Arithmetic Using Sequential Stochastic Logic

  • Saraf

We present the design of stochastic computing systems based on sequential logic to
implement arbitrary polynomial functions. Stochastic computing is an emerging alternative
computing paradigm that performs arithmetic operations on real-valued data …

Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall Devices

  • Bai

Despite many attractive advantages, Null Convention Logic (NCL) remains to be a niche
largely due to its high imple- mentation costs. Using emerging spintronic devices,
this paper proposes a Domain-Wall-Motion-based NCL circuit design methodology that

Inter-Tier Crosstalk Noise On Power Delivery Networks For 3-D ICs With Inductively-Coupled

  • Papistas
    Ioannis A.

Inductive links have been proposed as an inter-tier interconnect solution for three-dimensional
(3-D) integrated systems. Combined with signal multiplexing, inductive links achieve
high communication bandwidth comparable to that of through silicon vias. …

Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees

  • Das

With extreme miniaturization of traditional CMOS devices in deep sub-micron design
levels, the delay of a circuit, as well as power dissipation and area are dominated
by interconnections between logic blocks. In an attempt to search for alternative

SESSION: Session 9: CAD 2

Session details: Session 9: CAD 2

  • Velev

VarDroid: Online Variability Emulation in Android/Linux Platforms

  • Mercati

Variability is the real big challenge for integrated circuits. Today, simulators help
to estimate the effect of variability, but fail to capture real workload dynamics
and user interactions, which are fundamental to mobile devices. This paper presents

Neural Network-based Prediction Algorithms for In-Door Multi-Source Energy Harvesting
System for Non-Volatile Processors

  • Liu

Due to size, longevity, safety, and recharging concerns, energy harvesting is becoming
a better choice for many wearable embedded systems than batteries. However, harvested
energy is intrinsically unstable. In order to overcome this drawback, non-…

A Unified Model of Power Sources for the Simulation of Electrical Energy Systems

  • Vinco

Models of power sources are essential elements in the simulation of systems that generate,
store and manage energy. In spite of the huge difference in power scale, they perform
a common function: converting a primary environmental quantity into power. …

Hardware-Accelerated Software Library Drivers Generation for IP-Centric SoC Designs

  • Jassi

In recent years, the semiconductor industry has been witnessing an increasing reuse
of hardware IPs for System-on-Chip (SoC) designs and embedded computing systems on
FPGA platforms with hard-core processors. The IP-reuse comes with an increasing …

Extracting Designs of Secure IPs Using FPGA CAD Tools

  • Mirian

In today’s competitive market, a company’s success is strongly dependent on delivering
sophisticated and state-of-the-art IPs prior to their competitors. To take a short
cut, a company may resort to reverse engineering or pirating their competitor’s IP.

SESSION: Special Session 3: Emerging Technology Devices and Security

Session details: Special Session 3: Emerging Technology Devices and Security

  • Rajendran

Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM

  • Karam

Inherent stochastic physical mechanisms in emerging nonvolatile memories (NVMs), such
as resistive random-access-memory (RRAM), have recently been explored for hardware
security applications. Unlike the conventional silicon Physical Unclonable Functions

Enhancing Hardware Security with Emerging Transistor Technologies

  • Bi

We consider how the I-V characteristics of emerging transistors (particularly those
sponsored by STARnet) might be employed to enhance hardware security. An emphasis
of this work is to move beyond hardware implementations of physically unclonable …

The Applications of NVM Technology in Hardware Security

  • Yang

The emerging nonvolatile memory (NVM) technologies have demonstrated great potentials
in revolutionizing modern memory hierarchy because of their many promising properties:
nanosecond read/write time, small cell area, non-volatility, and easy CMOS …

Survey of Emerging Technology Based Physical Unclonable Funtions

  • Bautista Adames
    Ilia A.

Authentication of electronic devices has become critical. Hardware authentication
is one way to enhance security of a chip. Along with software, it makes it harder
for an intruder to access any computer, smart-phone, or other devices without …

SESSION: Session 10: VLSI Design 2

Session details: Session 10: VLSI Design 2

  • Meyer

Trellis-search based Dynamic Multi-Path Connection Allocation for TDM-NoCs

  • Chen

This paper proposes a centralized approach for connection allocation for TDM-based
NoCs by making use of dedicated hardware unit called NoCManager that employs trellis-based
search algorithm enabling dynamic parallel multi-path, multi-slot allocation. …

Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping

  • Soltani

Recently, work has been done on using nonvolatile cells, such as Spin Transfer Torque
RAM (STT-RAM) or Magnetic RAM (M-RAM), to construct last level caches (LLC). These
structures mitigate the leakage power and density problem found in traditional SRAM

A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors

  • Psarras

Technology scaling of tiled-based CMPs reduces the physical size of each tile and
increases the number of tiles per die. This trend directly impacts the on-chip interconnect;
even though the tile population increases, the inter-tile link distances scale …

Dynamic Real-Time Scheduler for Large-Scale MPSoCs

  • Ruaro

Large-scale MPSoCs requires a scalable and dynamic real-time (RT) task scheduler,
able to handle non-deterministic computational behaviors. Current proposals for MPSoCs
have limitations, as lack of scalability, complex static steps, validation with …

SESSION: Special Session 4: Emerging Frontiers in Hardware Security

Session details: Special Session 4: Emerging Frontiers in Hardware Security

  • Joshi

Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges

  • Gu

3D die stacking and 2.5D interposer design are promising technologies to improve integration
density, performance and cost. Current approaches face serious issues in dealing with
emerging security challenges such as side channel attacks, hardware …

POSTER SESSION: Poster Session 2

Session details: Poster Session 2

  • Tabkhi

FCM: Towards Fine-Grained GPU Power Management for Closed Source Mobile Games

  • Song

Contemporary mobile platforms employ embedded graphic processing units (GPUs) for
graphics-intensive games, and dynamic voltage and frequency scaling (DVFS) policies
are used to save energy without sacrificing quality. However, current GPU DVFS policies

Quality of Service-Aware, Scalable Cache Tuning Algorithm in Consumer-based Embedded

  • Alsafrjalani
    Mohamad Hammam

To meet energy and quality of service (QoS) constraints in consumer-based embedded
devices (CEDs), configurable caches can be tuned to a best configuration that consumes
the least amount of energy while adhering to QoS expectations. However, due to …

Temperature-aware Dynamic Voltage Scaling for Near-Threshold Computing

  • Kiamehr

Power/energy reduction is of uttermost importance for applications with stringent
power/energy budget such as ultra-low power and energy-harvested systems. Aggressive
voltage scaling and in particular Near-Threshold Computing (NTC) is a promising …

Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks
of Dependent Paths

  • Chakraborty
    Tuhin Subhra

Leakage power minimization is one of the key aspects of modern multi-million low power
system-on-chip (SoC) design. In post timing-closure phase, leakage-in-place-optimization
(LIPO) is generally adopted to reduce leakage power by swapping high-leaky …

An Enhanced Analytical Electrical Masking Model for Multiple Event Transients

  • Watkins

Due to the reducing transistor feature size, the susceptibility of modern circuits
to radiation induced errors has increased. This, as a result, has increased the likelihood
of multiple transients affecting a circuit. An important aspect when modeling …

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components

  • Stamoulis

Atomistic-based approaches accurately model Bias Temperature Instability phenomena,
but they suffer from prolonged execution times, preventing their seamless integration
in system-level analysis flows. In this paper we present a comprehensive flow that

Performance Constraint-Aware Task Mapping to Optimize Lifetime Reliability of Manycore

  • Rathore

Negative bias temperature instability (NBTI) has emerged as a critical challenge to
lifetime reliability of computing systems. Traditionally, temperature-aware methodologies
are used to mitigate the impact of NBTI on aging and degradation of computing …

ASIC Implementation of An All-digital Self-adaptive PVTA Variation-aware Clock Generation

  • Pérez-Puigdemont

An all-digital self-adaptive clock generation system capable of autonomously adapt
the clock frequency to compensate the effects of static spatially heterogeneous (SSHet)
PVTA variations is presented. The design uses time-to-digital converters (TDCs) as

Ultra-Low Energy Reconfigurable Spintronic Threshold Logic Gate

  • Fan

This paper introduces a novel design of reconfigurable Spintronic Threshold Logic
Gate (STLG), which employs spintronic weight devices to perform current mode weighted
summation of binary inputs, whereas, the low voltage spintronic threshold device …

Red-Shield: Shielding Read Disturbance for STT-RAM Based Register Files on GPUs

  • Zhang

To address the high energy consumption issue of SRAM on GPUs, emerging Spin-Transfer
Torque (STT-RAM) memory technology has been intensively studied to build GPU register
files for better energy-efficiency, thanks to its benefits of low leakage power, …

Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits

  • Marthi

In this paper, study of different digital logic circuits developed using two-BDT ballistic
nanostructure is presented. New D flip-flop (DFF) based on the same nanostructure
is also proposed. The logic structure comprises two ballistic deflection …

SESSION: Session 11: Emerging 2

Session details: Session 11: Emerging 2

  • Dai

Exploring Main Memory Design Based on Racetrack Memory Technology

  • Hu

Emerging non-volatile memories (NVMs), which include PC-RAM and STT-RAM, have been
proposed to replace DRAM, mainly because they have better scalability and lower standby
power. However, previous research has demonstrated that these NVMs cannot …

An Offline Frequent Value Encoding for Energy-Efficient MLC/TLC Non-volatile Memories

  • Alsuwaiyan

This paper describes a low overhead, offline frequent value encoding (FVE) solution
to reduce the write energy in multi-level/triple-level cell (MLC/TLC) non-volatile
memories (NVMs). The proposed solution, which does not require any runtime software

Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices

  • Bishnoi

Multi-port memories are widely used as shared memory, such as register files, in a
microprocessor system, and its number of ports and capacities are significantly increasing
with every product generation. However, with technology advancements, multi-…

Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write
Assist Circuitry

  • Afzali-Kusha

This paper deals with obtaining the minimum operating voltage of memory arrays based
on TFET SRAM cells. First, we compare the I-V characteristics of two TFETs and one
FDSOI using SPICE simulations based on 20nm technology models. The results reveal

SESSION: Session 12: Low Power 2

Session details: Session 12: Low Power 2

  • Kim
    Kyung Ki

Approximate Differential Encoding for Energy-Efficient Serial Communication

  • Jahier Pagliari

Embedded computing systems include several off-chip serial links, that are typically
used to interface processing elements with peripherals, such as sensors, actuators
and I/O controllers. Because of the long physical lines of these connections, they

Fast Thermal Simulation using SystemC-AMS

  • Chen

Out of the many options available for thermal simulation of digital electronic systems,
those based on solving an RC equivalent circuit of the thermal network are the most
popular choice in the EDA community, as they provide a reasonable tradeoff …

Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal

  • Aprile

Wireless implantable devices capable of monitoring the electrical activity of the
brain are becoming an important tool for understanding and potentially treating mental
diseases such as epilepsy and depression. While such devices exist, it is still …

Load Balanced On-Chip Power Delivery for Average Current Demand

  • Pathak

A dynamic power management system for homogeneous chip multi-processors (CMP) is proposed.
Each core of the CMP includes on chip DC-DC switching buck converters that are interconnected
through a switch network. The peak current rating of the buck …