CADathlon 2022 Problem References

P1: “Memory controller enhancement via exploiting locality,” 

[1] S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, J. D. Owens, “Memory Access Scheduling”, ISCA ’00: pp 128-138.


P2: “Triple Patterning Aware Detailed Placement”

[1] Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles Alpert and David Z. Pan, “Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.34, no.5, pp.726-739, 2015.

P3: “Modularity optimization for synchronous block diagram”

[1] Peng Deng, Qi Zhu, Marco Di Natale, and Haibo Zeng, “Task Synthesis for Latency-sensitive Synchronous Block Diagram,” SIES 2014.

P4: ” Reliability-Driven Mixed-Precision Navigation”

[1] A. Mahmoud, T. Tambe, T. Aloui, D. Brooks and G. -Y. Wei, “GoldenEye: A Platform for Evaluating Emerging Numerical Data Formats in DNN Accelerators,” 2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2022, pp. 206-214, doi: 10.1109/DSN53405.2022.00031.

P5: “

Verifiable Execution of Deep Neural Networks”

[1] Zahra Ghodsi, Tianyu Gu, Siddharth Garg, “SafetyNets: Verifiable Execution of Deep Neural Networks on an Untrusted Cloud”, In Advances in Neural Information Processing Systems, 2017. 

P6: “Deciphering Secret Key for Provably-Secure Logic Locking Techniques” 

[1] S. Patnaik, N. Limaye and O. Sinanoglu, “Hide and Seek: Seeking the (Un)-Hidden Key in Provably-Secure Logic Locking Techniques,” in IEEE Transactions on Information Forensics and Security (TIFS), vol. 17, pp. 3290-3305, 2022, DOI: 10.1109/TIFS.2022.3207361

[2] M. Yasin, B. Mazumdar, J.V. Rajendran, and O. Sinanoglu, “SARLock: SAT attack resistant logic locking,” 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2016, pp. 236-241, DOI: 10.1109/HST.2016.7495588

[3] Y. Xie and A. Srivastava, “Anti-SAT: Mitigating SAT Attack on Logic Locking,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 2, pp. 199-207, Feb. 2019, DOI: 10.1109/TCAD.2018.2801220

[4] K. Shamsi, T. Meade, M. Li, D. Z. Pan, and Y. Jin, “On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes,” in IEEE Transactions on Information Forensics and Security (TIFS), vol. 14, no. 2, pp. 347-359, Feb. 2019, DOI: 10.1109/TIFS.2018.2850319

P7: “Timing-driven layer assignment in global routing”

[1]D. Liu, B. Yu, S. Chowdhury and D. Z. Pan, “Incremental layer assignment for critical path timing,” 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, pp. 1-6, doi: 10.1145/2897937.2898033.

CADathlon 2019 Problem References

Problem 1: Circuit Design and Analysis
Contributed by Jianlei Yang, Beihang University
Overview: Solve Landau-Lifshitz-Gilbert (LLG) equation (in C++)
Reference: Iwasaki, Junichi, Masahito Mochizuki, and Naoto Nagaosa. “Current-induced skyrmion dynamics in constricted geometries,” Nature nanotechnology 8.10 (2013): 742.

Problem 2: Physical Design & Design for Manufacturability
Contributed by William Chow, Cadence
Overview: Tap assignment for gated clock network (in C++)
Reference: W-H Chen, C-K Wang, H-M Chen, Y-C Chou, and C-H Tsai, “A Comparative Study on Multisource Clock Network Synthesis,” The 22nd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 2016

Problem 3: Logic & High-Level Synthesis
Overview: Boolean Function Manipulation by Quantification (in C++)
Reference: No specific reference is provided.

Problem 4: System Design & Analysis
Contributed by Andy Yu-Guang Chen, National Central University
Overview: On-line Wake-up Scheduling for Multi-module design (in C++)
Reference 1: D. Brelaz, “New Methods to Color the Vertices of a Graph,” Communications of the ACM, Vol.22, Issue 4, Apr. 1979.
Reference 2: M.C. Lee, Y. Shi, Y.G. Chen, D. Marculescu, S.C. Chang, “Efficient On-Line Module-Level Wake-Up Scheduling for High Performance Multi-Module Designs,” Proc. on the International Symposium on Physical Design (ISPD), 2012, Page(s): 97-104.

Problem 5: Functional Verification & Testing
Contributed by Hao Zheng, University of South Florida
Overview: Cycle-based logic simulation (in C++)
Reference 1: S. Palnitkar and D. Parham, “Cycle Simulation Techniques,” IEEE International Verilog HDL Conference, 1995, Page(s) 2-8.
Reference 2: A. Biere, “The AIGER And-Inverter Graph (AIG) Format, Version 20070427,” Johannes Kepler University, 2006-2007

Problem 6: Future technologies (Bio-EDA, Security, AI, etc.)
Contributed by Mimi Xie, The University of Texas at San Antonio and Caiwen Ding, University of Connecticut
Overview: Efficient Pruning for Neural Networks (in Python)
Reference: Han, Song, Jeff Pool, John Tran, and William Dally. “Learning both weights and connections for efficient neural network,” In Advances in neural information processing systems, pp. 1135-1143. 2015.


Sunday, Oct. 30, 2022  08:00 AM – 05:00 PM, Hybrid

Sorrento Ballroom, San Diego Mission Bay Resort, CA

The Winner of this CADathlon 2022:

First place award:

Yen-Ju Lee and Tzu-Yu Tung, National Taiwan University

Enzo Yoshio Niho and Eduardo Quirino de Oliveira, Universidade de Brasília

Welcome to CADathlon@ICCAD

CADathlon 2022 will be held hybridly, you will be competing against the bests around the world.

The CADathlon is a challenging, all-day, programming competition focusing on practical problems at the forefront of Computer-Aided Design, and Electronic Design Automation in particular. The contest emphasizes the knowledge of algorithmic techniques for CADapplications, problem-solving and programming skills, as well as teamwork.

As the “Olympic games of EDA,” the contest brings together the best and the brightest of the next generation of CAD professionals. It gives academia and the industry a unique perspective on challenging problems and rising stars, and it also helps attract top graduate students to the EDA field.

The contest is open to two-person teams of undergraduate/graduate students specializing in CAD and currently full-time enrolled in a Ph.D. granting institution in any country. Students are selected based on their academic backgrounds and their relevant EDA programming experiences. Partial or full travel grants are provided to qualifying students. CADathlon competition consists of six problems in the following areas:

  • Circuit Design & Analysis
  • Physical Design & Design for Manufacturability
  • Logic & High-Level Synthesis
  • System Design & Analysis
  • Functional Verification & Testing
  • Future technologies (Bio-EDA, Security, AI, etc.)

More specific information about the problems and relevant research papers will be released on the Internet one week prior to the competition. The writers and judges that construct and review the problems are experts in EDA from both academia and industry. At the contest, students will be given the problem statements and example test data, but they will not have the judges’ test data. Solutions will be judged on correctness and efficiency. Where appropriate, partial credit might be given.

The team that earns the highest score is declared the winner. In addition to handsome trophies, the first place and the second place teams receive cash award, and the contest winners will be announced at the ICCAD conference.

  • Cash Prize
    • First place award: 1500 per person
    • Second place award: 750 per person
  • Participation Request (please submit via Google Form)
  • Important dates
    • October 15: Participation request form due
    • October 21: Confirmation of attendance due
    • October 23: Release of topic/hardware details
    • October 30: Contest date

Global Education Partner: