Who’s Ahmedullah Aziz

June 1st, 2022

Headshot of Ahmedullah Aziz in the Student Union on August 05, 2019. Photo by Steven Bridges/University of Tennessee

Ahmedullah Aziz

Assistant Professor

University of Tennessee Knoxville

Email:

aziz@utk.edu

Personal webpage

https://nordic.eecs.utk.edu/

Research interests

Cryogenic Electronics, Beyond-CMOS Technologies, Neuromorphic Hardware, Superconducting Devices/Circuits, VLSI

Short bio

Dr. Ahmedullah Aziz is an Assistant Professor of Electrical Engineering & Computer Science at the University of Tennessee, Knoxville, USA. He earned his Ph.D. in Electrical & Computer Engineering from Purdue University in 2019, an MS degree in Electrical Engineering from the Pennsylvania State University (University Park) in 2016, and a BS degree in Electrical & Electronic Engineering from Bangladesh University of Engineering & Technology (BUET) in 2013. Before beginning his graduate studies, Dr. Aziz worked in the ‘Tizen Lab’ of the Samsung R&D Institute in Bangladesh as a full-time Engineer. During graduate education, he worked as a Co-Op Engineer (Intern) in the Technology Research division of Global Foundries (Fab 8, NY, USA). He received several awards and accolades for his research, including the ‘ACM SIGDA Outstanding Ph.D. Dissertation Award (2021)’ from the Association of Computing Machinery, ‘EDAA Outstanding Ph.D. Dissertation Award (2020)’ from the European Design and Automation Association, ‘Outstanding Graduate Student Research Award (2019)’ from the College of Engineering, Purdue University, and ‘Icon’ award from Samsung (2013). He was a co-recipient of two best publication awards (2015, 2016) from the SRC-DARPA STARnet Center and the best project award (2013) from CNSER. In addition, he received several scholarships and recognition for academic excellence, including – Dean’s Award, JB Gold Medal, and Chairman’s Award. He is a technical program committee (TPC) member for multiple flagship conferences (including DAC, ISCAS, GLSVLSI, Nano) and a reviewer for several journals from reputed publishers (IEEE, AIP, Elsevier, Frontiers, IOP Science, Springer Nature). He served as a review panelist for the US Department of Energy (DOE) and a guest editor for – ‘Frontiers in Nanotechnology’, ‘Photonics’, and ‘Micromachines’.

Reasearch highlights

Dr. Aziz is an expert in device-circuit co-design and electronic design automation (EDA). His research laid the foundation for physics-based and semi-physical compact modeling of multiple emerging device technologies, including – Mott switches, oxide memristors, ferroelectric transistors, Josephson Junctions, cryotrons, topological memory/switches, and so on. His exemplary contributions to the field of low-power electronics have been internationally recognized through two prestigious distinguished dissertation awards by (i) the Association for Computing Machinery (ACM) – 2021 and (ii) European Design and Automation Association (EDAA) – 2020. His research portfolio comprises multiple avenues of exploratory nanoelectronics, spanning from device modeling to circuit/array design. In addition, Dr. Aziz has been a trailblazer in cryogenic memory technologies, facilitating critical advancements in quantum computing systems and space electronics. His works on memristive (room-temperature) and superconducting (cryogenic) neuromorphic systems have paved the way for dense, reconfigurable, and bio-plausible computing hardware.

Who’s Li Jiang

July 1st, 2022

Li Jiang

Assistant Professor

Shanghai Jiao Tong University

Email:

ljiang_cs@sjtu.edu.cn

Personal webpage

https://www.cs.sjtu.edu.cn/~jiangli/

Research interests

Compute-in-memory, Neuromorphic Computing, Domain Specific Architecture for AI, Database, networking etc.

Short bio

Li Jiang received the B.S. degree from the Dept. of CS&E, Shanghai Jiao Tong University in 2007, the MPhil, and the Ph.D. degree from the Dept. of CS&E, the Chinese University of Hong Kong in 2010 and 2013, respectively. He has published more than 80 peer-review papers in top-tier computer architecture, EDA and AI/Database conferences and journals, including ISCA, MICRO, DAC, ICCAD, AAAI, ICCV, SigIR, TC, TCAD, TPDS and etc. He received the Best Paper Award in DATE’22, Best Paper Nomination in ICCAD10, and DATE21. According to the IEEE Digital Library, five articles ranked in the top 5 of citations of all papers collected at its conferences. Some of the achievements have been introduced into the IEEE P1838 standard, and several technologies have been in commercial use in cooperation with TSMC, Huawei, and Alibaba.

He got the best Ph.D. Dissertation award in ATS 2014, and he was in the final list of TTTC’s E. J. McCluskey Doctoral Thesis Award. He received ACM Shanghai Rising Star award and CCF VLSI early career award in 2019. He received the 2nd class prize of Wu Wenjun Award for Artificial Intellegence. He serves as co-chair and TPC member in several international and national conferences, such as MICRO, DATE, ASP-DAC, ITC-Asia, ATS, CFTC, CTC, etc. He is an Associate Editor of IET Computers Digital Techniques, VLSI, the Integration Journal. He is the co-founder of ChinaDA and ACM/SigDA East China Branch.

Reasearch highlights

Prof. Li Jiang has been working on the test and repair architecture of 3D ICs that can dramatically reduce costs, advocating and emphasizing the precious resources sharing mechanism. They optimize the 3D SoC test architecture under test-pin count and thermal dissipation constraints by sharing the test-access-mechanism (TAM) and test wire of pre-bond wafer-level and post-bond package-level tests. They further propose the inter-die spare-sharing technique and the die-matching algorithms to improve the stack yield of 3D stacked memory. This work is nominated as the best paper in ICCAD 2010. Based on this method, they work with TSMC to propose a novel BISR architecture that can cluster and map faulty rows/columns across die to the same spare row/column to enhance the reparability. This series of works have been widely accepted by the mainstream and introduced into the IEEE P1838 standard.

To improve the assembly yield in the TSV fabrication process, they develop a fault model considering TSV coupling effect that has not been carefully investigated before. It leads their attention to a unique phenomenon, i.e., the faulty TSVs can be clustered. Thus, they propose a novel spare-TSV sharing architecture composed of a lightweight switch design, two effective and efficient repair algorithms, and a TSV-grid mapping mechanism that can avoid catastrophic TSV clustering defects.

ReRAM cell needs multiple programming pulses to avoid device programming variation and resistance drifting. To overcome the resulting programming latency and energy, they propose a Self-Terminating Write (STW) circuit that heavily reuses the inherent PIM peripherals (e.g., ADC and Trans-Impedance Amplifier) to obtain 2-bit precision via a single program pulse. This work is the best paper award of DATE 2022.

Who’s Fan Chen

July 1st, 2022

Fan Chen

Assistant Professor

Indiana University Bloomington

Email:

fc7@iu.edu

Personal webpage

https://homes.luddy.indiana.edu/fc7/

Research interests

Beyond-CMOS Computing, Quantum Machine Learning, Accelerator Architecture for Emerging Applications, Emerging Nonvolatile Memory

Short bio

Fan Chen is an assistant professor in the Department of Intelligent Systems Engineering at the Indiana University Bloomington. Dr. Chen received her Ph.D. from the department of Electrical and Computer Engineering at Duke University. Dr. Chen is a recipient of the 2022 NSF Faculty Early Career Development Program (CAREER) Award, the 2021 Service Recognition Award of Great Lakes Symposium on VLSI (GLSVLSI), the 2019 Cadence Women in Technology Scholarship, the Best Paper Award and the Ph.D. forum Best Poster Award at 2018 Asia and South Pacific Design Automation Conference (ASP-DAC). Dr. Chen serves as the publication chair of ISLPED 2022/2021, chair of SIGDA University Booth at DAC 2022/2021, web and registration chair of GLSVLSI 2022, proceedings chair of ASAP 2021, arrangement chair of GLSVLSI 2021. Dr. Chen also serves on the editorial board of IEEE Circuits and Systems Magazine (CAS-M). She is a technical reviewer for over 30+ international conferences/journals, such as IEEE TC, IEEE TCAS-I, IEEE TNNLS, IEEE D&T, IEEE IoT-J, ACM TACO, ACM TODAES, ACM JETC, etc.

Reasearch highlights

Prof Chen’ research interests are focused on beyond-CMOS computing, quantum machine learning, accelerator architecture for emerging applications. Her latest work on quantum machine learning investigates fundamentally novel quantum equivalent of deep learning frameworks derived from the working principles of quantum computers, paving the way for general-purpose quantum algorithms on noisy intermediate-scale quantum devices. Another notable contribution of Prof. Chen’s work is accelerator architecture designs for emerging applications including deep learning and bioinformatics. The memory and computing requirements of such big-data applications pose significant technical challenges for their adoption in a broader range of services. Prof. Chen investigates how system/architecture/algorithm co-designed domain-specific accelerators can help on performance and energy efficiency. Prof. Chen’s works have been recognized by the academic community and appeared in top conferences, such as HPCA, DAC, ICCAD, DATE, ISLPED, ASP-DAC, and ESWEEK. Her research on “System Support for Scalable, Fast, and Power-Efficient Genome Sequencing” has been honored with the National Science Foundation Faculty Early Career Development CAREER Award.