May 1st, 2022
Real-Time Embedded Systems, Non-Volatile Memories, Architecture-Aware Software Design, Resource-Constrained Machine Learning
Dr.-Ing. Kuan-Hsun Chen is an assistant professor at the Chair of Computer Architecture and Embedded Systems (CAES) for the University of Twente in the Netherlands. He earned his Ph.D. degree (05.2019) in Computer Science (Dr.-Ing.) from TU Dortmund University, Germany with distinction (summa cum laude), and his master’s degree in Computer Science at National Tsing Hua University in Taiwan. He has published more than 40 scientific works in top peer-reviewed journals and international conferences. His key research interests are in design for real-time embedded systems, non-volatile memories, architecture-aware software design, and resource-constrained machine learning. Dr. Chen currently serves as Associate Editor in the journal of AIMS Applied Computing and Intelligence (AIMS-ACI) and Guest Editor for the Journal of Signal Processing Systems (JSPS). He is also a Technical Program Committee (TPC) member for various leading international conferences in the computer science area like Real-Time Systems Symposium (RTSS), International Conference on High Performance Computing, Data, & Analytics (HiPC), and others. He is also a reviewer for many peer-reviewed journals and conferences (TC, TECS, TCPS, RTAS, IROS, ECML PKDD) in computer science. Dr. Chen holds one best student paper award at RTCSA’18, one best paper nomination at DATE’21, and one dissertation award at TU Dortmund University in 2019. He was granted by the German Academic Exchange Service (DAAD) one research project as Principal Investigator and one personal grant for postdoctoral exchange in Japan for the Summer of 2021. He is also a volunteer mentor in the European Space Agency (ESA) Summer of Code in Space (2017) and Google Summer of Code since 2016 for open-source development on a popular real-time operating system, namely RTEMS.
Embedded systems in various safety-critical domains, such as computing systems in automotive and avionic devices, are important for modern society. Due to their intensive interaction with the physical environment, where time naturally progresses, the correctness of the system depends not only on the functional correctness of the delivered results but also on the timeliness of the instant at which these results are delivered. Dr. Chen’s research results cover a wide range of scientific issues in such areas, and two central-most research areas are as follows: Dependable Real-Time Systems: Along with technology shrinking, the presence of hardware faults is growing, which risks the correct system behavior. Against such faults, software tolerance techniques are prominent due to their flexibility. However, their time overhead also makes timeliness a pressing issue. Under this context, three kinds of treatments are studied: 1) In soft real-time systems, occasional deadline misses are acceptable. A series of analyses for the probability of deadline misses are developed. The most effective one is to efficiently derive safe upper bounds on the probability of deadline misses with several magnitude speed-up, in comparison to conventional convolution-based approaches (https://ieeexplore.ieee.org/abstract/document/7993392). 2) By modeling inherent safety margin in applications, soft errors can also be safely ignored in control applications. A runtime adaptive method is thus developed to only compensate when it is necessary while satisfying hard real-time constraints. This work was presented in LCTES’16 and published in ACM SIGPLAN (https://dl.acm.org/doi/abs/10.1145/2980930.2907952). 3) On multi-core systems, several approaches are developed to optimize the system reliability via the deployment of redundant multithreading. A reliability-driven task mapping technique is developed for homogeneous multi-core architectures with reliability and performance heterogeneity, which was published in IEEE Transactions on Computers (https://ieeexplore.ieee.org/abstract/document/7422036). Architecture-Aware Software Design: To unleash the scarce computational power on embedded systems, he focuses on how to exploit a given architecture, especially for data analysis applications, e.g., data mining and machine learning. He develops code generators to automate the optimization of the memory layouts for the tree-based inference model. Given a trained model, the optimized code sessions are generated in C++ to reduce cache misses for various CPU architectures and speed up the runtime. This work is recently published in ACM Transactions on Embedded Computing Systems (https://dl.acm.org/doi/abs/10.1145/3508019). He also works on the system design for non-volatile memories, which feature several advantages like low leakage power, high density, and low unit costs. However, they also impose novel technical constraints, especially limited endurance. His research results on software-based memory analyses, wear-leveling approaches, etc. One highlight is the exploration of energy-aware real-time scheduling for hybrid memory architectures. In this work, a multi-processor procrastination algorithm (HEART) is proposed, based on partitioned earliest-deadline-first (pEDF) scheduling, which facilitates reducing energy consumption by actively enlarging the hibernation time. This work was presented in EMSOFT’21 and published in ACM Transactions on Embedded Computing Systems (https://dl.acm.org/doi/abs/10.1145/3477019).