CADathlon 2017 Contest Problems and References

Problems and References

 
Problem 1: Circuit Design & Analysis
Contributed by Aosen Wang (SUNY Buffalo) and Wenyao Xu (SUNY Buffalo)
Overview: Efficient Cascaded Classifier Layout Identification
Aosen Wang, Chen Song, Zhanpeng Jin and Wenyao Xu, "Adaptive compressed sensing architecture in wireless brain-computer interface," 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, 2015, pp. 1-6.

Problem 2: Physical Design
Contributed by: Hua-Yu Chang (Synopsys) and Iris Hui-Ru Jiang (National Taiwan University)
Overview: Flip-flop Clustering
I. H.-R. Jiang, C.-L. Chang, Y.-M. Yang, "INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving," IEEE TCAD, vol. 31, no. 2, pp. 192-204, Feb. 2012.
 
Problem 3: Logic & High-Level Synthesis
Contributed by Jacky Hsu (Cadence)
Language: Python 3
Overview: Optimization of Polynomial Datapaths Using Finite Ring Algebra (structural/boolean matching)
a. S. Gopalakrishnan and P. Kalla. "Optimization of polynomial datapaths using finite ring algebra." ACM TODAES, vol. 12, no. 49, 49:1-49:30, Sep. 2007.
N. Shekhar, P. Kalla, M. B. Meredith and F. Enescu, "Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 4, pp. 376-387, April 2008.
 
Problem 4: System Design and Analysis
Contributed by: Wei-Ming Cheng (National Taiwan University) and Pi-Cheng Hsiu (Academia Sinica)
Overview: Value-based Task Scheduling for Nonvolatile Processor
W. M. Chen, T. S. Cheng, P. C. Hsiu and T. W. Kuo, "Value-Based Task Scheduling for Nonvolatile Processor-Based Embedded Devices," 2016 IEEE Real-Time Systems Symposium (RTSS), Porto, 2016, pp. 247-256.
 
Problem 5: Verification
Contributed by: JV Rajendran (Texas A&M University) and Jiang Hu (Texas A&M University)
Overview: Split Manufacturing
Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan Rajendran: The cat and mouse in split manufacturing. DAC 2016: 165:1-165:6
More reading (suggested but not necessary): Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri: Is split manufacturing secure? DATE 2013: 1259-1264
Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan J. V. Rajendran: Routing perturbation for enhanced security in split manufacturing. ASP-DAC 2017: 605-510
 
Problem 6: Future technologies (Security)
Contributed by: JV Rajendran (Texas A&M University) and Ozgur Sinanoglu (NYU Abu Dhabi)
Tools: 1. Minisat - http://minisat.se/
2. Crypto Minisat (CMSAT) - https://github.com/msoos/cryptominisat .
Overview: Attack on Logic Locking  
Pramod Subramanyan, Sayak Ray, Sharad Malik: Evaluating the security of logic encryption algorithms. HOST 2015: 137-143
More reading (suggested but not necessary): Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, Ramesh Karri: Security analysis of logic obfuscation. DAC 2012: 83-89
Duo Liu, Cunxi Yu, Xiangyu Zhang, Daniel E. Holcomb: Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits. DATE 2016: 433-438