1 November 2012, Vol. 42, No. 11
Online archive: http://www.sigda.org/newsletter
Comments from the Editors
Dear ACM/SIGDA members,
In this issue, we have a very interesting article on Thermal
Simulation. If you are interested in contributing to this column in
the future, please contact Srinivas Katkoori <firstname.lastname@example.org>.
An article only needs to be about 1 page long with several references.
All articles are included in the ACM digital library and there is no
restriction for the reproduction of the article for printed
Sudeep Pasricha, E-Newsletter Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Srinivas Katkoori, E-Newsletter Associate Editor
Prabhat Mishra, E-Newsletter Associate Editor
"TechCon keynote: Move bits, not atoms"
Improving energy efficiency is the way the electronics industry must go, but it
is important to also take a system-level view of issues, according to Professor
Jonathon Koomey, recently appointed as research fellow at the Steyer-Taylor
Center for Energy Policy and Finance at Stanford University.
"Microprocessor server benchmarks seen as irrelevant"
Server design--and by extension microprocessor and component
considerations--are now driven by new-media companies such as Facebook and
Google, whose system specifications render traditional benchmarks useless.
"The x86 is dead. Long live the x86"
Technologies never die. Like sine waves, they just rise and fall and rise
again. So it is and will be with the Intel x86 microprocessor architecture. What
was once a wimpy core among a forest of superscalar and Reduced Instruction
Set Computing Architectures, the x86 came to dominate.
"IBM claims carbon nanotube IC breakthrough"
Researchers from IBM Corp. have demonstrated a new approach to carbon
nanotechnology that they say opens up the path for commercial fabrication of
chips with transistors made of carbon nanotubes.
"Princeton researchers claim quantum computing breakthrough"
Researchers from Princeton University have developed a technique to read
spintronic information off electrons, a potential step on the road to
"Imagination tools graphics cores for 28 nm"
Imagination Technologies is integrating details of process technologies
at 28 nm and beyond into the designs of its graphics cores. The effort
is aimed at helping SoC designers better optimize the graphics blocks
around power consumption, performance and area.
"MIT applies invisibility to electronics"
Researchers from the Massachusetts Institute of Technology (MIT) are
applying technology developed for the visual cloaking of objects to
enable particles to "hide" from passing electronics, which could lead
to more efficient thermoelectric devices and new kinds of electronics.
"London Calling: How to save Moore's Law"
One way to save Moore's Law from an unpleasant and industry-disrupting demise
is for manufacturing process technology developers to make a series of changes
at a given node – say 20-nm – but label each successive change with a smaller
"Software framework helps designers to develop car-to-x applications"
At the ITS World Congress 2012 to be held later this year in Vienna,
Scientists from Fraunhofer ESK will demonstrate the car-to-x framework
they developed. By means of the platform, developers can implement
complex car-to-x applications such as collaborative driver assistance systems.
"EETimes' Silicon 60: Hot startups to watch"
EE Times latest Silicon 60, our list of emerging startups, adds 17
innovators in version 14.0. (Our version 13.0 list, from April, is here.
The newcomers include EDA, memory technology and processor companies along
with sensors and haptics, wireless communications, power semiconductors,
optoelectronics, audio and security.
"EDA extends sales growth streak"
EDA revenue grew to $1.59 billion in the second quarter, up 11 percent from the
second quarter of 2011, according to the EDA Consortium (EDAC).
"Latest Release of Synplify Software Cuts Days off FPGA Implementation Time"
Synopsys, Inc. (Nasdaq: SNPS), a global leader accelerating innovation in the
design, verification and manufacture of chips and systems, today announced the
latest release of the Synopsys Synplify Pro® and Synplify® Premier FPGA
synthesis tools. The 2012.09 Synplify releases include new multiple error
isolation and incremental fix capabilities that accelerate FPGA implementation.
These features enable FPGA designers and engineers deploying FPGA-based
prototypes such as Synopsys' HAPS systems to cut weeks off their design project
"Cadence Announces Tapeout of 14nm Test-Chip With ARM Processor and IBM
FinFET Process Technology"
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic
design innovation, announced today the tapeout of a 14-nanometer test-chip
featuring an ARM Cortex®-M0 processor implemented using IBM's FinFET process
technology. The successful tapeout is the result of close collaboration
between the three technology leaders as they teamed to build an ecosystem
to address the new challenges from design through manufacturing inherent
in a 14-nanometer FinFET-based design flow.
What is Thermal Simulation?
University of California, Santa Cruz
Temperature is becoming even more important for micro-electronics because of
the high power densities that can be found in current microprocessors.
Nowadays, dies can reach 1W/mm^2 power density. To put it in context, current
systems have around an order or magnitude more power density than a hot plate,
and approximately the same power density of that of a nuclear reactor. If left
unmanaged, this high power densities create temperatures that make the
processor not operational.
Temperature is important not only because it can melt your chip but also
because it is a factor with an exponential impact in leakage power and chip
reliability. Temperature also has an impact of propagation delay. For all these
reasons, thermal simulation of modern SoC is a must.
Heat propagates through only three methods: conduction, convection, and
radiation. Conduction happens through solids and it is considered by any
thermal simulation infrastructure for SoCs. Convection is the heat transfer
when a liquid and/or a gas is involved. Convection is able to transfer heat
much faster than conduction. Radiation is the slowest heat transfer method, and
typically it is only considered in electronics for satellites due to the lack
of overall system convection.
If power consumption transients are not considered, temperature can be
approximated with an array of resistors. The more efficient that the
temperature transfers due to conduction, convection, and/or radiation, the
lower the resistance. This simple approximation tend to be used for heat sink
and high level designs.
Since power consumption in current microelectronics does not tend to be
constant, current designers should consider thermal transients. This
complicates the simulation as it requires to solve differential equations.
Nevertheless, the majority of the thermal simulation infrastructure models
[1, 2, 3] use a mesh of resistors and capacitors to find junction temperatures.
This is a time intensive computation with a cubic cost in relationship with the
thermal granularity considered in the model.
To accelerate thermal simulations for SoC, some common tools like HotSpot 
have several degrees of accuracy and parallelism support. Other proposed more
efficient thermal solver algorithms that leverage the slow temperature
propagation [4, 6], and other propose to apply statistical sampling to perform
detailed simulation only during some time periods .
Although the basic thermal principles have been known for a long time,
the never ending feature shrink is posing new challenges. Specifically, having
structure with just a few atoms breaks the statistical assumption of
thermodynamic laws. This fine grain modeling is a area with several open
In summary, thermal simulation is a must have component in modern SoC whenever
leakage and reliability is considered. It is also an important factor for high
frequency designs because it also affects timing. There are several models and
tools available that allow fast modeling, and some of them are free.
 Sang-Soo Lee; Allstot, D.J.; , "Electrothermal simulation of integrated
circuits," Solid-State Circuits, IEEE Journal of , vol.28, no.12, pp.1283-1293,
Dec 1993 doi: 10.1109/4.262001
 Y.K. Cheng, P. Raha, C.C. Teng, E. Rosenbaum, and S.M. Kang. "ILLIADS-T:
An Electrothermal Timing Simulator for Temperature-Sensitive Reliability
Diagnosis of CMOS VLSI Chips." IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, 17(8):1434-1445, Aug 1998
 K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D.
Tarjan. "Temperature-Aware Microarchitecture." In Proceedings of the 30th
International Symposium on Computer Architecture, pp. 2-13, June 2003.
 Ting-Yuan Wang, Yu-Min Lee, and Charlie Chung-Ping Chen. 2003. "3D
thermal-ADI: an efficient chip-level transient thermal simulator." In
Proceedings of the 2003 international symposium on Physical design (ISPD '03).
 Ehsan K.Ardestani, Elnaz Ebrahimi, Gabriel Southern, and Jose Renau,
"Thermal-Aware Sampling in Architectural Simulation," International
Low Power Electronics and Design (ISLPED), August 2012.
 T. Kemper, Y. Zhang, Z. Bian, and A. Shakouri, "Ultrafast Temperature
Profile Calculation in IC chips," Proc. of 12th International Workshop on
Thermal investigations of ICs (THERMINIC), Nice, France, pp. 133-137,
NOCS'13 – Int’l Symposium on Networks-on-Chip
Deadline: Nov 26, 2012 (Abstracts due: Nov 19, 2012)
Apr 21-24, 2013
DAC'13 – Design Automation Conference
Deadline: Dec 3, 2012 (Abstracts due: Nov 27, 2012)
User track deadline: Feb 6, 2013
Jun 2-6, 2013
HOST'13 – International Symposium on Hardware-Oriented Security and Trust
Deadline: Dec 10, 2012
June 2-3, 2013
ASYNC'13 – Int’l Symposium on Asynchronous Circuits and Systems
Santa Monica, CA
Deadline: Dec 14, 2012 (Abstracts due: Dec 7, 2012)
May 19-22, 2013
TAU'13 – Int’l Workshop on Timing Issues in the Specification and
Synthesis of Digital Systems
(co-located with ISPD’13)
Deadline: Dec 18, 2012
Mar 27-29, 2013
MSE'13 - Microelectronics Systems Education
Deadline: Jan 15, 2013
Jun 2-3, 2013
ICCAD’12 – Int’l Conference on Computer-Aided Design
San Jose, CA
Nov 5-8 2012
HLDVT’12 – Int’l High-Level Design, Validation and Test Workshop
Huntington Beach, CA
Nov 9-10, 2012
BIOCAS'12 - Biomedical Circuits and Systems Conference
Nov 28-30, 2012
MICRO'12 - Int'l Symposium on Microarchitecture
Dec 1-5, 2012
ICFPT'12 - Int'l Conference on Field-Programmable Technology
Dec 10-12, 2012
ICPADS'12 - Int'l Conference on Parallel and Distributed Systems
Dec 17-19, 2012
HiPC'12 - Int'l Conference on High Performance Computing
Dec 18-21, 2012
ISED’12 – Int’l Symposium on Electronic System Design
Dec 19-22, 2012
VLSI'13 - Int'l Conference on VLSI Design
Jan 5-10, 2013
HiPEAC'13: Int'l Conference on High Performance Embedded Architectures &
Jan 21-23, 2013
ASP-DAC'13 - Asia and South Pacific Design Automation Conference
Jan 22-25, 2013
ISSCC'13 - Int'l Solid-State Circuits Conference
San Francisco, CA
Feb 17-21, 2012
ISQED'13 - Int'l Symposium on Quality Electronic Design
Santa Clara, CA
Mar 11-13, 2013
DATE'13 - Design Automation and Test in Europe
Mar 18-22, 2013
ISPD’13 – Int’l Symposium on Physical Design
(co-located with TAU’13)
Lake Tahoe, CA
Mar 24-27, 2013
ISCAS'13 - Int'l Symposium on Circuits and Systems
May 19-23, 2013
Office of Naval Research (ONR) Summer Faculty Research Program
Deadline: December 05, 2012
National Defense Science and Engineering Graduate (NDSEG) Fellowship Program
Deadline: December 16, 2012
Office of Naval Research (ONR) Sabbatical Leave Program
Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Early Career Research Program
Deadline: November 26, 2012
Robust Computational Intelligence - AFOSR-BAA-2012-01
Systems and Software - AFOSR-BAA-2012-01
ERDC BAA - Computational Science and Engineering (ITL-1)
Advanced Distributed Sensor Technologies - BAA 57-09-06
Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01)
High Performance Computing on Massively Parallel Architectures (BAA 64-09-01)
ASEE-NRL Postdoctoral Fellowship Program
Director's Postdoctoral Fellows
Sabbaticals and Faculty Appointments
Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Information and Intelligent Systems (IIS): Core Programs
Deadline: Nov 30 (large) / Dec 17 (small), 2012
Computer and Network Systems (CNS): Core Programs
Deadline: Nov 30 (large) / Dec 17 (small), 2012
Computing and Communication Foundations (CCF): Core Programs
Deadline: Nov 30 (large) / Dec 17 (small), 2012
Communications, Circuits, and Sensing-Systems (CCSS)
Deadline: November 1, 2012
Energy, Power and Adaptive Systems (EPAS)
Deadline: November 1, 2012
Communications, Circuits, and Sensing-Systems (CCSS)
Deadline: November 1, 2012
Graduate Research Fellowship Program (GRFP)
Deadline: November 13, 2012
Secure and Trustworthy Cyberspace (SaTC)
Deadline: Nov 30 (medium) / Dec 14 (small), 2012
Cyber-Enabled Sustainability Science and Engineering (CyberSEES)
Deadline: Dec 4, 2012 (LOI) / Feb 5, 2013
Expeditions in Computing
Deadline: December 10, 2012
National Robotics Initiative (NRI)
Deadline: December 11, 2012 (small) / January 23, 2013 (large)
Cyber-Physical Systems (CPS)
Deadline: January 29, 2013
Core Techniques and Technologies for Advancing Big Data Science & Engineering
Deadline: June 13, 2013
Young Investigator Program (YIP)
Deadline: Jan 4, 2013
Paris, France, May 2-4 2013
Sponsored by ACM SIGDA, with Technical Support of IEEE CEDA
The 23rd edition of GLSVLSI will be held in Paris, France and collocated with
the ACM European Computing Research Congress (ECRC), http://ecrc.acm.org.
Original, unpublished papers describing research in the general area of
VLSI are solicited. Both theoretical and experimental research results are
welcome. Proceedings will be published by the ACM and will be available through
the ACM Digital Library. For more information, visit http://www.glsvlsi.org/.
> VLSI Design: design of ASICs, microprocessors/micro-architectures, embedded
processors, analog/digital/mixed-signal systems, NoC, interconnects, memories,
> VLSI Circuits: analog/digital/mixed-signal circuits, RF and communication
circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits.
> Computer-Aided Design (CAD): hardware/software co-design, logic and
behavioral synthesis, logic mapping, simulation and formal verification,
layout (partitioning, placement, routing, floorplanning, compaction),
algorithms and complexity analysis
> Low Power and Power Aware Design: circuits, micro-architectural techniques,
thermal estimation and optimization, power estimation methodologies, and
> Testing, Reliability, Fault-Tolerance: digital/analog/mixed-signal testing,
design for testability and reliability, online testing techniques, static
and dynamic defect- and fault-recoverability, and variation-aware design
> Emerging Technologies: nano technology, molecular electronics, quantum
devices, biologically-inspired computing, CNT, SET, RTD, QCA, VLSI aspects
of sensor and sensor networks, and CAD tools for emerging technology devices
> Post-CMOS VLSI: evolutionary computing, optical computing, quantum computing,
reversible logic, spin-based computing, biological computation, nanotechnology,
molecular electronics, quantum devices, biologically-inspired computing.
Emphasis should be on the analysis, novel circuits and architectures,
modeling, CAD tools, and design methodologies.
Paper submission deadline: December 15, 2012
Acceptance Notification: February 15, 2013
Camera-Ready Paper Due: March 1, 2013
Paper Submission: Authors are invited to submit full-length (6 pages maximum),
original, unpublished papers along with an abstract of at most 200 words.
To enable blind review, the author list should be omitted from the main
document. Previously published papers or papers currently under review for
other conferences/journals should not be submitted and will not be considered.
Electronic submission in PDF format to the http://www.glsvlsi.org website
is required. Author and contact information (name, street/mailing address,
telephone, fax, e-mail) must be entered during the submission process.
Paper Format: Submissions should be in camera-ready two-column format,
following the ACM proceedings specifications located at:
and the classification system detailed at: http://www.acm.org/class/1998
Paper Publication and Presenter Registration: Papers will be accepted for
regular or poster presentation at the symposium. Every accepted paper
MUST have at least one author registered to the symposium by the time the
camera-ready paper is submitted; the author is also expected to attend the
symposium and present the paper.
Jose L. Ayala - Complutense Univ. of Madrid, Spain
Alex K. Jones - University of Pittsburgh, USA
Patrick Madden - Binghamton University, USA
Ayse Coskun - Boston University, USA
Theocharis Theocharides - University of Cyprus, Cyprus
David Atienza - EPFL, Switzerland
Iris Bahar - Brown University, USA
Sanjukta Bhanja - University of South Florida, USA
Erik Brunvand - University of Utah, USA
Joseph Cavallaro - Rice University, USA
Fabrizio Lombardi - Northeastern University, USA
Enrico Macii - Politecnico di Torino, Italy
Ken Stevens - University of Utah, USA
Yuan Xie - Penn State University, USA
Tong Zhang - Rensselaer, USA
April 21-24, 2013
Tempe, Arizona, USA
The International Symposium on Networks-on-Chip (NOCS) is the premier event
dedicated to interdisciplinary research on on-chip and chip-scale communication
technology, architecture, design methods, applications and systems. NOCS brings
together scientists and engineers working on NoC innovations and applications
from inter-related research communities, including computer architecture,
networking, circuits and systems, embedded systems, and design automation.
Topics of interest include, but are not limited to:
NoC architecture and implementation
- Network architecture (topology, routing, arbitration)
- NoC Quality of Service
- Timing, synchronous/asynchronous communication
- NoC reliability issues
- Network interface issues
- NoC design methodologies and tools
- Signaling & circuit design for NoC links
- Physical design of interconnect & NoC
NoC analysis and verification
- Power, energy & thermal issues (at the NoC, un-core and/or system-level)
- Benchmarking & experience with real NoC-based hardware
- Modeling, simulation, and synthesis of NoCs
- Verification, debug & test of NoCs
- Metrics and benchmarks for NoCs
- Mapping of applications onto NoCs
- NoC case studies, application-specific NoC design
- NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
- NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
- Network design for 2.5D & 3D stacked logic and memory
NoC at the un-core and system-level
- Design of memory subsystem (un-core) including memory controllers, caches,
cache coherence protocols & NoCs
- NoC support for memory and cache access
- OS support for NoCs
- Programming models including shared memory, message passing and novel
- Multi/many-core workload characterization & evaluation
- Optical, RF, & emerging technologies for on-chip/inpackage interconnects
- Issues related to large-scale systems (datacenters, supercomputers) with
NoC-based systems as building blocks
Electronic paper submission requires a full paper, up to 8 double-column IEEE
format pages, including figures and references. The program committee in a
double-blind review process will evaluate papers based on scientific merit,
innovation, relevance, and presentation. Submitted papers must describe
work that has not been published before or is under review by another
at the same time. Each submission will be checked for any significant
to previously published works or for simultaneous submission to other archival
venues, and such papers will be rejected. Furthermore, NOCS will notify the
technical chair of the venue where the duplicate was submitted. Please see the
paper submission instructions for details.
Proposals for tutorials, special sessions, and panels are also invited. Please
see the detailed submission instructions for paper, tutorial, special sessions,
and panel proposals at the submission page. A special section related to the
theme of the conference will be organized in one of the IEEE journals.
Abstract registration deadline
Nov 19, 2012
Full paper submission deadline
Nov 26, 2012
Proposals for tutorials, special sessions and panels Jan 11, 2013
Notification of acceptance
Feb 1, 2013
Final version due
Mar 1, 2013
Karam S. Chatha, Arizona State University, USA
Chita R. Das, Penn State University, USA
Sudeep Pasricha, Colorado State, USA
Mohammed Al Faruque, Siemens, USA
Carole Jean Wu, Arizona State University, USA
John Bainbridge, Sonics Inc., USA
Natalie Enright Jerger, University of Toronto, CA
Paul Gratz, Texas A&M, USA
Zhonghai Lu, KTH, Sweden
Umit Ogras, Intel, USA
February 7-8, 2013
Field-coupled nanocomputing (FCN) utilizes local field interactions between
nanoscale building blocks to transfer information and implement logic without
the need for charge transport. Each of the leading FCN paradigms - quantum dot
cellular automata (QDCA), molecular quantum cellular automata (MQCA), and
nanomagnetic logic (NML) –is a potential candidate for post-CMOS
and each faces critical challenges to realization.
FCN’13 will provide a dedicated forum for assessment of the current status of
this emerging field, identification of critical challenges for FCN, and
of potential strategies for realization of FCN-based nanocomputers. This
is sponsored by National Science Foundation (NSF).
- Enabling FCN device, circuit, and architecture concepts.
- Scalable nanomanufacturing strategies for FCN circuits and systems.
- Clocking strategies and issues.
- Heat dissipation in FCN paradigms.
- Noise, defects, error correction, and fault tolerance.
- Reversible computing in FCN.
- Evolution of the QCADesigner simulation tool.
- Circuit design, CAD, and logic synthesis.
Abstract Deadline: Two-page extended abstract due November 15, 2012.
Kenote Speakers: Professor Craig Lent (Notre Dame), Professor Wolfgang Porod
(Notre Dame), and Professor Robert Wolkow (U of Alberta).
Panel Discussion: “Critical Challenges for FCN and the Road Ahead”
Graduate Student Support: Graduate student presentations are particularly
encouraged, and a number of stipends for travel and lodging will be available
for graduate student authors.
Workshop Proceedings: High quality, chapter-length expositions of the workshop
contributions will be solicited for publication in book form. Also included in
the FCN’13 proceedings will be an edited transcript of the panel
FCN’13 Organizers: Sanjukta Bhanja (USF) and Neal Anderson (UMass Amherst).
Call for Papers: Workshop on Virtual Prototyping of Parallel and Embedded
May 24th, Boston, USA
(in conjunction with IPDPS)
1st Workshop on Virtual Prototyping of Parallel and Embedded Systems ViPES,
The 1st Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES
2013) will be held in Boston, USA in May 2013. ViPES 2013 is associated with
the 27th Annual International Parallel & Distributed Processing Symposium
(IPDPS 2013) and is sponsored by the IEEE Computer Society's Technical
Committee on Parallel Processing.
Virtual prototyping stands for the development of hardware/software
systems without using a real hardware prototype, i.e. no printed circuit
board with electronic devices such as processors, field programmable gate
arrays, peripherals and other devices is needed. The advantage is the
possibility to exchange parts in the system setup with faster turnaround
times in comparison to the traditional development process, where a time
consuming redesign of the complete board has to be done. Since some years,
the community exploiting these novel methods has grown as time to market
plays a major role in industry. Additionally, the increasing complexity
of embedded systems, which are more and more realized as parallel and
distributed cyber-physical system, forces to perform a time-consuming design
space exploration. For academics virtual prototyping is a hot topic and
is used to develop future systems and to enable an outlook into the next
generation of embedded systems and devices. The wide range of application
scenarios for this type of development includes amongst others automotive,
avionics, railway and medicine applications. This workshop targets the domain
of virtual prototyping focusing the following topics:
- Virtual prototyping development tools
- Methods for virtual prototyping of complex systems
- Application development with virtual platforms
- Methods for Hardware / Software Codesign with virtual platforms
- Design space exploration for parallel and distributed multicore and
- Estimation of system characteristics in an early stage of development
- Functional verification at a high level of abstraction
- Methods for modeling of IP cores with SystemC
- Usage of Architecture Description Languages (ADL) for IP core development
All manuscripts will be reviewed by at least three members of the program
committee. Submissions should be a complete manuscript (not to exceed 6
pages of single spaced text, including figures and tables. Submissions
should be in PDF-format. Templates for paper preparation can be found at:
IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a
printed volume. The complete symposium and workshop proceedings will also
be published by IEEE CS Press as a CD-ROM disk. Submitted papers should
not have appeared in or be under consideration for a different workshop
or conference. The 5 best ranked papers (according to the review results)
will be invited to submit an extended version to ACM TECS journal.
Submission deadline: December 21st, 2012
Decision notification: February 1st, 2013
Camera ready paper due: February 28st, 2013
The submission interface via EDAS is available under
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