1 October 2012, Vol. 42, No. 10
Online archive: http://www.sigda.org/newsletter
Comments from the Editors
Dear ACM/SIGDA members,
In this issue, we have a very interesting article on Protein
Identification. If you are interested in contributing to this column in
the future, please contact Srinivas Katkoori <firstname.lastname@example.org>.
An article only needs to be about 1 page long with several references.
All articles are included in the ACM digital library and there is no
restriction for the reproduction of the article for printed
Sudeep Pasricha, E-Newsletter Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Srinivas Katkoori, E-Newsletter Associate Editor
Prabhat Mishra, E-Newsletter Associate Editor
"Plan emerges to link IP protection, China investors"
China is big. China is not homogeneous. It has a poor record of protecting intellectual
property. But it also has plenty of government funding at the central, provincial
and municipal levels to go along with a massive domestic market for new technologies
and products. Add up the pluses and minuses and the Chinese market is a mixed bag.
"Xilinx All Programmable FPGAs used in robotic-assisted surgical app"
The folks from Xilinx are bouncing around with excitement because they were presented
with an Outstanding Achievement award at the Electronic Product Design e-Legacy Awards
2012 event in London earlier this month.
"Erbium on silicon chip speeds up light"
A researcher has demonstrated that the rare earth material erbium can be integrated
with silicon for the first time to amplify an optical signal.
"Teardown: Inside Apple's iPhone 5"
Apple is considered the leader in the smartphone market. In five years, the company
has generated more than $150 billion in revenue from the iPhone family of handsets
and accessories, according to research firm Strategy Analytics. More than 100 million
iPhones have been sold.
"A peek inside Apple's A6 processor"
Apple Inc.'s A6—the processor powering its new iPhone 5—is likely fabricated by
South Korea's Samsung Electronics Co. Ltd. and may employ ARM's "big-little" graphics
processor core scheme, according to a preliminary teardown of the handset done by UBM
"Researchers develop printable lasers"
Scientists from the University of Cambridge have reported a way of making organic
lasers using inkjet printing technology. The breakthrough has implications for a wide
range of potential applications from disposable lab-on-film test kits to arrays of
colored lasers for low-cost emissive displays.
"Intel's Haswell: a viable platform for tablets?"
Recently at the Intel Developer Forum (IDF), EE Times had the opportunity to sit
down one to one with Intel’s executive vice president, David (Dadi) Perlmutter,
general manager of the firm’s architecture group. Perlmutter was particularly
excited about Intel’s upcoming fourth generation core processor--Haswell-- which
has already made significant strides in terms of balancing high performance with much
lower power than previous generations.
"U.S. boosts funding for nanotech deployment"
Three new university research centers to be funded by the National Science Foundation
will focus on developing nanotechnology systems that could be used in electromagnetic,
mobile computing, energy and manufacturing.
"German research project aims to improve energy distribution in smart grid
The German Federal Ministry of Education and Research (BMBF) is supporting "Energy
To Smart Grid" (E2SG), a major European energy research project. Six German partners
are working on new technologies for distributing power from the producer to the end
"The Measure of Nanometer Silicon Success"
I was speaking with experts at Mentor about the latest developments in back-end
physical verification (PV) and design-for-manufacturing (DFM). It prompted me to take a
look at what has changed and what will be essential going forward. Here is what I see for
this critical area for IC implementation.
"Oscillating microscopic beads could be key to biolab on a chip"
MIT team finds way to manipulate and measure magnetic particles without contact,
potentially enabling multiple medical tests on a tiny device.
"Researchers move quantum computing to silicon"
Quantum computing has been brought a step closer to mass production by a research
team led by scientists from the University of Bristol that has made a transition
from using glass to silicon.
What is Protein Identification?
Jason Gallia and Patrick Madden
Protein identiﬁcation is the task of determining the amino acid sequence
that makes up an unknown molecule, given limited information. In this article,
we describe collaborative work between design automation researchers and
biochemists, focusing on the identiﬁcation of proteins from mass spectrometer
data. There are surprising connections to techniques used in detailed placement
and legalization which we have adapted and applied in a novel way.
Proteins molecules are a key part of the functionality of cells in living
organisms. No matter what the organism is, the proteins are constructed from a
linked chain of amino acids; there are twenty types of amino acids. The way in
which the amino acids are arranged in the chain determines the functionality.
Determining which proteins are present can help a biologist better understand
functionality, which can in turn lead to new ways to ﬁght viruses as well better
methods to detect disease.
There are two primary methods for identiﬁcation of a proteins. The ﬁrst
method, Edman degradation, is performed through a series of chemical experiments
which remove a single amino acid at a time from a chain. Though this
method is very accurate, it is also time consuming and expensive.
The second method involves the use of a machine called a tandem mass
spectrometer, MS/MS. A mass spectrometer gathers proteins with similar mass,
and then breaks these into fragments, with cleavage normally occuring along
amino acid bonds. The mass of each fragment can be measured very precisely;
the quantity of fragments observed at for any given mass value are recorded,
giving a spectrum view of the protein.
Typical methods to identify proteins from a spectra rely heavily on ﬁngerprint
style matching with a large database; two well known tools for this are
SEQUEST and Mascot. If the protein has never been sequenced before,
however, database matching will fail to give a correct result. Other approaches
such as PEAKS, and the one developed by our lab, use a method called de
novo sequencing. De novo sequencing uses algorithmic methods to determine the
amino acid sequence from the spacings and positions directly from the MS/MS
The approach we employ is inspired by an integer knapsack approach to
placement legalization. In the placement work, individual cells were
considered one by one, with the cost of assigning a cell to a particular location
being equal to the physical displacement of the cell. The cost for legalization
of an entire row is simply the sum of individual cell costs, allowing dynamic
programming to be applied.
For protein identiﬁcation, one can simply replace displacement cost with a
metric that examines the spectra for peaks that would correspond to expected
ions. To give a greatly simpliﬁed example, if there were only three amino acids,
with masses of four, ﬁve, and six respectively, a protein with mass of ten might
have a “spike” in the spectrum at the mass value of ﬁve – or it might have two
spikes, one at four, and one at six. Using the known masses for the amino acids,
and the spike locations observed in a spectra, one can determine amino acid
sequences that could have generated the spectra.
There is growing interest in cross-disciplinary work; our group brings together
researchers from computer aided design and biochemistry to pursue problems of
common interest. Numerical techniques for placement legalization have
been adapted to handle a challenging problem in biochemistry, and we see many
further opportunities. While the optimization objectives are quite diﬀerent,
many of the underlying challenges are similar.
 A. R. Agnihotri, M. C. Yildiz, A. Khatkhate, A. Mathur, S. Ono, and P. H.
Madden. Fractional Cut: Improved recursive bisection placement. In Proc.
Int. Conf. on Computer Aided Design, pages 307–310, 2003.
 J. Gallia, A. Tan-Wilson, and P. H. Madden. De novo protein identiﬁcation
by dynamic programming (poster). In ICCABS 2011, 2011.
 J. R. Yates III. Database searching using mass spectrometry data.
Electrophoresis, 19(6):893–900, 1998.
 Michael Kinter and Nicholas E. Sherman. Protein Sequencing and Identiﬁ-
cation Using Mass Spectrometry. Wiley-Interscience, 2000.
 Bin Ma, Kaizhoung Zhang, Christopher Hendrie, Chengzhi Liang, Ming Li,
Amanda Doherty-Kirby, and Gilles Lajoie. Peaks: powerful software for
peptide de novo sequencing by tandem mass spectrometry. Rapid Communications
In Mass Spectrometry, 2003.
 D. N. Perkins, D. J. C. Pappin, D. M. Creasy, and J. S. Cottrell. Probability
based protein identiﬁcation by searching sequence databases using mass
spectrometry data. Electrophoresis, 1999.
ISPD’13 – Int’l Symposium on Physical Design
(co-located with TAU’13)
Lake Tahoe, CA
Mar 24-27, 2013
Deadline: Oct 1, 2012
NOCS'13 – Int’l Symposium on Networks-on-Chip
Deadline: Nov 26, 2012 (Abstracts due: Nov 19, 2012)
Apr 21-24, 2013
ASYNC'13 – Int’l Symposium on Asynchronous Circuits and Systems
Santa Monica, CA
Deadline: Dec 14, 2012 (Abstracts due: Dec 7, 2012)
May 19-22, 2013
DAC’13 – Design Automation Conference
Deadline: Dec 3, 2012 (Abstracts due: Nov 27, 2012)
User track deadline: Feb 6, 2013
Jun 2-6, 2013
TAU’13 – Int’l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
(co-located with ISPD’13)
Deadline: Dec 18, 2012
Mar 27-29, 2013
MSE'13 - Microelectronics Systems Education
Deadline: Jan 15, 2013
Jun 2-3, 2013
VLSI-SoC’12 – Int’l Conference on Very Large Scale Integration and System on Chip
Santa Cruz, CA
Oct 7-12, 2012
ESWEEK'12 - Embedded Systems Week (CASES, CODES+ISSS, and EMSOFT)
Oct 7-12, 2012
San Diego, CA
Oct 22-25, 2012
ICCAD’12 – Int’l Conference on Computer-Aided Design
San Jose, CA
Nov 5-8 2012
HLDVT’12 – Int’l High-Level Design, Validation and Test Workshop
Huntington Beach, CA
Nov 9-10, 2012
BIOCAS'12 - Biomedical Circuits and Systems Conference
Nov 28-30, 2012
MICRO'12 - Int'l Symposium on Microarchitecture
Dec 1-5, 2012
ICFPT'12 - Int'l Conference on Field-Programmable Technology
Dec 10-12, 2012
ICPADS'12 - Int'l Conference on Parallel and Distributed Systems
Dec 17-19, 2012
HiPC'12 - Int'l Conference on High Performance Computing
Dec 18-21, 2012
ISED’12 – Int’l Symposium on Electronic System Design
Dec 19-22, 2012
VLSI'13 - Int'l Conference on VLSI Design
Jan 5-10, 2013
HiPEAC'13: Int'l Conference on High Performance Embedded Architectures & Compilers
Jan 21-23, 2013
ASP-DAC'13 - Asia and South Pacific Design Automation Conference
Jan 22-25, 2013
ISSCC'13 - Int'l Solid-State Circuits Conference
San Francisco, CA
Feb 17-21, 2012
ISQED'13 - Int'l Symposium on Quality Electronic Design
Santa Clara, CA
Mar 11-13, 2013
DATE'13 - Design Automation and Test in Europe
Mar 18-22, 2013
ISCAS'13 - Int'l Symposium on Circuits and Systems
May 19-23, 2013
Office of Naval Research (ONR) Summer Faculty Research Program
Deadline: December 05, 2012
National Defense Science and Engineering Graduate (NDSEG) Fellowship Program
Deadline: December 16, 2012
Office of Naval Research (ONR) Sabbatical Leave Program
Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Unconventional Processing of Signals for Intelligent Data Exploitation (UPSIDE)
Deadline: October 12, 2012
Robust Computational Intelligence - AFOSR-BAA-2012-01
Systems and Software - AFOSR-BAA-2012-01
ERDC BAA - Computational Science and Engineering (ITL-1)
Advanced Distributed Sensor Technologies - BAA 57-09-06
Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01)
High Performance Computing on Massively Parallel Architectures (BAA 64-09-01)
ASEE-NRL Postdoctoral Fellowship Program
Director's Postdoctoral Fellows
Sabbaticals and Faculty Appointments
Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Information and Intelligent Systems (IIS): Core Programs
Deadline: Oct 9 (medium) / Nov 30 (large) / Dec 17 (small), 2012
Computer and Network Systems (CNS): Core Programs
Deadline: Oct 9 (medium) / Nov 30 (large) / Dec 17 (small), 2012
Computing and Communication Foundations (CCF): Core Programs
Deadline: Oct 9 (medium) / Nov 30 (large) / Dec 17 (small), 2012
CISE Computing Research Infrastructure (CRI)
Deadline: October 23, 2012
Communications, Circuits, and Sensing-Systems (CCSS)
Deadline: November 1, 2012
Energy, Power and Adaptive Systems (EPAS)
Deadline: November 1, 2012
Communications, Circuits, and Sensing-Systems (CCSS)
Deadline: November 1, 2012
Expeditions in Computing
Deadline: December 10, 2012
National Robotics Initiative (NRI)
Deadline: December 11, 2012 (small) / January 23, 2013 (large)
Core Techniques and Technologies for Advancing Big Data Science & Engineering (BIGDATA)
Deadline: June 13, 2013
Research and Evaluation on Education in Science and Engineering (REESE)
ACM SIGDA CADathlon 2012
Sunday, November 4
The CADathlon is a challenging, all-day, programming competition
focusing on practical problems at the forefront of Computer-Aided
Design, and Electronic Design Automation in particular. The contest
emphasizes the knowledge of algorithmic techniques for CAD
applications, problem-solving and programming skills, as well as
In its eleventh year as the "Olympic games of EDA," the contest brings
together the best and the brightest of the next generation of CAD
professionals. It gives academia and the industry a unique perspective
on challenging problems and rising stars, and it also helps attract
top graduate students to the EDA field.
The contest is open to two-person teams of graduate students
specializing in CAD and currently full-time enrolled in a
Ph.D. granting institution in any country. Students are selected
based on their academic backgrounds and their relevant EDA programming
experiences. Travel grant s are provided to qualifying students.The
CADathlon competition consists of six problems in the following areas:
(1) Circuit analysis
(2) Physical design
(3) Logic and behavioral synthesis
(4) System design and analysis
(5) Functional verification
More specific information about the problems and relevant research
papers will be released on the Internet one week prior to the
competition. The writers and judges that construct and review the
problems are experts in EDA from both academia and industry. At the
contest, students will be given the problem statements and example
test data, but they will not have the judges' test data. Solutions
will be judged on correctness and efficiency. Where appropriate,
partial credit might be given. The team that earns the highest score
is declared the winner. In addition to handsome trophies, the first
place team's prize is a $2,000 cash award. The second place team's
prize is a $1,000 cash award.
Contest winners will be announced at the ICCAD Opening Session on
Monday morning and celebrated at the ACM/SIGDA Dinner and Member
Meeting on Monday evening.
The CADathlon competition is sponsored by ACM/SIGDA and several
Computer and EDA companies. For detailed contest information and
sample problems from last year's competition, please visit the ACM/
SIGDA website at
October 10 Participation request for submission due
October 15 Notification of acceptance
Chair, Jarrod Roy, email@example.com
Vice Chair, Asst. Prof. Sudeep Pasricha, firstname.lastname@example.org
Vice Chair, Assoc. Prof. Srinivas Katkoori, email@example.com
Vice Chair, Sudarshan Banerjee, firstname.lastname@example.org
Vice Chair, Luis Angel D. Bathen, email@example.com
E M B E D D E D S Y S T E M S W E E K
Tampere, Finland, October 7-12, 2012
Embedded Systems Week is an exciting event which brings together conferences,
tutorials, and workshops centered on various aspects of embedded systems
research and development. Leading conferences in the area will take place
at the same time and location, allowing attendees to benefit from a wide
range of topics covered by these conferences and their associated tutorials
One registration, three conferences
Registered attendees will be allowed to attend sessions in the other
conferences and tutorials for free: CASES 2012, CODES+ISS 2012, EMSOFT
2012. Please note that workshops may require separate registration.
- International Conference on Compilers, Architecture, and Synthesis for
Embedded Systems, chaired by Vincent Mooney and Rodric Rabbah
- International Conference on Hardware - Software Codesign and System
Synthesis, chaired by Franco Fummi and Naehyuck Chang
- International Conference on Embedded Software, chaired by Florence Maraninchi
and John Regehr
Industrial sessions and panels
•Trends in Automotive Embedded Systems
•Internet-of-Energy - Combining Embedded Computing and Communication for
the Smart Grid
•Research issues in smart phones, notepads and related services
•"Low power high performance computing - How could this trend help embedded
•Monday: Wireless Innovations for Smartphones. Speaker: Dr. Hannu Kauppinen,
Vice President, Head of Nokia Research Center
•Tuesday: Computing without Processors. Speaker: Prof. Satnam Singh,
Technical Infrastructure division, Google, USA
•Wednesday: A Standards-Based, Fully-Open Software Platform for Smart
Embedded Systems. Speaker: Dr. Jong-Deok Choi, Executive Vice President,
Samsung Electronics, Korea
•Analytical Approaches for Performance Evaluation of Networks-on-Chip
Organizer: Axel Jantsch; Speakers: Abbas Eslami Kiasari, Alan Burns, Axel
Jantsch, Marco Bekooij, Zhonghai Lu
•Embedded Reconfigurable Architectures
Organizer: Stephan Wong; Speakers: Stephan Wong, Luigi Carro, Roberto Giorgi,
Stamatis Kavvadias, Stefanos Kaxiras, Georgios Keramidas, Francesco Papariello,
•Coarse-Grained Reconfigurable Architectures - Compilation and Exploration
Organizer: Tom Vander Aa; Speakers: Tom Vander Aa, Panagiotis Theocharis
•Soft Errors: The Hardware-Software Interface
Organizer: Kyoungwoo Lee; Speakers: Kyoungwoo Lee, Reiley Jeyapaul, Aviral
•Runtime Verification of Real-time Embedded Systems
Organizer: Borzoo Bonakdarpour; Speakers: Borzoo Bonakdarpour, Sebastian
•Mixed critical system design and analysis
Organizer: Rolf Ernst;Speakers: Rolf Ernst, Alan Burns, Jimmy Le Rhun,
•CASA 2012: 8th Workshop on Compiler Assisted System-on-chip Assembly ;
Organizer: Aviral Shrivastava
•ESTIMedia 2012: 10th IEEE Symposium on Embedded Systems for Real-Time
Multimedia; Organizers: Jian-Jia Chen , and Maurizio Palesi
•RSP 2012: IEEE International Symposium on Rapid System Prototyping;
Organizers: Fabiano Hessel, Jérôme Hugues and Frédéric Rousseau.
•WSS 2012: Workshop on Software Synthesis; Organizers: Peter Marwedel and
•WESE 2012: Workshop on Embedded and Cyber-Physical Systems Education;
Organizers: Peter Marwedel, Jeff Jackson, and Kenneth Ricks.
•EON 2012: Workshop on Optimization of Computing at the Edge of Network;
Organizers: Shahrokh Daijavid, Sumedh Sathaye and Seraphin Calo
•WESS 2012: Workshop on Embedded Systems Security; Organizers: Dimitrios
•MeCoES 2012: Workshop Metamodeling and Code Generation for Embedded Systems;
Organizers: Wolfgang Mueller and Wolfgang Ecker
•MeAOW 2012: Memory Architecture and Organization Workshop; Organizers:
Jason Xue and Nikil Dutt
SoC 2012: International Symposium on System-on-Chip 2012, October 11-12, 2012.
Registration is now open at www.esweek.org
Contacts: ESWeek General Chairs: - Ahmed Jerraya, CEA, France; Luca Carloni,
Columbia University, USA
ESWeek Local Arrangement Chair: - Jari Nurmi, Tampere University of Technology,
ACM International Symposium on Physical Design 2013
With a tribute to Professor Yoji Kajitani
* IMPORTANT DATES
Submission deadline: October 1, 2012
Acceptance notification: November 14, 2012
Camera-ready paper due: January 16, 2013
Symposium date: March 24 - 27, 2013
Location: To be announced shortly.
(Co-located with TAU, http://www.tauworkshop.com)
Sponsored by ACM SIGDA with Technical Co-sponsorship from IEEE CAS
The International Symposium on Physical Design provides a premier forum
to exchange ideas and promote research on critical areas related to the
physical design of VLSI systems. All aspects of physical design,
including its interactions with architecture, behavioral- and logic-level
synthesis, and back-end performance analysis and verification are within
the scope of the symposium. Target domains include semi-custom and
full-custom IC's, regular fabrics, FPGA's, and
systems-on-chip/systems-in-package. Following its twenty-one predecessors,
the 2013 symposium will highlight key new directions and leading-edge
theoretical and experimental contributions to the field. The ACM Press
will publish accepted papers in the Symposium proceedings. Topics of
interest include but are not limited to:
- Floorplanning and interconnect planning
- Interactions with behavior-level synthesis flows
- Partitioning, placement and routing
- Interactions with logic-level (re-)synthesis flows
- Physical design for manufacturability and yield
- Analysis and management of power dissipation
- Synthesis optimizations within physical design
- Management of design data and constraints
- Estimation and modeling
- New physical design methodologies
- Timing and crosstalk issues in physical design
- New paradigms in physical design
- Special structures for clocking and power networks
- Circuit performance measurements in a PD context
- Physical design for emerging process technologies
- Multithreaded/distributed algorithms in physical design
- Makeover of traditional PD problem formulation for the new technology nodes
and new applications
- Critiques and in-depth analysis of previously published PD algorithms with
new experimental results for better comparison
Continuing the tradition of spirited competition for the previous eight ISPD
contests, a contest will be held in ISPD 2013. Details will be announced on
our website later.
* SUBMISSION OF PAPERS
All papers must be submitted electronically. Details will be posted on the
website http://www.ispd.cc . Potential authors will be required to submit
full-length, original, unpublished papers (a maximum of 8 pages in ACM
conference format) along with an abstract of at most 200 words and contact
author information (name, street/mailing address, telephone/fax, e-mail).
Previously published or papers concurrently submitted for publication to other
conferences/journals will not be considered. If one or more related papers
have been previously published elsewhere or have been concurrently submitted
elsewhere for publication, the authors should clearly state the differences
between these papers and the current submission. All submitted papers will be
under blind reviews, and thus they must not include name(s) or affiliation(s)
of the author(s) anywhere in the manuscripts. Failure to comply with these
requirements will result in automatic rejection.
ISPD will recognize excellent contributions through a Best Paper Award.
* SYMPOSIUM ORGANIZATION
General Chair: Cheng-Kok Koh (Purdue Univ.) [firstname.lastname@example.org]
Steering Committee Chair: Jiang Hu (Texas A&M Univ.) [email@example.com]
Technical Program Chair: Cliff Sze (IBM) [firstname.lastname@example.org]
Publications Chair: Azadeh Davoodi (Univ. Wisconsin) [email@example.com]
Publicity Chair/Webmaster: Evangeline F. Y. Young (Chinese Univ. of Hong Kong)
Contest Chair: Mustafa Ozdal (Intel) [firstname.lastname@example.org]
Paris, France, May 2-4 2013
Sponsored by ACM SIGDA, with Technical Support of IEEE CEDA
The 23rd edition of GLSVLSI will be held in Paris, France and collocated with
the ACM European Computing Research Congress (ECRC), http://ecrc.acm.org.
Original, unpublished papers describing research in the general area of
VLSI are solicited. Both theoretical and experimental research results are
welcome. Proceedings will be published by the ACM and will be available through
the ACM Digital Library. For more information, visit http://www.glsvlsi.org/.
> VLSI Design: design of ASICs, microprocessors/micro-architectures, embedded
processors, analog/digital/mixed-signal systems, NoC, interconnects, memories,
> VLSI Circuits: analog/digital/mixed-signal circuits, RF and communication
circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits.
> Computer-Aided Design (CAD): hardware/software co-design, logic and
behavioral synthesis, logic mapping, simulation and formal verification,
layout (partitioning, placement, routing, floorplanning, compaction),
algorithms and complexity analysis
> Low Power and Power Aware Design: circuits, micro-architectural techniques,
thermal estimation and optimization, power estimation methodologies, and
> Testing, Reliability, Fault-Tolerance: digital/analog/mixed-signal testing,
design for testability and reliability, online testing techniques, static
and dynamic defect- and fault-recoverability, and variation-aware design
> Emerging Technologies: nano technology, molecular electronics, quantum
devices, biologically-inspired computing, CNT, SET, RTD, QCA, VLSI aspects
of sensor and sensor networks, and CAD tools for emerging technology devices
> Post-CMOS VLSI: evolutionary computing, optical computing, quantum computing,
reversible logic, spin-based computing, biological computation, nanotechnology,
molecular electronics, quantum devices, biologically-inspired computing.
Emphasis should be on the analysis, novel circuits and architectures,
modeling, CAD tools, and design methodologies.
Paper submission deadline: December 15, 2012
Acceptance Notification: February 15, 2013
Camera-Ready Paper Due: March 1, 2013
Paper Submission: Authors are invited to submit full-length (6 pages maximum),
original, unpublished papers along with an abstract of at most 200 words.
To enable blind review, the author list should be omitted from the main
document. Previously published papers or papers currently under review for
other conferences/journals should not be submitted and will not be considered.
Electronic submission in PDF format to the http://www.glsvlsi.org website
is required. Author and contact information (name, street/mailing address,
telephone, fax, e-mail) must be entered during the submission process.
Paper Format: Submissions should be in camera-ready two-column format,
following the ACM proceedings specifications located at:
and the classification system detailed at: http://www.acm.org/class/1998
Paper Publication and Presenter Registration: Papers will be accepted for
regular or poster presentation at the symposium. Every accepted paper
MUST have at least one author registered to the symposium by the time the
camera-ready paper is submitted; the author is also expected to attend the
symposium and present the paper.
Jose L. Ayala - Complutense Univ. of Madrid, Spain
Alex K. Jones - University of Pittsburgh, USA
Patrick Madden - Binghamton University, USA
Ayse Coskun - Boston University, USA
Theocharis Theocharides - University of Cyprus, Cyprus
David Atienza - EPFL, Switzerland
Iris Bahar - Brown University, USA
Sanjukta Bhanja - University of South Florida, USA
Erik Brunvand - University of Utah, USA
Joseph Cavallaro - Rice University, USA
Fabrizio Lombardi - Northeastern University, USA
Enrico Macii - Politecnico di Torino, Italy
Ken Stevens - University of Utah, USA
Yuan Xie - Penn State University, USA
Tong Zhang - Rensselaer, USA
April 21-24, 2013
Tempe, Arizona, USA
The International Symposium on Networks-on-Chip (NOCS) is the premier event
dedicated to interdisciplinary research on on-chip and chip-scale communication
technology, architecture, design methods, applications and systems. NOCS brings
together scientists and engineers working on NoC innovations and applications
from inter-related research communities, including computer architecture,
networking, circuits and systems, embedded systems, and design automation.
Topics of interest include, but are not limited to:
NoC architecture and implementation
- Network architecture (topology, routing, arbitration)
- NoC Quality of Service
- Timing, synchronous/asynchronous communication
- NoC reliability issues
- Network interface issues
- NoC design methodologies and tools
- Signaling & circuit design for NoC links
- Physical design of interconnect & NoC
NoC analysis and verification
- Power, energy & thermal issues (at the NoC, un-core and/or system-level)
- Benchmarking & experience with real NoC-based hardware
- Modeling, simulation, and synthesis of NoCs
- Verification, debug & test of NoCs
- Metrics and benchmarks for NoCs
- Mapping of applications onto NoCs
- NoC case studies, application-specific NoC design
- NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
- NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
- Network design for 2.5D & 3D stacked logic and memory
NoC at the un-core and system-level
- Design of memory subsystem (un-core) including memory controllers, caches,
cache coherence protocols & NoCs
- NoC support for memory and cache access
- OS support for NoCs
- Programming models including shared memory, message passing and novel
- Multi/many-core workload characterization & evaluation
- Optical, RF, & emerging technologies for on-chip/inpackage interconnects
- Issues related to large-scale systems (datacenters, supercomputers) with
NoC-based systems as building blocks
Electronic paper submission requires a full paper, up to 8 double-column IEEE
format pages, including figures and references. The program committee in a
double-blind review process will evaluate papers based on scientific merit,
innovation, relevance, and presentation. Submitted papers must describe original
work that has not been published before or is under review by another conference
at the same time. Each submission will be checked for any significant similarity
to previously published works or for simultaneous submission to other archival
venues, and such papers will be rejected. Furthermore, NOCS will notify the
technical chair of the venue where the duplicate was submitted. Please see the
paper submission instructions for details.
Proposals for tutorials, special sessions, and panels are also invited. Please
see the detailed submission instructions for paper, tutorial, special sessions,
and panel proposals at the submission page. A special section related to the
theme of the conference will be organized in one of the IEEE journals.
Abstract registration deadline
Nov 19, 2012
Full paper submission deadline
Nov 26, 2012
Proposals for tutorials, special sessions and panels Jan 11, 2013
Notification of acceptance
Feb 1, 2013
Final version due
Mar 1, 2013
Karam S. Chatha, Arizona State University, USA
Chita R. Das, Penn State University, USA
Sudeep Pasricha, Colorado State, USA
Mohammed Al Faruque, Siemens, USA
Carole Jean Wu, Arizona State University, USA
John Bainbridge, Sonics Inc., USA
Natalie Enright Jerger, University of Toronto, CA
Paul Gratz, Texas A&M, USA
Zhonghai Lu, KTH, Sweden
Umit Ogras, Intel, USA
A special issue of Journal of Electrical and Computer Engineering on ESL Design
Methodology has just been published. It is open access, and all the
be accessed at:
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