1 January 2010 :: ACM/SIGDA E-NEWSLETTER :: Vol. 41, No. 1
1 January 2010, Vol. 41, No. 1
Online archive: http://www.sigda.org/newsletter
Dear ACM/SIGDA members,
Happy New Year!
In this issue, we have reprinted the article "What Is Physical
Synthesis?" contributed by Zhuo Li and Charles Alpert of IBM. If you
would like to contribute to the "What is..." column in the
E-Newsletter, please feel free to contact us.
The SIGDA would like to thank Qing Wu, Qinru Qiu, and Deming Chen for
their contributions to the SIGDA E-Newsletter over the last few
years. They are "retiring" from the E-Newsletter and being replaced by
Matthew Guthaus, Sudeep Pasricha, and Mehmet Yildiz, respectively.
Qing Wu, E-Newsletter Editor;
Matthew Guthaus, E-Newsletter Editor;
Marc Riedel, E-Newsletter Associate Editor;
Qinru Qiu, E-Newsletter Associate Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Soheil Ghiasi, E-Newsletter Associate Editor;
Umit Y Ogras, E-Newsletter Associate Editor;
Sudeep Pasricha, E-Newsletter Associate Editor;
Mehmet Yildiz, E-Newsletter Associate Editor;
"Qualcomm Buys Atheros"
Qualcomm Inc confirmed plans to acquire wireless and wired communications
specialist Atheros Communications Inc for $45 per share in cash, representing
a total value of $3.1 billion.
"Intel, AMD Get Graphic With CPUs"
As expected, rival microprocessor firms Intel Corp. and Advanced Micro Devices
Inc. (AMD) used the occasion of the 2011 Consumer Electronics Show in Las
Vegas to officially launch new multicore chips that combine microprocessing
and graphics processing capabilities on a single die.
"Micron Offers SSDs Up to 512-Gbyte"
Memory chipmaker Micron Technology Inc. has announced several solid-state
drives based on the company's 25-nm NAND flash memory technology and ranging
in capacity from 64-Gbyte to 512-Gbyte.
"1,000 Processors on a Xilinx FPGA"
Scientists at the University of Glasgow have created a 1,000-core computer
processor based on a Xilinx field programmable gate array. The researchers
created 1,000 mini-circuits within the FPGA chip with each core working on its
"Samsung Sampling 400-GB MLC SSDs"
Samsung Electronics Co Ltd is sampling 100-, 200-, and 400-GB MLC
(multi-level-cell) SSDs (solid state drives) for use as primary storage in
enterprise storage systems. The SSDs use 30-nm-class MLC NAND flash chips with
a Toggle DDR interface and a controller that uses a 3 Gb/s SATA interface.
"TSMC Solar Partner Builds U.S. Plant"
Stion Inc., a manufacturer of thin-film solar panels, will build a new
production facility in Mississippi. This is part of an incentive agreement
that includes a $75 million loan and other tax and training incentives.
"In Split Vote, FCC Approves Net Neutrality Rules"
After a 14-month debate, the U.S. Federal Communications Commission split
along party lines to narrowly pass what its chairman called the first
enforceable rules for the Internet. The so-called Net neutrality ruling faced
criticism from both parties as going too far and not far enough in protecting
the openness of the Web.
"13 Fabless IC Suppliers Expected to Top $1B in 2010 Sales"
A forecast of the 2010 billion-dollar fabless IC suppliers, excerpted from a
ranking of the top 50 fabless IC suppliers in IC Insights' coming 2011 edition
of The McClean Report, shows 13 fabless companies expected to register more
than $1 billion in sales in 2010 up from 10 such companies in 2009 and eight
companies in 2008. IC Insights reported that the 13 suppliers are forecast to
have a combined $41.4 billion in sales and represent about 70% of the $59.6
billion worth of total fabless company IC sales expected in 2010.
"Electronics Industry Braces for Rare-Earth-Materials Shortages"
China has started to severely restrict the exports of rare-earth materials,
which often find use in â€œgreenâ€-technology designs, including hybrid vehicles
and energy-efficient lighting, as well as in the medical, defense, and
consumer markets. The country delivers nearly 100% of the worldâ€™s rare-earth
materials: 17 metals that are somewhat hard to refine and that tend to occur
in the same ore deposits. The cutbacks have resulted in shock waves through
the electronics industry and could force design changes in the near future.
Zhuo Li and Charles J. Alpert, IBM
VLSI technology scaling has caused interconnect delay to increasingly dominate
the overall chip performance. A design that satisfies timing constraints after
logic synthesis will not necessarily meet timing constraints after place-and-
route due to wire delays. Physical synthesis has been emerged as a necessary
weapon for design closure. It is a core component of modern VLSI design
methodologies for ASIC, game chips and high performance microprocessors.
Physical synthesis begins with a mapped netlist generated by logic synthesis.
The netlist describes the logical connections among the physical components
(logic gates, macro/IP blocks, I/O pins, etc.). Physical synthesis generates a
new optimized netlist and a corresponding layout. Its objectives are to
satisfy a combination of timing, area, power, and routability. One can think
of physical synthesis as a wrapper around traditional place and route, whereby
synthesis-based optimization are interwoven with placement and routing.
For example, physical synthesis commonly starts by performing placement,
followed by timing analysis . Not surprisingly, timing analysis will
generally highlight severe timing and electrical problems due to long wires.
Timing optimization like buffering, gate sizing, Vt swapping, cloning, fan-in
tree optimization, logic decomposition, connection reordering, etc. can then be
applied to drive towards timing closure . In addition, scan chain generation
and clock insertion can also be run during this process.
Physical synthesis naturally proceeds from a low-level of accuracy to a high
level. Initial timing closure might be done with Steiner estimates. Then
global routing can be invoked and optimization will use global wires and
perhaps use first order coupling analysis. Then detailed routing can be run and
timing closure can proceed with accurately extracted detailed wires. As the
level of accuracies increase, optimizations become more expensive to perform so
most optimizations should occur with the coarsest levels of accuracy.
How to organize a â€œbestâ€ flow for each subsequent phase of accuracy (Steiner,
global and detailed wires) to come up is still an ad hoc approach (or an art).
The academic literature has not been able to address these problems because it
lacks all the components and infrastructure to tune such a flow. For efficiency
reasons, physical synthesis may employ heuristic approaches, starting with
large changes and inexpensive analyses early in the design flow and then
transitioning to more expensive analyses and restricting consideration to small
changes as the design converges.
During physical synthesis, each optimization or transform generally has a
special purpose, and tries to optimize one objective without hurting the others
ones. A buffer insertion transform generally tries to reduce delay and
electrical violations while using minimum area and power cost. A gate sizing
transform can be used to fix critical paths, but it also can be used to recover
area and power. One can also develop complex transforms that perform more than
one optimization at a time, such as simultaneous gate sizing and Vt swapping
, buffer insertion and layer assignment . Fast incremental timing
analysis is a critical ingredient for understanding whether or not transforms
should be accepted. Similarly, intelligent placement services that
incrementally place and legalize changes to the netlist are necessary.
While physical synthesis is a fairly mature technology, it is far from a solved
problem in industry. Modern technologies (45 nm and beyond) provide a host of
problems that can easily break physical synthesis. For example, complex design
rules, IP/macros from hierarchical designs, the inability of buffers to drive
long distances, more and varying metal layers make routability an increasingly
vexing problem . Physical synthesis has to be much more cognizant of not
just timing closure, but of creating routable designs. Thus, new optimizations
that try to spread cells, refactor logic, and find alternative buffering
strategies are key to achieving routing closure.
Logic synthesis, placement, routing, and clocking are no longer truly separate
tasks. The choices made by one component severely affect the others.
Consequently powerful incremental techniques that can surgically attack timing
and congestion problems are growing in importance. It is impossible for
optimizing one objective not to sometimes mess up another, which makes recovery
very important. For example, clock insertion could destroy routability, and one
needs techniques to incrementally clean up damage caused by this disruption.
 Charles J. Alpert, Shrirang Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T.
Quay, Haoxing Ren, C. N. Sze, Paul G. Villarrubia, and Mehmet Yildiz,
"Techniques for Fast Physical Synthesis," Proceedings of the IEEE, Vol. 95, No.
3, March 2007, pp. 573-599.
 Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar, "Handbook of
Algorihms for Physical Design Automation,", 2008, Auerbach Publications,
Boston, MA, UA.
 Yifang Liu and Jiang Hu, â€œA New Algorithm for Simultaneous Gate Sizing and
Threshold Voltage Assignment,â€ IEEE Trans. On CAD of Integrated Circuits and
Systems, Vol. 29, No. 2, Feb 2010, pp. 223-234.
 Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, and
Paul G. Villarrubia, â€œFast interconnect synthesis with layer assignment,â€ In
Proceedings of the 2008 international symposium on Physical design (ISPD '08),
 Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy,
and Gustavo Tellez, â€œWhat makes a design difficult to route,â€ in Proceedings of
the 19th international symposium on Physical design (ISPD '10). pp. 7-12.
MSE'11 - Microelectronics Systems Education
San Diego, CA (co-located with DAC)
June 5 - 6, 2011
Deadline: Jan 21, 2011
ACM JETC - Journal on Emerging Technologies in Computing Systems
Special Issue on Asynchrony in System Design
Deadline: March 15, 2011
PACT'11 - Int'l Conference on Parallel Architectures and Compilation
Galveston Island, TX
Oct 8-12, 2011
Deadline: Mar 25, 2011 (Abstract submission deadline: Mar 18, 2011)
ISLPED'11 â€“ Int'l Symposium on Low-Power Electronics and Design
Aug 1-3, 2011
Deadline: (Date unannounced yet)
VLSI-SoC'11 â€“ Int'l Conference on Very Large Scale Integration and System on
Hong Kong, China
Oct 3-5, 2011
Deadline: Apr 4, 2011
ASQED'11 - Asia Symposium on Quality Electronic Design
Kuala Lumpur, Malaysia
Jul 19-20, 2011
Deadline: April 4, 2011
24th ACM SIGDA University Booth
San Diego, CA (co-located with DAC)
June 5 - 10, 2011
Deadline: May 2, 2011 (tentative)
VLSI'11 - Int'l Conference on VLSI Design
Jan 2-7, 2011
HiPEAC'11: Int'l Conference on High Performance Embedded Architectures &
Jan 24-26, 2011
ASP-DAC'11 - Asia and South Pacific Design Automation Conference
Jan 25-28, 2011
ISSCC'11 - Int'l Solid-State Circuits Conference
San Francisco, CA
Feb 20-24, 2011
ISQED'11 - Int'l Symposium on Quality Electronic Design
Santa Clara, CA
Mar 14-16, 2011
DATE'11 - Design Automation and Test in Europe (sponsored by SIGDA)
Mar 14-18, 2011
ISPD'11 â€“ Int'l Symposium on Physical Design
Santa Barbara, CA
Mar 27-30, 2011
TAU'11 - Int'l Workshop on Timing Issues in the Specification and
Synthesis of Digital Systems (co-located with ISPDâ€™11)
Santa Barbara, CA
Mar 31 â€“ Apr 1, 2011
SPL'11 - Southern Conference on Programmable Logic
Apr 13-15, 2011
ASYNC'11 - Int'l Symposium on Asynchronous Circuits and Systems
Apr 27-29, 2011
ISCAS'11 - Int'l Symposium on Circuits and Systems
Rio De Janerio, Brazil
May 15-18, 2011
ISCA'11 â€“ Int'l Symposium Computer Architecture
San Jose, CA
Jun 4-8, 2011
DAC'11 â€“ Design Automation Conference
San Diego, CA
Jun 5-10, 2011
Seapower 21 or Seatrial Concept Experimentation Software Technologies
Deadline: March 25, 2011
Deadline: March 25, 2011
Biomimetic Signal Processing and Control - BAA-RWK-10-0001
Deadline: Continuous through April 30, 2011
Hardware-in-the-Loop Simulation Technologies - BAA-RWK-10-0001
Deadline: Continuous through April 30, 2011
Army Research Office (ARO) Broad Agency Announcement for Basic and
Applied Scientific Research (W911NF-07-R-0003)
Deadline: Continuous through September 30, 2011
ARL/ARO Core Broad Agency Announcement for Basic and Applied
Scientific Research for Fiscal Years 2007 through 2011
Deadline: Continuous through September 30, 2011
Sensing, Surveillance, Navigation - AFOSR-BAA-2010-01
Robust Computational Intelligence - AFOSR-BAA-2010-01
Advanced Scene Generation - BAA-RWK-08-0001
Multi-Agent Systems - BAA-RWK-08-0002
Systems and Software (AFOSR-BAA-2008-1)
ERDC BAA - High Performance Computing (HPC) and Networking (ITL-3)
ERDC BAA - Computational Science and Engineering (ITL-1)
ERDC BAA - Software Engineering and Informatics (ITL-2)
Artificial Intelligence Technologies (NRL-WIDE BAA-N00173-01)
Advanced Distributed Sensor Technologies - BAA 57-09-06
Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01)
High Performance Computing on Massively Parallel Architectures
ASEE-NRL Postdoctoral Fellowship Program
Engineering Design and Innovation (EDI)
Deadline: September 1, 2010 - October 1, 2010
January 15, 2011 - February 15, 2011
Emerging Frontiers in Research and Innovation 2011 (EFRI-2011) - NSF 10-596
Deadline: October 04, 2010
November 08, 2010
April 01, 2011
Advancing Digitization of Biological Collections (ADBC) - NSF 10-603
Deadline: December 10, 2010
NSF Fellowships for Transformative Computational Science Using
CyberInfrastructure (CI TraCS) - NSF 10-553
Deadline: January 13, 2011
January 13, 2012
Nanoelectronics for 2020 and Beyond (NEB) - NSF 10-614
Deadline: January 19, 2011
Cyber-Enabled Discovery and Innovation (CDI) - NSF 11-502
Deadline: January 19, 2011 (type I proposal)
January 20, 2011 (type II proposal)
Broadening Participation Research Initiation Grants in Engineering
(BRIGE) - NSF 10-609
Deadline: January 24, 2011
Strategic Technologies for CyberInfrastructure (STCI) - PD 10-7684
Deadline: February 03, 2011
August 04, 2011
Energy, Power, and Adaptive Systems (EPAS) - PD 10-1518
Deadline: February 07, 2011 (full proposal)
April 01, 2011 (application)
Cyber-Physical Systems (CPS) - NSF 10-515
Deadline: March 10, 2011
January 17, 2012
High Performance Computing System Acquisition: Enhancing the Petascale
Computing Environment for Science and Engineering - NSF 11-511
Deadline: May 7, 2011
Office of Naval Research (ONR) Sabbatical Leave Program
Call for Demonstration
24th ACM SIGDA University Booth
at the 48th Design Automation Conference
San Diego Convention Center
San Diego, California
June 5-10, 2011
This year marks the 24th University Booth at the Design Automation
Conference. The booth is an opportunity for university researchers to
display their results and to interact with participants at
DAC. Presenters and attendees at DAC are especially encouraged to
participate, but participation is open to all members of the
university community. The demonstrations include new EDA tools, EDA
tool applications, design projects, and instructional materials.
* The university booth will be located near the technical sessions for
* The university booth will be open two full days. June 7th - 8th:
10am - 5pm.
* The submission is in a 5-min video presentation format. Live
demonstrations performed at the booth by university researchers
simultaneous with the video presentations. Submitted video are
considered for publications in the ACM Digital Library. Also, it
will be featured on the DAC and SIGDA web pages, and be available
* Participants at the University Booth are also provided with modest
travel grant reimbursements, provided that posters are hung for the
entire duration of the conference and that demonstrations are
completed during the time slots that they are
scheduled. Participants who receive funding for the conference via
alternative sources such as the Ph.D. forum and Student Design
Contest are not eligible for travel grants through the University
Tentative Deadline for registration is May 2, 2011
To apply for participation, please visit the University Booth website
( http://www.dac.com/university+booth.aspx ) Video demonstrations should
include a brief title sequence identifying the name of the research
group and university, the team members, and stating "SIGDA University
Booth at DAC 2011". Otherwise, there is complete freedom in how a
group wishes to present their work. A sample video is available on
Youtube ( http://www.youtube.com/watch?v=OJfefVCIWhU )
Call for Papers
ISLPED 2011 (http://www.islped.org)
IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN
Location: Fukuoka, Japan
Date: August 1-3, 2011
Technical paper submission deadline: March 7, 2011
Notification of paper acceptance: April 29, 2011
Camera-ready version due: May 25, 2011
The International Symposium on Low Power Electronics and Design (ISLPED)
is the premier forum for presentation of recent advances in all aspects
of low power design and technologies, ranging from process and circuit
technologies, simulation and synthesis tools, to system level design and
optimization. Specific topics include, but are not limited to, the
following two main areas, each with three sub-areas:
1. Architecture, Circuits, and Technology
1.1. Technologies and Digital Circuits
1.2. Logic and Microarchitecture Design
1.3. Analog, MEMS, Mixed Signal and Imaging Electronics
2. Design Tools, System and Software Design
2.1. CAD & Design Tools
2.2. System Design and Methodologies
2.3. Software Design and Optimization
****TECHNICAL PAPER SUBMISSIONS****
Submissions should be full-length papers of up to 6 pages (double-column
format, font size 9pt to 10pt), including all illustrations, tables,
references and an abstract of no more than 100 words. Papers exceeding
the six-page limit will not be reviewed. Electronic submission in pdf
format only via the web is required. More information on electronic
submission to ISLPEDâ€™11 can be found at http://www.islped.org.
-Naehyuck Chang, Seoul National Univ.
-Hiroshi Nakamura, The Univ. of Tokyo
-Kenichi Osada, Hitachi
-Massimo Poncino, Politecnico Di Torino
Vice General Chair
-Koji Inoue, Kyushu Univ.
Local Arrangement Chair
-Hiroaki Honda, ISIT
-Tohru Ishihara, Kyushu Univ.
-Yuan Xie, Penn State Univ.
Special Session Co-Chairs
-Toshinori Sato, Fukuoka Univ.
-Youngsoo Shin, KAIST
-Hiroyuki Tomiyama, Ritsumeikan University
-Jian-Jia Chen, Karlsruhe Institute of Tech.
-Hamid Mahmoodi, San Francisco State Univ.
-Yu Wang, Tsinghua Univ.
Design Contest Co-Chairs
-Chia-Lin Yang, National Taiwan Univ.
-Yiran Chen, University of Pittsburgh
-Satoshi Goto, Waseda Univ.
-Masaaki Kondo, The Univ. of Electro-Communications
-Masanori Hashimoto, Osaka Univ.
-Taewhan Kim, Seoul National Univ.
-Pai Chou, UC Irvine and National Tsing Hua Univ.
-Kunio Uchiyama, Hitachi
-Sungjoo Yoo, POSTEC
-Kiyoung Choi (Seoul National University)
-Takayasu Sakurai (The University of Tokyo)
-Hiroto Yasuura (Kyushu University)
CRA-W/CDC Workshop on Multicore Systems â€“ Architectures, Runtime
Systems and Software Development
Sunday, March 6, 2011
Co-located with ASPLOS 2011 in Newport Beach, CA.
The workshop is intended for women and underrepresented minorities
working in or interested in working in the multicore systems space.
Attendees will include students, junior (pre-tenure) university
faculty, and junior industry researchers. Travel and subsistence
funding will be awarded to selected applicants. Application details
are provided below. The workshop is part of a series of
Discipline-specific Mentoring Workshops organized by Computing
Research Association's Committee on the Status of Women in
Computingand the Coalition to Diversify Computing (CDC). Additional
support for this workshop comes from Penn State University, The
University of Virginia, The University of Pittsburgh, ACM SIGARCH
(pending), ACM SIGPLAN (pending), and ACM SIGOPs (pending).
The one-day workshop will be organized into four sessions followed by
* Multicore architecture systems research challenges
* Multicore software systems research challenges
* Getting started in multicore research â€“ platforms, benchmarks,
simulation tools, software tools
* Panel session: Career opportunities and research directions in
Funding is available to help cover travel costs and subsistence
(hotel, food) during the workshop for attendees. The deadline for
applications to attend the Workshop is January 15, 2011. Selected
participants will be notified by February 1, 2011. Applications
should be sent via email to Mary Jane Irwin ( firstname.lastname@example.org ). An
application requires the following information:
Link to your webpage:
Current University/College (for students/faculty) or Company (for industry researchers):
Current degree program (e.g., bachelors, MS, PhD) and GPA (for students):
Current year in program (for students), or time-in-rank (for faculty/researchers):
Research area of interest (if any):
Contact information for one reference in case we need additional information (name, title, e-mail address, phone number):
Statement: 1 page max statement on "How can you contribute to and benefit from this workshop?" Please make sure you address both parts of the question.
Mary Lou Soffa, University of Virginia
Mary Jane Irwin, Penn State University
Workshop on Green Multimedia Communication
This workshop will be held with IEEE International Conference on
Multimedia and Expo, Barcelona, Spain, July 2011.
Goals: To establish a forum for sharing the latest progress in
developing energy-conservation techniques for multimedia
Significant amounts of energy may be consumed for the production,
storage, transmission, reception, and consumption of multimedia
content. Many techniques have been proposed to reduce the energy
consumption of multimedia communication, from efficient network
protocols to better compression algorithms, from adjusting displayâ€™s
brightness to reducing frame rates. The workshop provides a forum in
which researchers can discuss ideas about the recent progress in green
Topics of interest related to this workshop include but are not limited to:
* principles for designing technologies for energy-efficient
* energy conservation techniques for production, storage,
transmission, reception, and consumption
* energy-efficient networking protocols or communication
algorithms for multimedia content delivery
* energy-efficient servers for multimedia streaming
* requirements to fairly and objectively evaluate energy-saving
* multimedia content as benchmarks
* metrics to evaluate multimedia quality when energy-conservation
techniques are applied
* tools (hardware, software, or both) that can quantify energy
savings for multimedia content production, storage, delivery,
* algorithms for energy management in office, computer labs to
handle efficient mechanisms to reduce power consumption in
* Intelligent ambient systems to schedule multimedia communication
based on limited resources
This workshop especially welcomes submissions of data, tools, and
programs that can be publicly available to other
researchers. Contributors are encouraged to provide live demonstration
in the workshop.
Submission: February 20, 2011
Notification to authors: April 10, 2011
Final version: April 20, 2011
Submitted papers must be no longer than eight 8.5" x 11" pages,
including figures, tables, and references; two-column format, using
10-point type on 12-point (single-spaced) leading; and a text block
6.5" wide x 9" deep. Author names and affiliations should appear on
the title page. Papers must be in PDF and submitted on-line through
the ICME web site.
Simultaneous submission of the same work to multiple venues,
submission of previously published work, or plagiarism constitutes
dishonesty or fraud. IEEE, like other scientific and technical
conferences and journals, prohibits these practices and may take
action against authors who have committed them. Author Guidelines.
Organized by the Green Multimedia Communication Interest Group of the
IEEE Multimedia Communication Committee
Special Section Call for Papers: IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems (TCAD)
PAR-CAD: Parallel CAD Algorithms and CAD for Parallel Architectures/Systems
The advent of multicore architectures and systems has created an impetus for
developing Computer-Aided Design (CAD) algorithms and design automation (DA)
tools specifically for such platforms. Indeed, most existing CAD flows and DA
tools assume a sequential underlying computing paradigm and do not exploit the
availability of parallel computing resources. Furthermore, such parallel
architectures/systems require a complete revamp of DA tools that need to
address scalable solutions for modeling, analysis, and optimization for
multicore systems. Finally, from an application perspective, emerging nano and
biological applications require CAD tools for their modeling, analysis, and
optimization. Due to their sheer complexity, such systems require fast and
scalable tools that take advantage of the available parallel resources existing
in current and future platforms.
The IEEE Transactions on Computer Aided Design of Integrated Circuits and
Systems (TCAD) welcomes original contributions that address these and other
related issues. More specifically, research papers with in-depth development
and coverage on the following topics are of particular interest:
1. Novel parallel CAD algorithms
2. Hardware-specific parallel acceleration of CAD applications
3. Design automation and architecture exploration for multi-core system design
4. Parallel runtime optimization and support for CAD
5. Parallel algorithms for emerging nano and biological CAD applications
Authors are encouraged to submit high-quality research contributions in areas
mentioned above, or other areas related to parallel CAD algorithm
implementation or CAD for parallel architectures/systems. In cases where the
submission is an extended version of one of more previously published papers
(including conference papers), please identify clearly the additional material
from the original paper(s) in your submitted manuscript. All manuscripts are
subject to standard IEEE Transactions on CAD review process. Prospective
authors should submit their manuscripts electronically on the TCAD Web site:
http://tcad.polito.it. Authors should clearly identify their papers as
submissions for the "Special Section on PAR-CAD 2010" on their manuscript and
use the prefix "PAR-CAD 2010:" before their paper title during the review
process. Instructions on how to submit a paper can be found at
Peng Li Diana Marculescu
Dept. of Electrical and Computer Dept. of Electrical and Computer
Texas A&M University Carnegie Mellon University
Submission due: January 30, 2011
Notification: July 30, 2011
Final paper due: August 10, 2011
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