===============================================================================
 SIGDA -- The Resource for EDA Professionals     http://www.sigda.org

 This newsletter is a free service for current SIGDA members
 and is added automatically with a new SIGDA membership.
 Circulation: 2,700
===============================================================================

   15 December 2007       ACM/SIGDA E-NEWSLETTER       Vol. 37, No. 24

   Online archive: http://www.sigda.org/newsletter

===============================================================================

Contents of this E-NEWSLETTER:

(1) SIGDA News
      Contributing author: Marc Riedel  
      Contributing author: Qing Wu 
      Contributing author: Lin Yuan 

(2) What Is Triple Modular Redundancy?

(3) ICCAD 2007 Best Paper Award
      Author: Jaijeet Roychowdhury 

(4) Paper Submission Deadlines
      From: Hai Zhou 

(5) Upcoming Symposia, Conferences and Workshops
      From: Hai Zhou 

(6) Upcoming Funding Opportunities
      From: Qinru Qiu 

(7) Call for Participation: ASP-DAC 2008
      From: Hai Zhou 

===============================================================================

Dear ACM/SIGDA members,

  Happy Holidays!

  In this issue, we have included a new "What Is Triple Modular Redundancy?"
column, as well as an article on "ICCAD 2007 Best Paper Award". In addition,
"SIGDA News" column contains a number of fresh headlines. We have also updated
the contents of other regular columns.

  As always, we welcome your comments and suggestions. If you would like to
participate or contribute to the content of the E-Newsletter, please feel free
to contact any of us.

Qing Wu, E-Newsletter Editor;
Matthew Guthaus, E-Newsletter Associate Editor;
Marc Riedel, E-Newsletter Associate Editor;
Qinru Qiu, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Hai Zhou, E-Newsletter Associate Editor;

===============================================================================

SIGDA News
-----------------------

"Researchers Hope to Use Synthetic DNA to Create Life-Forms"
http://www.dallasnews.com/sharedcontent/dws/news/healthscience/stories/121707dnnatsynbio.2bf46e0.html
It has been 50 years since scientists first created DNA in a test tube,
stitching ordinary chemical ingredients together to make life's most
extraordinary molecule. Until recently, however, even the most sophisticated
laboratories could make only small snippets of DNA â.. an extra gene or two to
be inserted into corn plants, for example, to help the plants ward off insects
or tolerate drought. Now researchers are poised to cross a dramatic barrier:
the creation of life-forms based on completely artificial DNA.

"Start Hacking Life: Desktop DNA Synthesizers"
http://blog.wired.com/wiredscience/2007/12/start-hacking-l.html
A couple of weeks ago, I speculated in a post called The Open Organism:
Genetic Engineering in the Open Source Era on the possibility for hackers to
build their own custom organisms like people build web apps now. Well, if that
post got you so excited that you want to run out and start building new
organisms, your new DNA "compiler" is for sale on Ebay for a mere $799. It
fits on your desk and can take genetic code that looks like this, gatcctccat,
and turn it into an actual DNA sequence. From there, it can be incorporated
into actual organisms via widely known genetic engineering techniques.

"Computer Modelling Technique Predicts Drug Side-Effects"
http://info.cancerresearchuk.org/news/archive/newsarchive/2007/december/18393303
A new computer modelling technique could be used to potentially identify the
side-effects of new drugs.  The procedure, which is detailed in PLoS
Computational Biology, screens specific drug molecules using the Protein Data
Bank - a worldwide database that contains tens of thousands of
three-dimensional protein structures.  Researchers at the University of
California, San Diego (UCSD) have now used the technique to study a class of
drugs called selective oestrogen receptor modulators (SERMs), which includes
the common breast cancer drug tamoxifen.  

"Everybody Loves Cadence; Can EDA Leader Sustain the Romance?"
http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=204803607
Michael J. Fister isn't being cocky; he truly believes the company he
shepherds as president and CEO deserved the surprising, though brief,
attention it apparently garnered from private-equity investors earlier this
year.  If companies looking for leveraged-buyout opportunities were indeed
sniffing around Cadence Design Systems Inc.--speculation that Fister, in a
recent interview, would neither confirm nor deny--it could be because they saw
a lot to like in the top-ranked supplier of electronic design auto- mation
hardware and software.

"EDA Has Good Showing in Hot 100"
http://www.edn.com/index.asp?layout=blog&blog_id=1480000148&blog_post_id=860018886
We've just posted our HOT 100 products for 2007. This year the EDA industry
produced quite a few interesting tools spanning several different design
disciplines.  In 2005 and 2006, a vast majority of the EDA startups and new
tools seemed to be in the DFM space. I think 2007 will likely be remembered as
the year in which the big EDA vendors consolidated the DFM tool space and
integrated many of these DFM tools into their RTL-to-GDSII tool flows.

"Gate Leakage, Down And Out?"
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=204700285
A high-k dielectric process for CMOS transistors promises to turn the
International Semiconductor Roadmap into a freeway by eliminating the
gate-leakage problem at advanced nodes down to 10 nanometers.  Overheating due
to excessive gate leakage is the number one hurdle to reaching advanced
semiconductor nodes below 45 nanometer. Now, a process with 1 million times
less gate leakage could enable rapid migration to advanced nodes, according to
Clemson University researchers.

"AMD Exec Discusses Barcelona Debacle"
http://www.eetimes.com/showArticle.jhtml?articleID=204801299
A senior executive at Advanced Micro Devices said Monday that launching the
first quad-core Opteron server chip to great fanfare in September was "a
stupid decision" given a glitch that has halted distribution to all but a few
customers, but insisted that it was "the right decision" at the time.  "Now if
I was to do it all over again, I have to tell you, with the data I had at the
time, I would make the same decision again. With the data I have now, clearly,
that was a stupid decision. But with the data I had that day, it was the right
decision," said Mario Rivas, head of AMD's Computing Products Group.

"Swedish Researchers Launch Printed Electronics Ventures"
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=204701248
This former paper mill town is emerging as a hot bed for printed electronics.
Along with top university researchers pushing the technology, which
essentially uses paper instead of semiconductors as an electron carrier,
there's another reason why the region has emerged: "There's a lot of paper in
Sweden," said Magnus Berggren, a printed electronics researcher and a
professor at Linkoping University here.

"IBM Hails On-Chip Optical Communications R&D"
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=204701679
IBM researchers have described a Mach-Zehnder electro-optic modulator, built
in silicon, that they claim is 100 to 1,000 times smaller in size compared to
previously demonstrated modulators of its kind. IBM goes on to claim the
development could pave the way to multiprocessing chips with optical routing
networks for the transmission of information.  The Mach-Zehnder electro-optic
modulator, described by IBM researchers in the journal Optics Express,
performs the function of converting electrical signals into pulses of light,
IBM said. However, IBM did not indicate how soon on-chip optical communication
might be deployed in commercial chips. The reduced size supports reduced cost,
energy and heat while increasing communications bandwidth between the cores
more than a hundredfold over wired chips, IBM said. The report, entitled
"Ultra-compact, low RF power, 10-Gbit/s silicon Mach-Zehnder modulator  by
William M. J. Green, Michael J. Rooks, Lidija Sekaric, and Yurii A. Vlasov of
IBM s T.J.Watson Research Center in Yorktown Heights, N.Y. is published in
Volume 15 of Optics Express.

"IBM Unveils Smallest Silicon Modulator"
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=204701734
Optical interconnections on silicon herald a future in which photons will
replace electrons to shuttle high-speed data streams between multiple
microprocessor cores.  A key component is an electro-optical modulator that
permits one core's electrical output to modulate a silicon laser beam into a
coded stream of pulses that can be routed to the input of any other core.

"A Revolution In Functional Verification"
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=204701843
Exhaustive functional coverage promises to revolutionize the design of ICs and
other digital systems. Exhaustive coverage is now a genuine possibility
because the scientific and mathematical foundation for measuring functional
space objectively has been revealed.  Mushy concepts like "features" and
"functionality" no longer serve designers.  These concepts can be useful for
thinking about the capabilities of a design, but they don't lend themselves to
objective enumeration by software in the way commercial extraction tools
discover and exhaustively enumerate timing paths.  Engineers enumerate
features, and two different teams of engineers are unlikely to produce two
identical lists of features for an identical design.

"IMEC Details High-K Planar CMOS Advances"
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=204800974
Researchers from Belgian research group IMEC and its partners in the 32-nm
CMOS program claim to have made significant advances in improving the
performance of planar CMOS using hafnium-based high-k dielectrics and
tantalum-carbide metal gates.  They outlined progress in the project at this
week's International Electron Devices Meeting in Washington, DC.

"NXP Claims Piezoresistive Silicon MEMS At 1.1 Ghz"
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=204802109
Researchers at NXP Semiconductors have described what they say is a
demonstrable, scalable piezoresistive MEMS resonator built in silicon and
operating at a record 1.1 GHz.  The team devised a novel transduction scheme
in which an electrostatic force excites the silicon resonator and the
mechanical motion is detected using the piezoresistive properties of silicon,
the group said in a presentation at the International Electron Devices Meeting
(IEDM) here.

"DRAM, Processor Price Wars Benefit Consumers, Says SIA's Scalise"
http://www.eetimes.com/news/design/showArticle.jhtml?articleID=204600568
Price attrition in DRAMs and microprocessors has continued throughout 2007 and
is good news for both the companies selling equipment and the general public
which buys consumer electronics, said George Scalise, president of the
Semiconductor Industry Association.

"Divergence of E-Paper Displays"
http://www.eetimes.com/news/design/showArticle.jhtml?articleID=204204087
We've all heard the sizzle of e-paper displays, with their promise of
wraparound advertising signs, wearable wrist monitors and e-newspapers that we
fold or roll up and stick into our pockets. While the age of these gee-whiz
products is not yet upon us, their enabling display technologies are on the
move.

"ASIC Design Starts to Fall 4% in 2007, Says Gartner"
http://www.eetimes.com/news/design/showArticle.jhtml?articleID=204600705
The number of ASIC designs taping out in 2007 looks set to be 3,275 down 4
percent from 3,408 ASIC design start tape outs in 2006, according to market
research company Gartner Inc. Of the 2007 ASIC design starts about 200 starts
made at 65-nanometer design rules or below.

"Virtually Every ASIC Ends Up an FPGA"
http://www.eetimes.com/news/design/showArticle.jhtml?articleID=204702700
Because more than 90 percent of all ASICs today are either partially or
completely prototyped in FPGAs before tape-out, the question is no longer
whether to implement an IC design as an ASIC, or as an FPGA. To meet the
demands of today's markets, most design teams must do both.


==============================================================================

What Is Triple Modular Medundancy?
---------------------------------------

http://en.wikipedia.org/wiki/Triple_modular_redundancy


==============================================================================

ICCAD 2007 Best Paper Award
-------------------------------

The paper "Approximation Algorithm for the Thermal-Aware Scheduling Problem",
by Sushu Zhang and Karam S. Chatha of Arizona State University, was selected
as the IEEE/ACM William J McCalla Best Paper at ICCAD 2007.  Following a
rigorous process involving three rounds of elimination, Zhang and Chatha's
paper was judged the best of nine candidates by an international panel of
eight distinguished experts.

Research performed by Zhang and Chatha addresses the increasing power
densities in current-day microprocessors that have raised chip-surface
temperatures to 120 degrees Celsius. High processor temperatures are
particularly problematic for devices embedded in handheld applications, which
typically feature only limited cooling facilities.  As a result, embedded
system designers are especially in need of thermal-aware design practices. The
paper addresses the timely design problem of performance maximization of a
periodic sequence of tasks on a microprocessor under peak thermal constraints.
Associated design decisions include selecting a processor voltage/frequency
state for each task, and scheduling processor sleep times to limit temperature
rise.

Zhang and Chatha first showed that the problem is NP-hard, ie, that it cannot
be solved optimally in an efficient manner. They then devised an efficient
algorithm (a polynomial time approximation scheme) that can generate designs
guaranteed to be within a designer-specified bound (eg, 1%, 5% or 10%) of the
optimal solution. For practical design problems with up to about 100 tasks,
the new technique can generate high-quality solutions within a matter of
seconds. The authors also demonstrated the inadequacy of existing power-aware
design practices for addressing thermal concerns.  The new method will be a
crucial enabler for a new generation of CAD tools that incorporate effective
automated approaches for thermal aware design of embedded systems.


==============================================================================

Paper Submission Deadlines:
----------------------------

EWME'08 - European Workshop on Microelectronics Education
Budapest, Hungary
May 28-30, 2008
Deadline: Jan 10, 2008 (extended)
http://www.eet.bme.hu/new/index.php?option=com_content&task=view&id=129&Itemid=160

RCE'08 - Reconfigurable Computing Education
Montpellier, France
Apr 10, 2008
Deadline: Dec 15, 2007
http://helios.informatik.uni-kl.de/RCeducation08/

RFID'08 - Conference on RFID
Las Vegas, NV
Apr 16-17, 2008
Deadline: Dec 19, 2007
http://www.ieee-rfid.org/

ACSD'08 - Int'l Conference on Application of Concurrency to System Design
(sponsored by SIGDA)
Xi.an, China
June 23-27, 2008
Deadline: Jan 4, 2008
http://ictt.xidian.edu.cn/acsd2008/Pages/ACSD_main.jsp

RSP'08 - Int'l Workshop on Rapid System Prototyping
Monterey, CA
Jun 2-5, 2008
Deadline: Jan 5, 2008
http://www.rsp-workshop.org/

CAV'08 - Int'l Conference on Computer Aided Verification
Princeton, PA
Jul 7-14, 2007
Deadline: Jan 28, 2008
http://www.princeton.edu/cav2008/

MEMOCODE'08 - Int'l Conference on Formal Methods and Models for Codesign
(sponsored by SIGDA)
Anaheim, CA
Jun 5-7, 2008
Deadline: Feb 1, 2008
http://svl1.cs.pdx.edu/memocode08/

ICICDT'08 - Int'l Conference on IC Design & Technology
Minatec in Grenoble, France
Jun 2-4, 2008
Deadline: Feb 29, 2008
http://www.icicdt.org/

MWSCAS'08 - Int'l Midwest Symposium on Circuits and Systems
Knoxville, TN
Aug 10-13, 2008
Deadline: Mar 12, 2008
http://www.eecs.utk.edu/mwscas/

PACT'08 - Int'l Conference on Parallel Architectures and Compilation
Techniques
Toronto, Canada
Oct 25-29, 2008
Deadline: Mar 28, 2008
http://www.pactconf.org/

==============================================================================

Upcoming Symposia, Conferences and Workshops:
---------------------------------------------

ICM'07 - Int'l Conference on Microelectronics
Cairo, Egypt
Dec 29-31, 2007
http://www.ieee-icm.com/

VLSI'08 - Int'l Conference on VLSI Design (sponsored by SIGDA)
ES'08 - Int'l Conference on Embedded Systems
Hyderabad, India
Jan 4-8, 2008
http://vlsiconference.com/vlsi2008/

ASP-DAC'08 - Asia and South Pacific Design Automation Conference
(sponsored by SIGDA)
Seoul, Korea
Jan 21-24, 2008
http://www.aspdac.com/aspdac2008/

HiPEAC'08: Int'l Conference on High Performance Embedded Architectures &
Compilers
Goteborg, Sweden
Jan 27-29, 2008
http://www.hipeac.net/hipeac2008/

ISSCC'08 - Int'l Solid-State Circuits Conference
San Francisco, CA
Feb 3-7, 2008
http://isscc.org/isscc/

LATW'08 - Latin-American Test Workshop
Puebla, Mexico
Feb 17-20, 2008
http://www-elec.inaoep.mx/latw2008/

FPGA'08 Int'l Symposium on Field-Programmable Gate Arrays (sponsored by SIGDA)
Monterey, California
February 24-26, 2008
http://www.isfpga.org

TAU'08 - Int'l Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (Sponsored by SIGDA)
Monterey, CA
Feb 25-26, 2008
http://www.tauworkshop.com/

DATE'08 - Design Automation and Test in Europe (sponsored by SIGDA)
Munich, Germany
Mar 10-14, 2008
http://www.date-conference.com/

ISQED'08 - Int'l Symposium on Quality Electronic Design
San Jose, CA
Mar 17-19, 2008
http://www.isqed.org/

SPL'08 - Southern Conference on Programmable Logic
Bariloche-Patagonia, Argentina
Mar 26-28, 2008
http://www.splconf.org/

ASYNC'08: Int'l Symposium on Asynchronous Circuits and Systems
Newcastle, UK
Apr 7-11, 2008
http://async.org.uk/async2008/

NOCS'08 - Int'l Symposium on Networks-on-Chips
Newcastle, UK
Apr 7-11, 2008
http://async.org.uk/nocs2008/

ISPD'08 - Int'l Symposium on Physical Design (sponsored by SIGDA)
Portland, OR
Apr 13-16, 2008
http://www.ispd.cc/

RAW'08 - Reconfigurable Architectures Workshop
Miami, FL
Apr 14-15, 2008
http://www.ece.lsu.edu/vaidy/raw/

GLSVLSI'08 - Great Lakes Symposium on VLSI (Sponsored by SIGDA)
Orlando, FL
May 4-6, 2008
http://www.glsvlsi.org/

SLIP'08 - Int'l Workshop on System Level Interconnect Prediction
Newcastle, UK
Apr 5-6, 2008
http://www.sliponline.org/

ISVLSI'08 - Annual Symposium on VLSI
Montpellier, France
Apr 7-9, 2008
http://www.lirmm.fr/isvlsi2008/

ISCAS'08 - Int'l Symposium on Circuits and Systems
Seattle, WA
May 18-21, 2008
http://iscas2008.org/

ICAC'08 - Int'l Conference on Autonomic Computing
Chicago, IL
Jun 2-6, 2008
http://www.acis.ufl.edu/~icac2008/

DAC'08 - Design Automation Conference (sponsored by SIGDA)
Anaheim, CA
Jun 9-13, 2008
http://www.dac.com/

==============================================================================

Upcoming Funding Opportunities
------------------------------------

SRC

Call for Research in System-Level/High-Level Tools and Logic/Physical Design
Tools
Deadline: January 3, 2008
http://grc.src.org/fr/S200710_Call.asp


James S. McDonnell Foundation

Studying Complex Systems - 21st Century Science Collaborative Activity
Deadline: continuous
http://www.jsmf.org/programs/cs/


ETS

Postdoctoral Fellowship Award Program
Deadline: February 1, 2008
http://www.ets.org/portal/site/ets/menuitem.1488512ecfd5b8849a77b13bc3921509/?vgnextoid=a7d6d635e06ed010VgnVCM10000022f95190RCRD&vgnextchannel=0d03d635e06ed010VgnVCM10000022f95190RCRD


DOE

Advanced Scientific Computing Research (ASCR)  (DE-PS02-08ER08-01)
Deadline: September 30, 2008
http://www.science.doe.gov/grants/FAPN08-01.html


IBM

IBM Herman Goldstine Fellowship
Deadline: January 5, 2008
http://domino.research.ibm.com/comm/research_projects.nsf/pages/goldstine.index.html


NIH

NLM Knowledge Management & Applied Informatics Grants
Deadline:  January 25, 2008
http://grants1.nih.gov/grants/guide/pa-files/PAR-07-236.html

Information Technologies and the Internet in Health Services and Intervention
Delivery (R03)
Deadline:  February 16, 2008
           June 16, 2008
           October 16, 2008
http://grants2.nih.gov/grants/guide/pa-files/PA-06-225.html


DOD

Young Investigator Program (YIP)
January 12, 2008
http://www.onr.navy.mil/sci_tech/3t/corporate/yip.asp

Microsystems Technology Office-Wide BAA
Deadline: January 14, 2008
http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07%2D18/SynopsisP.html

Homeland Security (2.2.1) - N61339-02-R-0071
Deadline: Continuous. This BAA expires on January 30, 2008
http://www1.fbo.gov/spg/DON/NAVAIR/N61339/N61339-02-R-0071/Attachments.html

Cognitive Technology Threat Warning System (CT2WS)
Deadline: April 11, 2008
http://fedbizopps.cos.com/cgi-bin/getRec?id=20070412a1

Modeling and Simulation for Information Systems Research
Deadline:   FY 09 should be submitted by June 1, 2008
            FY 10 should be submitted by June 1, 2009
http://fedbizopps.cos.com/cgi-bin/getRec?id=20061030a9

Military Networking Technology for Global Information Exchange (GIE)
Deadline: Continuous until September, 2008
http://fedbizopps.cos.com/cgi-bin/getRec?id=20040909a11

Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA)
Deadline: September 30, 2008
http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html

SPINS in Semiconductors
Deadline: December 31, 2008
http://fundingopps.cos.com/alerts/57993

Artificial Intelligence Technologies
Deadline: December 31, 2008
http://heron.nrl.navy.mil/contracts/baa.htm

Quantum Information Science and Technology
Deadline: December 31, 2008
http://heron.nrl.navy.mil/contracts/0708baa/baa.htm

Microsystems Technology Office-Wide
Deadline: January 14, 2009
http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07-18/Attachments.html

Warrior Systems Technologies - Body-Worn Systems, Hand Held Devices, and
Smart-Lightweight Electronic Components/Modules for Soldier Protection,
Knowledge Management and Cognitive Improvement
Deadline: Continuous. (April 1, 2007 ~ March 31, 2009)
https://www3.natick.army.mil/ssbaa.htm

Joint National Training Capability Broad Agency Announcement
Deadline: May 14, 2009
http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990

TRADOC FOC-03-06: Situational Understanding
Deadline: Continuous until August 26, 2009
https://abop.monmouth.army.mil/baas.nsf/1f6c118700adf19d85256d3d0051f9a2/31926e7d7d4b2e9285256f6d0056ce06?OpenDocument

BAA for Simulation and Training Technology R&D
Deadline: Continuous until December 31, 2010
http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451

Army Research Office (ARO) Broad Agency Announcement for Basic and Applied
Scientific Research (W911NF-07-R-0003)
Deadline: Continuous through September 30, 2011
http://www.arl.army.mil/www/default.cfm?Action=6&Page=8

High Density Optical Memory
Deadline: Continuous
http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf

Quantum Electronic Solids
Deadline: Continuous
http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf

Distributed Intelligence
Deadline: Continuous
http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf


NSF

Expeditions in Computing
Deadline: Letter of Intent Due Date(s) (required):
    July 10, 2008
    July 10, Annually Thereafter
   Preliminary Proposal Due Date(s) (required):
        December 30, 2007
        September 10, 2008
        September 10, Annually Thereafter
http://www.nsf.gov/pubs/2007/nsf07592/nsf07592.htm

Software for Real-World Systems (SRS) - NSF 07-599
Deadline: January 17, 2008
http://www.nsf.gov/pubs/2007/nsf07599/nsf07599.htm

Scientific Computing Research Environments for the Mathematical Sciences
(SCREMS) - NSF 07-502
Deadline: January 24, 2008
http://www.nsf.gov/pubs/2007/nsf07502/nsf07502.htm

Broadening Participation Research Initiation Grants in Engineering (BRIGE) -
NSF 07-589
Deadline: February 8, 2008
http://www.nsf.gov/pubs/2007/nsf07589/nsf07589.htm

Strategic Technologies for Cyberinfrastructure (STCI)
Deadline :    February 14, 2008
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=500066&org=NSF&sel_org=NSF&from=fund

Engineering Design (ED)
Deadline :   February 15, 2008
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13340

Emerging Models and Technologies for Computation (EMT)
Deadline: March 13, 2008
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=503220&org=CISE&from=home

Assembling the Tree of Life (ATOL)
Deadline: March 14, 2008
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=5129&org=CISE&from=home

Theoretical Foundations 2008 (TF08)
Deadline: March 31, 2008
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=500026&org=CISE&from=home

Collaborative Research in Computational Neuroscience (CRCNS)
Deadline: February 26, 2008
          October 30, 2008
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=5147&org=CISE&from=home

High Performance Computing Acquisition: Towards a Petascale Computing
Environment for Science and Engineering - NSF 05-625
Deadline: November 28, 2008
http://www.nsf.gov/pubs/2005/nsf05625/nsf05625.htm


==============================================================================

Call for Participation:
-----------------------
2008 Asia and South Pacific Design Automation Conference
January 21-24, 2008 COEX, Seoul, Korea
http://www.aspdac.com

Features of ASP-DAC 2008:

* Keynote Addresses

Keynote I: Tuesday, January 22, 9:00-10:00, .A Brand New Wireless Day.
Jan M. Rabaey (Univ. of California, Berkeley, USA)

Keynote II: Wednesday, January 23, 9:00-10:00, .The Evolution of SoC
Platform According to the New Mobile Paradigm.
Ki-Soo Hwang (Core Logic, Korea)

Keynote III: Thursday, January 24, 9:00-10:00, .The Future of Semiconductor
Industry - A Foundry's Perspective.
F. C. Tseng (TSMC, Taiwan)

* Technical Program Committee carefully reviewed and only 100 regular papers
(123 papers including short papers) accepted out of 350 papers submitted. It
is an outstanding program that covers a variety of key topics from system
level design to physical design. Four Special sessions cover up-to-date topics
of DFM, embedded software, EDA challenges, and multi-processor platforms.

* Designers. Forum was conceived as a unique program that shares design
experience and solutions of real product designs of the industries among SoC
designers and EDA academia/developers.

* Tutorials: January 21, 2008, two full-day and four half-day tutorials are
scheduled to provide introductions to hot topics like DFM tools and
methodologies, functional verification, low power, physical design, and
practical embedded system design.

* The University LSI Design Contest was conceived as a unique program of
ASP-DAC Conference. The purpose of the Contest is to encourage education and
research in LSI design, and its realization on chips at universities, and
other educational organizations by providing opportunities to present and
discuss innovative and state-of-the-art designs at the conference.

* Student Forum at the ASP-DAC 2008 is a poster session for graduate students
to present and discuss their research with people in the EDA community. A
professional review committee selected quality posters among the submissions.
Please join the poster session and give feedbacks to the presenters and also
have discussion with people from academia and industry.


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Last revised by I. Markov - 05/21/06
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