=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membersip. Circulation: 2,700 =============================================================================== 01 October 2007 ACM/SIGDA E-NEWSLETTER Vol. 37, No. 19 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel (2) What is IEEE P1801 (Unified Power Format) ? Author: Phillip Stanley-Marbell (3) Paper Submission Deadlines From: Hai Zhou (4) Upcoming Conferences and Symposia From: Hai Zhou (5) Upcoming Funding Opportunities From: Qinru Qiu (6) Call for Nominations: Computer-Aided Verification Award (7) Call for Participation: The CADathlon at ICCAD From: Matthew Guthaus (8) Call for Papers: ACM Great Lakes Symposium on VLSI From: Hai Zhou =============================================================================== Dear ACM/SIGDA members, In this issue, we have included the article "What is IEEE P1801 (Unified Power Format)?" by Phillip Stanley-Marbell. In addition, "SIGDA News" column contains a number of fresh headlines. We have also updated the contents of other regular columns. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Qing Wu, E-Newsletter Editor; Matthew Guthaus, E-Newsletter Associate Editor; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "Kaufman Award Honors Brayton" http://eetimes.com/news/design/showArticle.jhtml?articleID=202101912 "Design automation pioneer Robert Brayton is to receive the Nobel Prize of the EDA Industry--the Phil Kaufman Award 2007. Brayton is credited with seminal contributions to the fundamental design automation algorithms used to fabricate integrated circuits, ranging from logic synthesis to the silicon compiler." "Moore Reflects On His Law" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201807397 SAN FRANCISCO - On what Intel Corp. billed at the 50th anniversary of the integrated circuit, Gordon Moore, the company's founder and chairman emeritus, took to the stage at the Intel Developer Forum here for an informal reflection on his thoughts on everything from cubicles to ecology. Here are some excerpts from his conversation with Moira Gunn, moderator of National Public Radio's "TechNation" program. "Measure Power Efficiently, Effectively--and Early" http://www.eetimes.com/news/design/showArticle.jhtml?articleID=201805258 Designers frequently turn to advanced power reduction techniques such as power shutoff (PSO) and multi-supply-voltage (MSV) architectures to help reach power consumption targets in advanced technology nodes (90 nanometers and below). Those techniques, however, can only be implemented if they are considered during the architecture phase of the design cycle. So it is important that power estimates be made early in the design project. "Synopsys Recognizes Engineers' Technical Excellence With Best Paper Awards at SNUG Boston Conference" http://money.cnn.com/news/newsfeeds/articles/prnewswire/AQW07726092007-1.htm Synopsys, Inc. today announced the Best Paper Awards for the ninth annual Synopsys Users' Group (SNUG(R)) in Boston, MA. At the Boston event, the first place award for Best Paper went to Clifford Cummings of Sunburst Design, Inc. for "SystemVerilog Implicit Port Enhancements Accelerate System Design and Verification." Second place went to Jonathan Bromley of Doulos for "Creating Stimulus and Stimulating Creativity: Using the VMM Scenario Generator." Third place went to Wilson Snyder of SiCortex, Inc. for "The Ten Edits I Make Against Most IP." The award for Best First-Time Presenter went to Dale Donchin of Analog Devices, Inc. for "From Validation to Generation: Making Hercules Do the Heavy Lifting." The winning papers were selected by the attendees and the SNUG Technical Committee. "Synthetic Biology? Memory In Yeast Cells Synthesized" http://www.sciencedaily.com/releases/2007/09/070915081448.htm Harvard Medical School researchers have successfully synthesized a DNA-based memory loop in yeast cells, findings that mark a significant step forward in the emerging field of synthetic biology. "Viewpoint: Wanted -- an IP Manager" http://www.eetimes.com/news/design/showArticle.jhtml?articleID=202200199 Whenever certain SoC design tasks take on a high level of importance (for example, being on the critical path of design completion), design teams usually add a task-specific manager. Examples include a testability manager (when DFT becomes an important part of chip design), a physical layout manager (when shrinking process nodes and increased clock speeds make layout very difficult), and, more recently, a DFM manager (when help is needed to ensure maximum yields, and profits, for chip vendors). But the question remains: Where is the IP manager? "Worldwide Semiconductor Sales Up Sharply in August" http://www10.edacafe.com/nbc/articles/view_article.php?section=ICNews&articleid=439783 Worldwide sales of semiconductors rose sharply in August, growing to $21.6 billion, an increase of 4.5 percent over August 2006, when sales were $20.5 billion, and an increase of 4.9 percent from July of this year when sales were $20.6 billion, the Semiconductor Industry Association (SIA) reported today. "Indian Center to be Xilinx Global R&D Hub" http://eetimes.com/news/design/showArticle.jhtml?articleID=201807121 Xilinx Inc.'s center in Hyderbad will serve as its global R&D hub. Until now, the Indian center focused on developing IP cores. It has developed about 60 cores, many based on 65-nm process technology. It will tackle software, systems and application development with teams focusing on each area. The system and application center will focus on domain-specific platforms for Xilinx customers developing products for the consumer electronics, telecommunications and video markets. A software center will work on EDA tools and algorithm development, verification and FPGA benchmarking. "North American Semiconductor Equipment Industry Posts August 2007 Book-to-Bill Ratio of 0.83" http://www10.edacafe.com/nbc/articles/view_article.php?section=ICNews&articleid=435258 North American-based manufacturers of semiconductor equipment posted $1.39 billion in orders in August 2007 (three-month average basis) and a book-to-bill ratio of 0.83 according to the August 2007 Book-to-Bill Report published today by SEMI. A book-to-bill of 0.83 means that $83 worth of orders were received for every $100 of product billed for the month. "Startup Shows 'Dielectric-as-Sensor' Technique for ICs" http://eetimes.com/news/design/showArticle.jhtml?articleID=201807062 ChipSensors Ltd. (Limerick, Ireland), a fabless chip company started in 2006, has developed a technology that allows the surface of an IC to be used to sense temperature, humidity, certain gases and pathogens, the company has claimed. "Silicon in Autos Stirs Patent Plans" http://www.us.design-reuse.com/news/news16790.html Customers are demanding more electronic value in automobiles as part of their driving experience. As a result, automotive manufacturers must consider carefully the intellectual property (IP) culture of the semiconductor industry, where patent licensing strategies are considerably different. In this case, IP refers to patent and trademark rights. "X86 War Cuts to the Cores" http://www.us.design-reuse.com/news/news16793.html The latest maneuvers in the chess match between Advanced Micro Devices Inc. and Intel Corp. find the rivals advancing toward similar architectures. That leaves AMD in a difficult spot, because it trails Intel by an entire process node in silicon technology. There are enough moves ahead that no endgame is at hand, but it's not looking good for AMD. "India Team Unveils New Approach To Test Digital Modules" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201806902 A team of researchers at the Indian Institute of Technology in Kharagpur have developed new approach for testing digital modules embedded in mixed-signal VLSI circuits. The team's methodology was based on analog backtrace, a technique that uses analog blocks themselves to test digital blocks. The methodology stresses the controllability of the inputs of the digital block by exploiting the analog block. "Scientists Charged! The Neutron's Not So Neutral After All" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201807560 Every engineering student is taught that electrons have a negative charge, protons a positive charge and neutrons are electrically neutral. Now, scientists claim to have discovered that neutrons are not as neutral as they thought. Using data confirmed by three separate particle accelerators, University of Washington researchers claim that neutrons have three layers of charge-negative/positive/negative-that together sum to zero, accounting for the historical belief that neutrons are neutral. However, the new, more detailed understanding of how that neutrality comes about could enable a new breed of nuclear energy generators and weaponry. "Power Group Rallies Around Roadmap" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=202101214 At its first technical conference, the Power.org group laid out a roadmap of stepwise improvements for Power microprocessors. Led by IBM Corp. and Freescale Semiconductor, the group seeks to keep its software base stable while expanding use of multi-core techniques and its penetration into consumer markets. "RPI Researchers Grow 'Nanoblades'" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=202101616 Researchers at Rensselaer Polytechnic Institute have created a razor-like nanoblades that could have applications in energy storage and fuel cell technology. Nanoblades are first-of-their-kind magnesium nanomaterials that challenge the conventional wisdom about nanostructure growth, according to the researchers. "Researchers Seek To Patent 'Memory Doubler' Algorithm" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=202102334 In the opening scene of "Johnny Mnemonic," the film version of the William Gibson short story, Keanu Reeves loads a "memory doubler" to increase his brain implant's storage capacity. Now a new "memory doubler" algorithm for embedded RAM has been invented by NEC Laboratories America, Inc. and Northwestern University. "Nanotubes Help Detect, Repair Wing Cracks" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=202102871 Nanotechnology can't relieve airport congestion, but it could be used to repair defects in aircraft wings. Researchers at Rensselaer Polytechnic Institute (Troy, N.Y.) have demonstrated the ability of carbon nanotubes to enable the self-healing of defects in aircraft wings and other polymer composites. Carbon nanotubes mixed into an epoxy coating that adds just 1 percent to a polymer composite's total weight enabled a matrix of embedded wires to initiate self-healing repairs in structure surfaces. "Sony To Launch World's First OLED Ultra-Thin TV" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=202103598 Sony Corp. said it will launch an ultra-thin flat TV in December, the world's first television based on organic light-emitting diode (OLED) technology into an $82 billion market dominated by LCD and plasma models. OLED panels are energy efficient, make thin and light displays. They offer crisp pictures and have strength in showing fast-moving images, suitable for watching sports events and action movies, but size is proving a limitation. "Forum Looks To Next Generation Wireless USB" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=202103741 The Wireless USB Promoter Group has started developing the next version of the Wireless USB specification, dubbed 1.1, that will build on the existing 1.0 standard. Specification enhancements include further options for first-time association of devices, improved power efficiency, and support for UWB frequencies above 6 GHz. "Intel Pushes Core Arrays, WiMax" http://www.edn.com/article/CA6479487.html?industryid=47037 Intel unfurled a vision of processors this morning that goes well beyond its traditional markets, pushing into verticals such as financial services and high-end graphics, as well as global wireless communication via WiMax. "LCD Panels Shift to LED Lighting" http://eetimes.com/news/design/showArticle.jhtml?articleID=201805563 Even if the next LCD you buy has pretty much the same characteristics as the last LCD you bought, a change is likely to have occurred behind the scenes. In display sizes below about 15 inches, the tried-and-true cold-cathode fluorescent lamp (CCFL) lighting system for the LCD is rapidly being replaced by light-emitting diodes. "Coverity Raises Static Analysis for Codes a Notch" http://eetimes.com/news/design/showArticle.jhtml?articleID=201807530 The concept of Boolean satisfiability is being applied to identify "bugs" in software code and consequently establish to code writers' satisfaction that lines of code are predominantly bug-free. "Automotive ASIC Market on 8.2% CAGR, Says Analyst" http://eetimes.com/news/design/showArticle.jhtml?articleID=201807454 The global market for automotive ASICs is set to benefit from the Asian market's revenue contributions and reach $4.10 billion in 2010, according to market research firm Frost & Sullivan (Palo Alto, Calif.). "Text-entry Algorithm Takes Aim at Qwerty" http://eetimes.com/news/design/showArticle.jhtml?articleID=201808008 The venerable keyboard may be obsolete, according to Kannuu Inc. (Dallas), which will demonstrate a one-thumb text-entry technique in San Diego today. By using smart software that anticipates the words being sought by users, the Kannuu data-entry method is said to enable a user of any device that has a screen and a four-way dial to input text with one thumb at speeds rivaling full-keyboard text entry. "Demystifying Multithreading and Multi-core" http://eetimes.com/news/design/showArticle.jhtml?articleID=202102042 Is multithreading better than multi-core? Is multi-core better than multithreading? The fact is that the best vehicle for a given application might have one, the other or both. Or neither. They are independent (but complementary) design decisions. As multithreaded processors and multi-core chips become the norm, architects and designers of digital systems need to understand their respective attributes, advantages and disadvantages. ============================================================================== What is IEEE P1801 (Unified Power Format) ? ------------------------------------------- Phillip Stanley-Marbell The Unified Power Format (UPF), currently undergoing standardization efforts by the IEEE P1801 Low Power Working Group, is a proposal for the specification of aspects of hardware designs relating to their power adaptation facilities. UPF is concerned with two separate but related issues. First, it enables the explicit specification of the aspects of a design relating to its power dissipation, such as the system's different power supply rails and the associated domains running off these supplies, different threshold voltage domains in a multi-Vt technology, the system's operations states with different power dissipation properties, and the semantics of system behavior when in different power states (e.g., whether registers keep their state when a supply rail is gated); this is a design issue, and is addressed in UPF by the UPF commands for specifying low-power design intent. Second, UPF enables the specification of information pertaining to power estimation results from hardware designs; this is a measurement issue, and is addressed in UPF by the forward and backward Switching Activity Interchange Format (SAIF) files. From the viewpoint of design, UPF enables designers to specify the interconnection of system components as they pertain to power dissipation. For example, a UPF specification for an embedded processor in which the processor core operates off a different voltage rail from its peripherals might define two power supply nets in a UPF description, corresponding to two different power domains within the UPF specification, and may define the core and peripherals to be each connected to one of these. UPF encapsulates the semantics of a system's power-related design and measurement issues into a separate specification in which the components have a direct correspondence to items in the hardware logic specification. The specification of this logical structure of power-dissipation- related design and runtime information separately in a UPF description aids activities such as simulation, where the power states of different system components might be deduced from analysis of the UPF description in the context of a given workload. The importance of UPF to integrated circuit and system designers is obvious, with the increasing criticality of understanding the power-dissipation behavior of systems, as well as the increasing use of multiple supply voltages in existing designs and design starts. What does UPF mean for the academic research community? Research targeted at design automation of low-power systems, whether focusing on the system-level, circuit-level, layout, or elsewhere, may be able to build new kinds of algorithms, and their implementations in tools, that take advantage of the coherent isolation of power-related concepts in UPF. For example, since the UPF specification for a system can be used to provide a detailed description of its power supply network and power states independent of the disclosure of its logic-level implementation, UPF specifications may be provided by semiconductor device vendors (e.g., for a microcontroller, microprocessor, or integrated system-on-chip), enabling the evaluation of power consumption behavior under different workloads. This will however require appropriate tools for "simulating" or otherwise analyzing UPF specifications, and a means of specifying such workloads to "drive" the specifications, if relevant. UPF is described in detail in the ``Unified Power Format Standard, version 1.0'', available online at http://www.accellera.org/activities/p1801_upf/. ============================================================================== Submission deadlines: --------------------- ISCAS'08 - Int'l Symposium on Circuits and Systems Seattle, WA May 18-21, 2008 Deadline: Oct 5, 2007 http://iscas2008.org/ ISPD'08 - Int'l Symposium on Physical Design (sponsored by SIGDA) Portland, OR Apr 13-16, 2008 Deadline: Oct 7, 2007 http://www.ispd.cc/ RAW'08 - Reconfigurable Architectures Workshop Miami, FL Apr 14-15, 2008 Deadline: Oct 8, 2007 http://www.ece.lsu.edu/vaidy/raw/ ASYNC'08: Int'l Symposium on Asynchronous Circuits and Systems Newcastle, UK Apr 7-11, 2008 Deadline: Oct 15, 2007 http://async.org.uk/async2008/ SPL'08 - Southern Conference on Programmable Logic Bariloche-Patagonia, Argentina Mar 26-28, 2008 Deadline: Nov 1, 2007 http://www.splconf.org/ LATW'08 - Latin-American Test Workshop Puebla, Mexico Feb 17-20, 2008 Deadline: Nov 1, 2007 http://www-elec.inaoep.mx/latw2008/ DAC'08 - Design Automation Conference (sponsored by SIGDA) Anaheim, CA Jun 9-13, 2008 Deadline: Nov 19, 2007 http://www.dac.com/ NOCS'08 - Int'l Symposium on Networks-on-Chips Newcastle, UK Apr 7-11, 2008 Deadline: Nov 19, 2007 http://async.org.uk/nocs2008/ GLSVLSI'08 - Great Lakes Symposium on VLSI Orlando, FL May 4-6, 2008 Deadline: Nov 30, 2007 http://www.glsvlsi.org/ ISVLSI'08 - Annual Symposium on VLSI Montpellier, France Apr 7-9, 2008 Deadline: Dec 5, 2007 http://www.lirmm.fr/isvlsi2008/ SLIP'08 - Int'l Workshop on System Level Interconnect Prediction Newcastle, UK Apr 5-6, 2008 Deadline: Dec 7, 2007 http://www.sliponline.org/ ============================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- CODES+ISSS'07 - Int'l Conference on Hardware-Software Codesign and System Synthesis (sponsored by SIGDA) Salzburg, Austria sep 30-Oct 5, 2007 http://www.codes-isss.org/ VLSI-SoC'07 - Int'l Conference on Very Large Scale Integration Atlanta, GA Oct 15-17, 2007 http://www.vlsisoc2007.gatech.edu/ ICCAD'07 - Int'l Conference on Computer-Aided Design (sponsored by SIGDA) San Jose, CA Nov 4-8, 2007 http://www.iccad.com/ PDCS'07 - Int'l Conference on Parallel and Distributed Computing Systems Cambridge, MA Nov 19-21, 2007 http://www.iasted.org/conferences/home-590.html ICST'07 - Int'l Conference on Sensing Technology Palmerston North, New Zealand Nov 26-28, 2007 http://icst.massey.ac.nz/ BIOCAS'07 - Biomedical Circuits and Systems Conference London, UK Nov 27-30, 2007 http://biocas.grm.polymtl.ca/ MICRO'07 - Int'l Symposium on Microarchitecture Chicago, IL Dec 1-5, 2007 http://www.microarch.org/micro40/ IP-SOC'07 - IP Based SoC Design Grenoble, France Dec 5-6, 2007 http://www.us.design-reuse.com/ipsoc2006/ ICPADS'07 - Int'l Conference on Parallel and Distributed Systems Hsinchu, Taiwan Dec 5-7, 2007 http://www.ccrc.nthu.edu.tw/icpads2007/ ICFPT'07 - Int'l Conference on Field-Programmable Technology Kitakyushu, Japan Dec 12-14, 2007 http://www.kameyama.ecei.tohoku.ac.jp/icfpt07/ EUC'07 - Int'l Conference on Embedded and Ubiquitous Computing Taipei, Taiwan Dec 17-20, 2007 http://www.cs.ccu.edu.tw/~shiwulo/euc07/ HiPC'07 - Int'l Conference on High Performance Computing Goa, India Dec 18-21, 2007 http://www.hipc.org/ ICM'07 - Int'l Conference on Microelectronics Cairo, Egypt Dec 29-31, 2007 http://www.ieee-icm.com/ VLSI'08 - Int'l Conference on VLSI Design (sponsored by SIGDA) ES'08 - Int'l Conference on Embedded Systems Hyderabad, India Jan 4-8, 2008 http://vlsiconference.com/vlsi2008/ ASP-DAC'08 - Asia and South Pacific Design Automation Conference (sponsored by SIGDA) Seoul, Korea Jan 21-24, 2008 http://www.aspdac.com/aspdac2008/ HiPEAC'08: Int'l Conference on High Performance Embedded Architectures & Compilers Goteborg, Sweden Jan 27-29, 2008 http://www.hipeac.net/hipeac2008/ ISSCC'08 - Int'l Solid-State Circuits Conference San Francisco, CA Feb 3-7, 2008 http://isscc.org/isscc/ DATE'08 - Design Automation and Test in Europe (sponsored by SIGDA) Munich, Germany Mar 10-14, 2008 http://www.date-conference.com/ ISQED'08 - Int'l Symposium on Quality Electronic Design San Jose, CA Mar 17-19, 2008 http://www.isqed.org/ ============================================================================== Upcoming Funding Opportunities ------------------------------------ ANS Student Grant Deadline: Continuous. The committee reviews and votes on the requests at its June and November meetings. http://rrsd.ans.org/grants.html Microsoft Microsoft Research New Faculty Fellowship Program Deadline: November 19, 2007 http://research.microsoft.com/ur/us/nff/overview.aspx IBM IBM Herman Goldstine Fellowship Deadline: January 5, 2008 http://domino.research.ibm.com/comm/research_projects.nsf/pages/goldstine.in dex.html Postgraduate Opportunities Postgraduate Research Participation at the Air Force Research Laboratory, Materials Directorate, Tyndall Air Force Base Deadline: Continuous http://www.orau.gov/orise/edu/USAF/gi-pdRLMD.htm Oak Ridge National Laboratory Advanced Short-Term Research Opportunity Deadline: Continuous http://www.orau.gov/orise/edu/ornl/gi-rgpdASTRO.htm Postdoctoral Fellowships (PDF) Deadline: October 15, 2007 http://www.nserc.ca/sf_e.asp?nav=sfnav&lbi=3a Faculty Opportunities Faculty Research Participation at the U.S. Army Research Laboratory Deadline: Continuous http://see.orau.org/ProgramDescription.aspx?Program=10084 American Association of University Women Summer/Short-Term Research Publication Grants Deadline: November 15, 2007 http://www.aauw.org/education/fga//fellowships_grants/american.cfm International Fellowships Deadline: December 1, 2007 http://www.aauw.org/fga/fellowships_grants/international.cfm ASEE Naval Research Laboratory (NRL) Postdoctoral Fellowship Program Deadline: Continuous. Applications are accepted on an ongoing basis. http://www.asee.org/resources/fellowships/nrl/index.cfm AAWU International Fellowships Deadline: December 1, 2007 http://www.aauw.org/fga/fellowships_grants/international.cfm NIH NLM Knowledge Management & Applied Informatics Grants Deadline: May 25, 2007 September 25, 2007 January 25, 2008 http://grants1.nih.gov/grants/guide/pa-files/PAR-07-236.html NASA Broad Agency Announcement (BAA) - N61339-06-R-0107 (Joint ADL Co-Laboratory) Deadline: Continuous http://nawctsd.navair.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?client=STRICOM Applied Information Systems Research - NNH07ZDA001N-AISR Deadline: To be announced (TBA) http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId=%7B89FBF877-DD5F-AC6E-DAB3-AE19504EA70D%7D&path=open DOD TRADOC FOC-03-06: Situational Understanding Deadline: Continuous until August 26, 2009 https://abop.monmouth.army.mil/baas.nsf/1f6c118700adf19d85256d3d0051f9a2/31926e7d7d4b2e9285256f6d0056ce06?OpenDocument Department of Defense Experimental Program to Stimulate Competitive Research (DEPSCoR) - ONR Deadline: October 26, 2007 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 Position and Navigation Technology Research, Development and Demonstration for Command and Control Directorate Deadline: October 31, 2007 http://fedbizopps.cos.com/cgi-bin/getRec?id=20070910a11 Military Networking Technology for Global Information Exchange (GIE) Deadline: Continuous until September, 2008 http://fedbizopps.cos.com/cgi-bin/getRec?id=20040909a11 Young Faculty Award Deadline: October 25, 2007 http://fedbizopps.cos.com/cgi-bin/eps/spg/ODA/DARPA/CMO/RA07-44/Attachments.html Brain Network Analysis and Modeling for Communication and Orientation - BAA-07-036 Deadline: October 23, 2007 http://www.grants.gov/search/search.do?oppId=14530&mode=VIEW 21st Century Approach to Electronic Device Reliability - BAA-07-036 Deadline: October 23, 2007 http://www.grants.gov/search/search.do?oppId=14530&mode=VIEW Microsystems Technology Office-Wide BAA Deadline: January 14, 2008 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07%2D18/SynopsisP.html ASEE-NRL Postdoctoral Fellowship Program Deadline: Continuous http://hroffice.nrl.navy.mil/jobs/postdoc.htm University Research Instrumentation Program (DURIP) - AFOSR BAA 2007-9 Deadline: August 21, 2007 http://www.afosr.af.mil/ResearchAreas/funding_otherOpp.htm Cognitive Technology Threat Warning System (CT2WS) Deadline: April 11, 2008 http://fedbizopps.cos.com/cgi-bin/getRec?id=20070412a1 Warrior Systems Technologies - Body-Worn Systems, Hand Held Devices, and Smart-Lightweight Electronic Components/Modules for Soldier Protection, Knowledge Management and Cognitive Improvement Deadline: Continuous. (April 1, 2007 ~ March 31, 2009) https://www3.natick.army.mil/ssbaa.htm Homeland Security (2.2.1) - N61339-02-R-0071 Deadline: Continuous. This BAA expires on January 30, 2008 http://www1.fbo.gov/spg/DON/NAVAIR/N61339/N61339-02-R-0071/Attachments.html Microsystems Technology Office-Wide Deadline: January 14, 2009 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07-18/Attachments.html SPINS in Semiconductors Deadline: December 31, 2008 http://fundingopps.cos.com/alerts/57993 Artificial Intelligence Technologies Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/baa.htm Quantum Information Science and Technology Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Young Investigator Program (YIP) January 12, 2008 http://www.onr.navy.mil/sci_tech/3t/corporate/yip.asp High Density Optical Memory Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Quantum Electronic Solids Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Distributed Intelligence Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF Cyber-Enabled Discovery and Innovation (CDI) Deadline: October 30, 2007 - November 30, 2007 August 30, 2008 - September 30, 2008 August 30 - September 30, Annually Thereafter High Performance Computing Acquisition: Towards a Petascale Computing Environment for Science and Engineering - NSF 05-625 Deadline: November 30, 2007 November 28, 2008 http://www.nsf.gov/pubs/2005/nsf05625/nsf05625.htm Computer Systems Research (CSR) - NSF 07-504 Deadline: November 9, 2007 http://www.nsf.gov/pubs/2007/nsf07504/nsf07504.htm Cyber Trust - NSF 07-500 Deadline: November 14, 2007 http://www.nsf.gov/pubs/2007/nsf07500/nsf07500.htm Foundations of Computing Processes and Artifacts (CPA) - NSF 07-587 Deadline: December 7, 2007 http://www.nsf.gov/pubs/2007/nsf07587/nsf07587.htm Broadening Participation Research Initiation Grants in Engineering (BRIGE) - NSF 07-589 Deadline: February 8, 2008 http://www.nsf.gov/pubs/2007/nsf07589/nsf07589.htm Expeditions in Computing Deadline: Letter of Intent Due Date(s) (required): November 05, 2007 July 10, 2008 July 10, Annually Thereafter Preliminary Proposal Due Date(s) (required): December 30, 2007 September 10, 2008 September 10, Annually Thereafter http://www.nsf.gov/pubs/2007/nsf07592/nsf07592.htm Software for Real-World Systems (SRS) - NSF 07-599 Deadline: January 17, 2008 http://www.nsf.gov/pubs/2007/nsf07599/nsf07599.htm Information and Intelligent Systems: Advancing Human-Centered Computing, Information Integration and Informatics, and Robust Intelligence - NSF 07-577 Deadline: October 23, 2007 for Medium Projects November 19, 2007 for Large Projects December 10, 2007 for Small Projects http://www.nsf.gov/pubs/2007/nsf07577/nsf07577.htm Strategic Technologies for Cyberinfrastructure (STCI) Deadline : August 9, 2007 February 14, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=500066&org=NSF&sel_org=NSF&from=fund Engineering Design (ED) Deadline : October 1, 2007 February 15, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13340 ============================================================================== Call For Participation ------------------------------ Thermal and Design Issues in 3D ICs Albany, New York http://www.sematech.org/meetings/announcements/8334/index.htm Stacking layers of silicon with through-silicon vias.3D ICs.can improve electrical performance, lower power consumption, enable the integration of heterogeneous devices, shrink device size, and reduce cost. However, it can exacerbate thermal problems by increasing both average and peak power densities. 3D ICs will also require new thinking in terms of architecture and design. CAD tools, which form the backbone of the design infrastructure, will need to be considerably enhanced. This workshop will address the nature and magnitude of these thermal challenges, and present design approaches and thermal management solutions that address those challenges. It will also address the broader architecture, design, and CAD tool challenges that must be met to exploit the full potential of 3D ICs. This workshop is being held in conjunction with Advanced Metallization Conference on October 9-11. This workshop will benefit IC manufacturers, designers, materials suppliers, design tool (CAD) users and suppliers, and researchers involved in the development and/or implementation of 3D TSV technology. To register and for more information, please go to http://www.sematech.org/meetings ============================================================================== Call For Nominations ------------------------------ CAV 2008 -- CAV Award http://www.princeton.edu/cav2008 An annual award, called the CAV Award, has been established "For a specific fundamental contribution or a series of outstanding contributions to the field of Computer-Aided Verification." The cited contribution(s) must have been made not more recently than five years ago and not over twenty years ago. In addition, the contribution(s) should not yet have received recognition via a major award, such as the ACM Turing or Kanellakis Awards. The award of $10,000 will be granted to an individual or a group of individuals chosen by the Award Committee from a list of nominations. The Award Committee may choose to make no award in a given year. The CAV Award will be presented in an award ceremony at the Computer-Aided Verification Conference and a citation will be published in a journal of record (currently, Formal Methods in System Design). Anyone, with the exception of members of the Award Committee, is eligible to receive the Award. Anyone can submit a nomination except a member of the Steering Committee of the Computer-Aided Verification Conference, or someone whose term of service on the Award Committee ended within the last two years. The Award Committee can originate a nomination. A nomination must state clearly the contribution(s), explain why the contribution is fundamental or the series of contributions is outstanding, and be accompanied by supporting letters and other evidence of worthiness. Nominations should include a proposed citation (up to 25 words), a succinct (100-250 words) description of the contribution(s), and a detailed statement to justify the nomination. For the CAV Award in 2008, please send nominations to one of the following two Steering Committee members of the Computer-Aided Verification Conference, who will forward the nominations to the Chair of the Award Committee: * Edmund M. Clarke, CMU, emc (at) cs.cmu.edu * Robert P. Kurshan, Cadence, rkurshan (at) cadence.com Nominations must be received by January 28, 2008. ============================================================================== Call For Participation ------------------------------ The CADathlon at ICCAD ACM/SIGDA sponsors the sixth annual EDA programming contest at ICCAD Monday, November 5, 8:00 am - 5:00 pm Sierra Ballroom The CADathlon is a challenging, all-day, programming competition focusing on practical problems at the forefront of Computer-Aided Design, and Electronic Design Automation in particular. The contest emphasizes the knowledge of algorithmic techniques for CAD applications, problem-solving and programming skills, as well as teamwork. In its sixth year as the "Olympic games of EDA," the contest brings together the best and the brightest of the next generation of CAD professionals. It gives the academia and the industry a unique perspective on challenging problems and rising stars, and it also helps attract top graduate students to the EDA field. The contest is open to 2-person teams of graduate students specializing in CAD and currently full-time enrolled in a Ph.D. granting institution in any country. Students are selected based on their academic backgrounds and their relevant EDA programming experiences. Travel grants are provided to qualifying students. The CADathlon competition consists of six problems in the following areas: (1) circuit analysis, (2) physical design, (3) logic and behavioral synthesis, (4) system design and analysis, (5) functional verification, and (6) timing, test, and manufacturing. More specific information about the problems and relevant research papers will be released on the Internet one week prior to the competition. The writers and judges that const ruct and review the problems are experts in EDA from both academia and industry. At the contest, students will be given the problem statements and example test data, but they will not have the judges' test data. Solutions will be judged on correctness and efficiency. Where appropriate, partial credit might be given. The team that earn s the highest score is declared the winner. In addition to handsome trophies, the first place team's prize is a $2,000 cash award. The second place team's prize is a $1,000 cash award. Contest winners will be announced at the ICCAD Opening Session on Tuesday morning and celebrated at the ACM/SIGDA Dinner and Member Meeting on Tuesday evening. The CADathlon competition is sponsored by ACM/SIGDA and several Computer and EDA companies. For detailed contest information and sample problems from last year's competition, please visit the ACM/SIGDA web site at http://www.sigda.org/programs/cadathlon or contact members of the CADathlon organizing committee: Prof. Matthew Guthaus, mrg@soe.ucsc.edu, Prof. Marc Riedel, mriedel@umn.edu, Prof. Puneet Gupta, puneet@ee.ucla.edu, SIGDA representative: Prof. Patrick Madden, pmadden@acm.org. ============================================================================== ACM GLSVLSI 2008 1st Call For Papers http://www.glsvlsi.org/ The 18th edition of GLSVLSI will be held May 4-6 2008, in Orlando, Florida. Original, unpublished papers, describing research in the general area of VLSI are solicited. Both theoretical and experimental research results are welcome. Proceedings will be published by the ACM and will be included in the SIGDA compendium CD-ROM. Program Tracks: * VLSI Design: design of ASICs, microprocessors and micro-architectures, embedded processors, analog/digital/mixed-signal systems, multi-chip modules, FPGAs. * VLSI Circuits: analog/digital/mixed-signal circuits, RF and communication circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits. * Computer-Aided Design (CAD): hardware/software co-design, logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction), algorithms and complexity analysis. * Low Power and Power Aware Design: circuits, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools. * Testing, Reliability, Fault-Tolerance: digital/analog/mixed-signal testing, design for testability and reliability, online testing techniques, static and dynamic defect- and fault-recoverability, and variation-aware design. * Emerging Technologies: nanotechnology, molecular electronics, quantum devices, biologically-inspired computing, single electron transistors, resonant tunneling devices, VLSI aspects of sensor and sensor networks, and CAD tools for emerging technology devices and circuits. Schedule * Paper submission deadline: November 30, 2007 * Acceptance notification: January 15, 2008 * Camera-ready paper due: February 14, 2008 ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06