=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membersip. Circulation: 2,700 =============================================================================== 15 August 2007 ACM/SIGDA E-NEWSLETTER Vol. 37, No. 16 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel (2) Call For Participations : International Symposium on Low Power Electronics and Design (ISLPED) 2007 From: Farzan Fallah (3) Paper Submission Deadlines From: Hai Zhou (4) Upcoming Conferences and Symposia From: Hai Zhou (5) Upcoming Funding Opportunities From: Qinru Qiu (6) Call For Papers : Special Issue on Three-dimensional Integrated Circuits and Microarchitectures From: Yuan Xie (7) Call For Papers : Second Annual Reconfigurable and Adaptive Architecture Workshop (RAAW-2) From: Mohamed Zahran (8) Call For Papers : Special Issue on Demonstrable Software Systems and Hardware Platforms II From: Alex K. Jones (9) Call For Nominations : 2007 ACM Outstanding Ph.D. Dissertation Award in EDA From: Radu Marculescu (10) Call For Papers : ASYNC 2008 From: Stephen A. Edwards =============================================================================== Dear ACM/SIGDA members, The "What is ..." column will continue in Fall of 2007. In this issue, we have included two new "Call For Papers" announcements. In addition, "SIGDA News" column contains a number of fresh headlines. We have also updated the contents of other regular columns. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Qing Wu, E-Newsletter Editor; Matthew Guthaus, E-Newsletter Associate Editor; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "Worldwide Chip Sales Grew by 2.1 Percent in First Half of 2007" http://www10.edacafe.com/nbc/articles/view_article.php?section=ICNews&articleid=417888 Worldwide sales of semiconductors grew to $121 billion in the first half of 2007, an increase of 2 percent from the $118.4 billion reported for the first half of 2006, the Semiconductor Industry Association (SIA) reported today. Second-quarter sales of $59.9 billion declined by 2 percent from the $61.1 billion reported in the first quarter of 2007. Sales in June 2007 amounted to $20 billion, a decline of 1.7 percent from the $20.3 billion reported in May. "Bush Prepares to Sign U.S. Tech Competitiveness Bill" http://eetimes.com/news/design/showArticle.jhtml?articleID=201305594 President George Bush will sign legislation designed to help the U.S. retain its "brainpower advantage. Congress approved and sent to the White House last week (Aug. 2) the America Creating Opportunities to Meaningfully Promote Excellence in Technology, Education and Science (Competes) Act. The legislation is based on recommendations contained in a 2005 government report, "Rising Above the Gathering Storm. "Beyond SoC and SiP: IMEC ponders 3-D circuit design" http://www.edn.com/index.asp?layout=blog&blog_id=1690000169&blog_post_id=1520012152 Buoyed by its ubiquitous application in cell phone handsets, multi-die packaging has become a serious alternative to advanced SoC design across a wide range of markets. The ability to reuse existing designs without integrating them into a larger SoC, to purchase known-good dice from other vendors rather than licensing IP and redesigning it, and the ability to use specialized processes when they are appropriate without increasing the footprint of the resulting chip are all very significant benefits. "Design For Manufacturing: Still Not Ready For Prime Time?" http://www.elecdesign.com/Articles/Index.cfm?AD=1&ArticleID=16305 In EDA, two primary areas still have room for innovation. One is at high levels of abstraction (above RTL), where a stalwart band of startups as well as one or two of EDA's heavier commercial hitters continue to seek a solid and predictable path from an idealized functional specification to a concrete physical representation of a complex system-on-a-chip (SoC) design. "Chip Designers Must Think Like an Architect for Chip-Package Co-Design" http://www.chipdesignmag.com/display.php?articleId=1530 Chip designers need to incorporate package-aware optimization and tradeoff software into their design plan to test how a signal propagates through the die, the package substrate and the PCB. "Israeli Researchers Tout Time Machine Model" http://eetimes.com/news/design/showArticle.jhtml?articleID=201203157 Researchers at the Technion University (Haifa, Israel) claim they have developed a theoretical model of a time machine that, in the distant future, could enable future generations to travel into the past. "Is FPGA a simpler puzzle for ASIC designers?" http://www.edn.com/article/CA6459058.html Over the last 10 years, FPGA vendors have made great strides in overcoming the shortcomings of FPGAs and taking share from the ASIC market. In the late 1990s, FPGA vendors increased the capacity of their devices to rival midsized ASICs. Then, circa 2001, FPGA vendors improved the performance of their devices to compete with midsized ASICs. Though FPGAs still consume much more power than ASICs of comparable densities and performance, last year, FPGA vendors made great strides to stabilize the amount of power that FPGAs consume. "The Yin and Yang of Software Development" http://www.acmqueue.com/modules.php?name=Content&pa=printer_friendly&pid=492&page=1 The C/C++ Solution Manager at Parasoft explains how infrastructure elements allow development teams to increase productivity without restricting creativity. "API: Design Matters" http://www.acmqueue.com/modules.php?name=Content&pa=printer_friendly&pid=488&page=1 Why changing APIs might become a criminal offense - Should the authors of lousy APIs be held accountable for their crimes? "Multicores, software tools, languages and the Charge of the Light Brigade" http://www.embedded.com/design/201800330;jsessionid=SIEOYFHKTSJHWQSNDLRSKH0CJUNN2JVN This article covers design challenges specifically faced by embedded systems developers working on multicore and multiprocessor systems found in network routers and switches and wireless base stations, in portable media devices, in servers and desktop computers as well as mobile phones. "Nanotechnology News" http://www.azonano.com/news.asp?newsID=4744 Report Examines The Impact of Nanotechnology on Energy and Environmental Technologies "Your Car -- Not Just for Transportation Anymore" http://www.chipdesignmag.com/display.php?articleId=1300 The automotive and transportation electronics world has always been different from the rest of the electronics industry. The sector has long been defined by a higher degree of reliability and a distributed processing environment. Recent enhancements to the automotive marketplace include widespread adoption of in-vehicle electronic systems, from the engine and driving controls to safety, display, and convenience features, such as entertainment. To meet the requirements of all these functions, automotive systems have grown from a single, central engine controller to more than 100 distributed controllers and processors on some high-end vehicles. "Training Doctoral Students for Academic Careers in Engineering" http://www.todaysengineer.org/2007/Aug/ffp.asp n the Fall of 2006, the University of Maryland.s A. James Clark School of Engineering launched its Future Faculty Program (FFP). The FFP has two goals: (1) to increase the number of Ph.D. graduates who obtain academic positions, especially at prominent research universities; (2) to improve the preparation of students for academic careers so that they can better succeed once they obtain such a position. "Global Chip Plant Usage Inching Upward" http://www.informationweek.com/hardware/showArticle.jhtml?articleID=201800458&subSection=Hardware The utilisation rate of semiconductor plants worldwide inched up for the second straight quarter in April-June on demand for cutting-edge memory chips and microprocessors used in lighter, thinner or smaller electronics. The utilisation rate was 89.7 percent in the quarter, up from 87.5 percent in January-March, the Semiconductor International Capacity Statistics (SICAS) group said on Thursday. "Researchers Create Environmentally Safe, Paper-Like Battery" http://www.informationweek.com/hardware/showArticle.jhtml?articleID=201800310&subSection=Hardware Researchers at Rensselaer Polytechnic Institute have created a paper-sized device that functions as a high-energy battery and a supercapacitor that can use human blood and sweat to recharge. This week, RPI announced the development of a nano-engineered battery that looks like a small sheet of black paper. Researchers published the details of the project in a report entitled, "Flexible Energy Storage Devices Based on Nanocomposite Paper" for the Aug. 13 issue of Proceedings of the National Academy of Sciences. "PCB Market to Reach $50 Billion, Says Researcher" http://eetimes.com/news/design/showArticle.jhtml?articleID=201309872 The market for printed circuit boards (PCBs) will be $50 billion in 2007 and rise to more than $76 billion in 2012, according to Visant Strategies a New York based market research company. "UK Starts Plastic Electronics Research Center" http://eetimes.com/news/design/showArticle.jhtml?articleID=201400058 Cenamps, a national centre for nanotechnology in the U.K., has hosted a groundbreaking ceremony for PETeC, a $20 million plastics electronics technology research center at Sedgefield, near Durham, England. "Virtualization: Key to Linux or Linux killer?" http://eetimes.com/news/design/showArticle.jhtml?articleID=201500042 Linux and virtual machines already work together closely, but more needs to be done in virtualization to drive even greater adoption of Linux on PCs and in data centers. Dell CTO Kevin Kettler, speaking at the LinuxWorld conference in San Francisco, said virtualization must become easier to use. Dell researchers are working on embedding a hypervisor, the program that provides a VM environment, in a server flash drive. "The overall benefit is time to boot--ready to go--and the management of these servers," Kettler said. "Inventor Forges Fresh Approach to Writing Software" http://eetimes.com/news/design/showArticle.jhtml?articleID=201800428 A lone inventor claims he has created a new approach to software development, called the Coherent Object Software Architecture that could make it easier to write parallel programs for multicore processors and bring a new level of discipline to the writing code. "NAND to Scale for Several Years" http://eetimes.com/news/design/showArticle.jhtml?articleID=201800776 NAND flash is projected to scale at least for another five or so years, pushing out the need for next-generation or universal memory technologies, according to an executive from Micron Technology Inc. Today, NAND flash-memory vendors are talking about developing sub-50-nm devices. In the future, NAND is expected to scale at least to the sub-20-nm range, said Frankie Roohparvar, vice president of NAND development at Micron (Boise, Idaho). Micron is involved in a NAND venture with Intel Corp., dubbed IM Flash Technologies LLC. "Litho Remains Roadblock for NAND" http://eetimes.com/news/design/showArticle.jhtml?articleID=201801015 What's the biggest roadblock for NAND scaling? One of the ongoing hurdles is lithography, said Frankie Roohparvar, vice president of NAND development at Micron Technology Inc. (Boise, Idaho). Micron is involved in a NAND venture with Intel Corp., dubbed IM Flash Technologies LLC. "Viewpoint: Routing Is Key To Implementing DFM Within The Design Flow" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201202910 As the Semiconductor industry continues to march down the road to ever smaller geometries, one has to question at what point the current design methodologies and paradigms will break. Or maybe, more to the point, when does the SoC designer really have to worry about design for manufacturing (DFM). "Organic Solar Cells Gain Ground" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201202360 A new composite material for plastic solar cells, formulated at Ohio State University, offers what researchers there claim is the best bet yet for beating the relatively high cost of grid-supplied electricity. Building on the best aspects of previous attempts to construct organic dye-sensitized solar cells, these researchers promise to best today's inorganic silicon-based solar cells, and beat the cost of traditional electricity generation sources in just a few years. "Chip Makers, Researchers Dish On Hottest Chips, Interconnects" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201202373 The Hot Chips and companion Hot Interconnects conferences provide a peek inside the leading multicore processors as well as research into the on- and off-chip networks that those future microprocessors may use. Hot Chips, Aug. 19-21 at Stanford University, provides an in-depth look into existing multicore CPUs such as IBM's Power6 and the latest graphics processors from Advanced Micro Devices and NVidia. In a rare new disclosure, startup Tilera Corp., founded by MIT professor Anant Agarwal, is expected to unveil its multicore processor for embedded systems. "Analyzing Dynamic Voltage Drop At 90 Nm And Beyond" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201201433 As VLSI technology scales to 90 nanometers and beyond, ASIC vendors increasingly see power grid integrity issues in their designs and in the field, for two primary reasons. First, deep-submicron geometries require lower power supply voltages, which reduce the chip's tolerance of noise (noise margin). Second, smaller geometries result in many more transistors per die. "Self-Assembly Extends To 10 Nanometers" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201300294 How to extend design features below the 10-nanometer node--which is off-the-scale beyond 2020 on the International Technology Roadmap for Semiconductors (ITRS)--was demonstrated recently by University of Alberta (Canada) researchers. "300-Mm Fab Capacity To Double" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201301688 SAN JOSE, Calif. - Despite the declines experienced by memory vendors, chip makers continue to invest in additional 300-mm fab capacity, according to SEMI. In total, worldwide 300-mm capacity will double from the beginning of 2007 to the end of 2008, as 25 new 300-mm high-volume fabs come online, according to the trade group. By the end of 2008, some 73 300-mm fabs will provide over 6.2 million wafers per month. "802.11n Face Off Favors Metalink" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201400114 In a test of four IEEE 802.11n end-user systems, a system design based on Metalink's WLANPlus chipset swept the field, delivering between 29 and 50 Mb/s data rates when operating in the 5-GHz band and 57 to 62 Mb/s in the 2.4-GHz band. Testing was conducted by The Tolly Group and sponsored by Metalink. Results were gathered from five points in a large home (6,000 sq ft) with normal residential environmental conditions such as walls and appliances. "Ten-Minute Cancer Screening Possible" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201500171 A new in-office test for oral cancer that takes only 10 minutes will soon be available using lab-on-a-chip microfluidic electronics, according to scientists supported by the National Institutes of Health. Billed as the world's first fully automated, all-in-one test, the lab-on-a-chip electronic reader, which is about half the size of a toaster, can scan cells brushed from the inside of the mouth with a swab. "Intel Readies Research Papers On Programmable Multicore Architectures" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201800194 Intel on Tuesday said it would release this week eight technical papers describing key findings from the company's work on future programmable multicore architectures. The papers will be published in the Intel Technical Journal and will provide details on how the company expects future microprocessors with simplified parallel programming models to evolve. With the commodity server market moving quickly toward increasingly more powerful multicore processors, new tools are needed to help programmers develop software that can take full advantage of the platforms. "Ionic Winds Can Cool Chips" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201800306 Just as ionic rain can irrigate a forest of nanotubes, ionic winds can cool the surface of chips. Harnessing ionic winds to accelerate charged air between high-voltage electrodes can enhance a chip's heat-transfer coefficient by 250 percent, according to Purdue University (West Lafayette, Ind.). Its chip-sized ionic wind engine prototype, funded by Intel Corp., works by overcoming the "no-slip" effect that ordinarily keeps the air molecules nearest the chip surface relatively stationary. "Bringing Silicon Contours Into The Designer's World" http://www.elecdesign.com/Articles/Index.cfm?AD=1&ArticleID=16304 In a fashion that defies logic, "design" for manufacturing actually got its start in the manufacturing realm. Several years and silicon generations ago, semiconductor manufacturing engineers figured out that the drawn ideal shapes in a designer's layout have sharp, crisp edges and those structures are going to change into rounded shapes (contours) when printed on silicon. "Nonvolatile Memory IP Now Available For 90-nm Processes" http://www.elecdesign.com/Articles/ArticleID/16338/16338.html Kilopass Technology's XPM (Extra Permanent Memory) IP products are now available for advanced 90-nm general-purpose and low-power designs. With the availability of the XPM-90G and XPM-90LP families for 90-nm designs, Kilopass is among the first memory IP suppliers to announce availability of a high-density nonvolatile memory (NVM) technology on both general-purpose and low-power 90-nm geometries. "SoC/ASIC Prototyping System Targets Designs Up To 9 Mgates" http://elecdesign.com/Articles/Index.cfm?AD=1&ArticleID=15919 Designed to debug and verify system-on-a-chip (SoC) designs of diverse styles up to 9 million ASIC gates in size, GiDEL's PROC9M prototyping system operates at system clock speeds up to 300 MHz. Each system includes an enclosed card cage for one to three of GiDEL's recon- figurable PROC3M FPGA boards, rated at 3 million ASIC gates. Each board has a pair of interconnected, high-speed Altera Stratix II EP2S180 FPGAs and 256 Mbytes of onboard DRAM or 768 Mbytes for each full PROC9M module. ============================================================================== Call For Participations ------------------------------- International Symposium on Low Power Electronics and Design 2007 August 27-29 2007 Portland, Oregon, USA Embassy Suites Portland Downtown Conference website: http://www.islped.org/ Advance Program: http://www.islped.org/Program07.pdf Conference registration: http://www.regonline.com/Checkin.asp?EventId=136073 The hotel registration deadline: August 3, 2007 The symposium registration deadline: August 3, 2007 (after that the registration can be done only at on-site rate) Outline of the ISLPED 2007 Advance Program ------------------------------------------------------------------------------- Day 1 . Monday August 27, 2007 8:15 . 8:30 am . Opening Address General Chairs: Diana Marculescu (CMU) and Anand Raghunathan (NEC) Program Chairs: Ali Keshavarzi (Intel) and Vijay Narayanan (PSU) 8:30 . 9:30 am . Keynote by Robert Chau - Fellow . Intel Keynote: Nanotechnology for Low-Power and High-Speed Nanoelectronics Applications 9:45 . 11:45 am TRACK 1: Session 1 - Emerging device technologies for low power 9:45 . 11:45 am TRACK 2: Session 2 - Power-Efficient CMP Design 1:15 . 3:15 pm TRACK 1: Session 3 - Low-power Techniques for Logic, Clock Distribution, and Interconnect 1:15 . 3:15 pm TRACK 2: Session 4 - Power Considerations at the physical level 5:00 . 6:30 pm TRACK 1: Session 5 - Software and System Power Optimization 5:00 . 6:30 pm TRACK 2: Session 6 - Leakage-Aware Architectural Synthesis* ------------------------------------------------------------------------------- Day 2 . Tuesday August 28, 2007 8:15 . 10:15 am TRACK 1: Session 7 - Low-Power Memory Design and NBTI Detection 8:15 . 10:15 am TRACK 2: Session 8 - DVS and thermal management 10:30 . 11:30 am . Plenary 1 by Prof. David Patterson . UC Berkeley Plenary 1: The Parallel Computing Landscape: A Berkeley View 1:00 . 3:00 pm TRACK 1: Session 9 - Signal Processing, Wireless, and Communication 1:00 . 3:00 pm TRACK 2: Session 10 - Architectural Power Optimization 3:15 . 4:30 pm . Embedded Tutorials 4:30 . 5:30 pm . Design Contest and Industry Sessions 7:00 . 9:00 pm . Dinner and Banquet Willamette River Cruse and Dinner ------------------------------------------------------------------------------- Day 3 . Wednesday August 29, 2007 8:00 . 10:00 am TRACK 1: Session 11 - DC/DC Converters 8:00 . 10:00 am TRACK 2: Session 12 - Energy and Power Delivery 10:15 . 11:15 am . Plenary 2 by Luiz Barroso . Distinguished Engineer - Google Plenary 2: All Watts Considered 11:15 . 12:45 pm . Poster Session 12:45 - 1:00 pm . Conference closing session ============================================================================== Submission deadlines: --------------------- DATE'08 - Design Automation and Test in Europe (sponsored by SIGDA) Munich, Germany Mar 10-14, 2008 Deadline: Sep 9, 2007 http://www.date-conference.com/ ISSCC'08 - Int'l Solid-State Circuits Conference San Francisco, CA Feb 3-7, 2008 Deadline: Sep 17, 2007 http://isscc.org/isscc/ IP-SOC'07 - IP Based SoC Design Grenoble, France Dec 5-6, 2007 Deadline: Sep 25, 2007 http://www.us.design-reuse.com/ipsoc2006/ ISQED'08 - Int'l Symposium on Quality Electronic San Jose, CA Mar 17-19, 2008 Deadline: Sep 30, 2007 http://www.isqed.org/ ISCAS'08 - Int'l Symposium on Circuits and Systems Seattle, WA May 18-21, 2008 Deadline: Oct 5, 2007 http://iscas2008.org/ ISPD'08 - Int'l Symposium on Physical Design (sponsored by SIGDA) Portland, OR Apr 13-16, 2008 Deadline: Oct 7, 2007 http://www.ispd.cc/ RAW'08 - Reconfigurable Architectures Workshop Miami, FL Apr 14-15, 2008 Deadline: Oct 8, 2007 http://www.ece.lsu.edu/vaidy/raw/ ASYNC'08: Int'l Symposium on Asynchronous Circuits and Systems Newcastle upon Tyne, UK Apr 7-11, 2008 Deadline: Oct 15, 2007 http://async.org.uk/async2008/ SPL'08 - Southern Conference on Programmable Logic Bariloche-Patagonia, Argentina Mar 26-28, 2008 Deadline: Nov 1, 2007 http://www.splconf.org/ DAC'08 - Design Automation Conference (sponsored by SIGDA) Anaheim, CA Jun 9-13, 2008 Deadline: Nov 19, 2007 http://www.dac.com/ ============================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- ISLPED'07 - Int'l Symposium on Low Power Electronics and Design Portland, OR Aug 27-29, 2007 http://www.islped.org/ FPL'07 - Int'l Conference on Field-Programmable Logic and Applications Amsterdam, Holland Aug 27-29, 2007 http://www.fpl.uni-kl.de/fpl/ DSD'07 - Euromicro Conference on Digital System Design Lubeck, Germany Aug 29-31, 2007 http://www.dsdconf.org/ PATMOS'07 - Power and Timing Modeling, Opt. & Sim. Goteborg, Sweden Sep 3-5, 2007 http://www.ce.chalmers.se/research/conference/patmos07/ SBCCI'07 - Symposium on Integrated and Systems Design (sponsored by SIGDA) Rio de Janeiro, Brazil Sep 3-6, 2007 http://www.sbcci.pads.ufrj.br/sbcci/index_sbcci.html PACT'07 - Int'l Conference on Parallel Architectures and Compilation Techniques Brasov, Romania Sep 15-19, 2007 http://www.pactconf.org/ CICC'07 - Custom Integrated Circuits Conference San Jose, CA Sep 16-19, 2007 http://www.ieee-cicc.org/ CODES+ISSS'07 - Int'l Conference on Hardware-Software Codesign and System Synthesis (sponsored by SIGDA) Salzburg, Austria sep 30-Oct 5, 2007 http://www.codes-isss.org/ VLSI-SoC'07 - Int'l Conference on Very Large Scale Integration Atlanta, GA Oct 15-17, 2007 http://www.vlsisoc2007.gatech.edu/ ICCAD'07 - Int'l Conference on Computer-Aided Design (sponsored by SIGDA) San Jose, CA Nov 4-8, 2007 http://www.iccad.com/ PDCS'07 - Int'l Conference on Parallel and Distributed Computing Systems Cambridge, MA Nov 19-21, 2007 http://www.iasted.org/conferences/home-590.html ICST'07 - Int'l Conference on Sensing Technology Palmerston North, New Zealand Nov 26-28, 2007 http://icst.massey.ac.nz/ BIOCAS'07 - Biomedical Circuits and Systems Conference London, UK Nov 27-30, 2007 http://biocas.grm.polymtl.ca/ MICRO'07 - Int'l Symposium on Microarchitecture Chicago, IL Dec 1-5, 2007 http://www.microarch.org/micro40/ ICPADS'07 - Int'l Conference on Parallel and Distributed Systems Hsinchu, Taiwan Dec 5-7, 2007 http://www.ccrc.nthu.edu.tw/icpads2007/ ICFPT'07 - Int'l Conference on Field-Programmable Technology Kitakyushu, Japan Dec 12-14, 2007 http://www.kameyama.ecei.tohoku.ac.jp/icfpt07/ EUC'07 - Int'l Conference on Embedded and Ubiquitous Computing Taipei, Taiwan Dec 17-20, 2007 http://www.cs.ccu.edu.tw/~shiwulo/euc07/ HiPC'07 - Int'l Conference on High Performance Computing Goa, India Dec 18-21, 2007 http://www.hipc.org/ ICM'07 - Int'l Conference on Microelectronics Cairo, Egypt Dec 29-31, 2007 http://www.ieee-icm.com/ VLSI'08 - Int'l Conference on VLSI Design (sponsored by SIGDA) ES'08 - Int'l Conference on Embedded Systems Hyderabad, India Jan 4-8, 2008 http://vlsiconference.com/vlsi2008/ ASP-DAC'08 - Asia and South Pacific Design Automation Conference (sponsored by SIGDA) Seoul, Korea Jan 21-24, 2008 http://www.aspdac.com/aspdac2008/ HiPEAC'08: Int'l Conference on High Performance Embedded Architectures & Compilers Goteborg, Sweden Jan 27-29, 2008 http://www.hipeac.net/hipeac2008/ ============================================================================== Upcoming Funding Opportunities -------------------------------- ASEE Naval Research Laboratory (NRL) Postdoctoral Fellowship Program Deadline: Continuous. Applications are accepted on an ongoing basis. http://www.asee.org/resources/fellowships/nrl/index.cfm AAWU International Fellowships Deadline: December 1, 2007 http://www.aauw.org/fga/fellowships_grants/international.cfm ACM Doctoral Dissertation Award Deadline: August 31, 2007 http://fundingopps.cos.com/alerts/33218?id=33218&if=alert NIH NLM Knowledge Management & Applied Informatics Grants Deadline: May 25, 2007 September 25, 2007 January 25, 2008 http://grants1.nih.gov/grants/guide/pa-files/PAR-07-236.html Continued Development and Maintenance of Software (R01) Deadline: May 17, 2007 September 13, 2007 http://grants1.nih.gov/grants/guide/pa-files/PAR-07-235.html NASA Applied Information Systems Research - NNH07ZDA001N-AISR Deadline: To be announced (TBA) http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId=%7B89FBF877-DD5F-AC6E-DAB3-AE19504EA70D%7D&path=open DOD Brain Network Analysis and Modeling for Communication and Orientation - BAA-07-036 Deadline: October 23, 2007 http://www.grants.gov/search/search.do?oppId=14530&mode=VIEW 21st Century Approach to Electronic Device Reliability - BAA-07-036 Deadline: October 23, 2007 http://www.grants.gov/search/search.do?oppId=14530&mode=VIEW Microsystems Technology Office-Wide BAA Deadline: January 14, 2008 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07%2D18/SynopsisP.html ASEE-NRL Postdoctoral Fellowship Program Deadline: Continuous http://hroffice.nrl.navy.mil/jobs/postdoc.htm Cognitive Technology Threat Warning System (CT2WS) Deadline: April 11, 2008 http://fedbizopps.cos.com/cgi-bin/getRec?id=20070412a1 Warrior Systems Technologies - Body-Worn Systems, Hand Held Devices, and Smart-Lightweight Electronic Components/Modules for Soldier Protection, Knowledge Management and Cognitive Improvement Deadline: Continuous. (April 1, 2007 ~ March 31, 2009) https://www3.natick.army.mil/ssbaa.htm Homeland Security (2.2.1) - N61339-02-R-0071 Deadline: Continuous. This BAA expires on January 30, 2008 http://www1.fbo.gov/spg/DON/NAVAIR/N61339/N61339-02-R-0071/Attachments.html Microsystems Technology Office-Wide Deadline: January 14, 2009 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07-18/Attachments.html SPINS in Semiconductors Deadline: December 31, 2008 http://fundingopps.cos.com/alerts/57993 Artificial Intelligence Technologies Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/baa.htm Quantum Information Science and Technology Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Young Investigator Program (YIP) January 12, 2008 http://www.onr.navy.mil/sci_tech/3t/corporate/yip.asp High Density Optical Memory Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Quantum Electronic Solids Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Distributed Intelligence Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF Information and Intelligent Systems: Advancing Human-Centered Computing, Information Integration and Informatics, and Robust Intelligence - NSF 07-577 Deadline: October 23, 2007 for Medium Projects November 19, 2007 for Large Projects December 10, 2007 for Small Projects http://www.nsf.gov/pubs/2007/nsf07577/nsf07577.htm Strategic Technologies for Cyberinfrastructure (STCI) Deadline : August 9, 2007 February 14, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=500066&org=NSF&sel_org=NSF&from=fund Engineering Design (ED) Deadline : October 1, 2007 February 15, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13340 Operations Research (OR) Deadline : October 1, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13341&org=NSF&from=fund Instrument Development for Biological Research (IDBR) Deadline: September 12, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=9187&org=NSF&from=home Cyberinfrastructure Training, Education, Advancement, and Mentoring for Our 21st Century Workforce (CI-TEAM) - NSF 07-564 Deadline: August 27, 2007 http://www.nsf.gov/pubs/2007/nsf07564/nsf07564.htm Sloan Foundation Sloan Research Fellowships Deadline: September 15, 2007 http://www.sloan.org/programs/scitech_fellowships.shtml Soroptimist International of the Americas, Inc. Women's Opportunity Awards Deadline: December 1, 2007 http://www.soroptimist.org/sia/AM/Template.cfm?Section=WOMEN_S_OPPORTUNITY_AWARDS ============================================================================== Call For Papers ----------------- Second Annual Reconfigurable and Adaptive Architecture Workshop (RAAW-2) http://www.comparch.binghamton.edu/raaw/ To be held in conjunction with the The 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2007 Chicago, Illinois, USA Workshop Theme -------------- The tremendous advances in process technology provide architects and microarchitects with many interesting opportunities for making use of the huge transistor budget to enhance performance and increase throughput. However, the complexity of software applications and system software presents a challenging problem. The varying requirements of the different applications running on a single machine, as well as the changing behavior of a single application during its lifetime, make choosing a suitable general purpose architecture a big challenge. This raises the need for an architecture that can adapt to the different requirements of the applications. The power consumption limits and the growing importance of reliability further add to the appeal of such adaptive architectures. The Reconfigurable and Adaptive Architecture Workshop provides a high-quality forum for computer scientists and engineers to present their latest research findings in the rapidly evolving field of reconfigurable and adaptive architectures. Submission Topics ----------------- Topics of interest include, but are not limited to: * High performance adaptive and reconfigurable architectures * Power-Aware and Thermal-Aware architectures * Adaptive architectures for enhanced hardware reliability * Compilation techniques for adaptive and reconfigurable architectures * Dynamic compilation and runtime execution environments * Heterogeneous multiprocessing on a chip * Reconfigurable interconnection * Hardware/software trade-offs * Novel architectures and micro-architectures * Reconfigurable embedded computing systems * Memory management techniques * Static and dynamic profiling techniques * Program phase detection and exploitation techniques * Hardware acceleration through reconfiguration * Integration of FPGAs with microprocessors Submission Guidelines --------------------- The Program Committee invites authors to submit papers up to 5000 words in length, describing original, unpublished recent work related to the workshop theme. Submission must be in pdf format and emailed to raaw@binghamton.edu. The submission should include the contact person's email address on the front page. The selected papers will be considered for publication in a special theme issue of JILP. At least one of the author(s) of an accepted paper is expected to register for the workshop and present the paper. Important Deadlines ------------------- Paper Submission: September 18, 2007 Acceptance Notification: October 26, 2007 Final version of papers: November 12, 2007 Organizers ----------- Aneesh Aggarwal Electrical and Computer Engineering SUNY Binghamton Pradip Bose IBM T. J. Watson Research Center Mohamed Zahran Electrical Engineering City University of New York Program Committee ----------------- Bryan Black (AMD) Alper Buyuktosunoglu (IBM) Joel Emer (Intel) Onur Mutlu (Microsoft) Eric Rotenberg (NCSU) Rajiv Gupta (UCR) Scott Mahlke (UMich) Amir Roth (UPenn) Contact Us at raaw@binghamton.edu ============================================================================== Call For Papers ---------------- ACM Journal on Emerging Technologies in Computing Systems Special Issue on Three-dimensional Integrated Circuits and Microarchitectures DEADLINE 11/15/2007 We are pleased to announce a call for papers for a special issue of ACM Journal on Emerging Technologies in Computing Systems on 3D ICs and Microarchitectures. The submission may be based on works that were previously published in refereed conferences, however, the submission should contain at least 30% new material, and the authors should state clearly how the submission differs from and/or expands on the workshop or conference paper. Please submit your paper to http://mc.manuscriptcentral.com/acm in the JETC section. Please specify "SPECIAL ISSUE ON 3D ICs and Microarchitectures" on your cover page and in the notes section of the Web site submission form. Important Dates Submission Deadline: 11/15/07 Acceptance Notice: 3/30/08 Final Manuscript Due: 5/31/08 Guest Editors Yuan Xie Pennsylvania State University yuanxie@cse.psu.edu Jason Cong University of California at Los Angeles cong@cs.ucla.edu Paul D. Franzon North Carolina State University paulf@ncsu.edu ============================================================================== Call For Papers ------------------ Special Issue on Demonstrable Software Systems and Hardware Platforms II DEADLINE EXTENDED TO 8/27/2007 We are pleased to announce a call for papers for a second special issue of ACM TODAES on Demonstrable Software Systems and Hardware Platforms. We are interested in research efforts that are dedicated to prototype experimental software systems and/or hardware platforms. Papers should demonstrate how these systems advance the fundamental science of electronic design automation (EDA) and/or offer a significant innovation in their application. Examples of relevant projects might include a system level design tool for improved thermal management, a radiation simulator for testing reconfigurable devices, an optical proximity correction tool for < 65 nm processes, etc. Practical aspects of the software tool or hardware platform development should be accompanied by new and substantive algorithmic and/or theoretic results. Submissions are encouraged from technical papers that describe the works presented at the SIGDA/DAC University Booth in San Diego, 2007. The submission may be based on works that were previously published in refereed conferences such as DAC or ICCAD, however submissions of expanded manuscripts based on the technical papers and Student Design Contest papers at DAC 2007 are especially encouraged. If the submission is an expanded version of a workshop/conference paper, it should contain at least 30% new material, and the authors should state clearly how the submission differs from and/or expands on the workshop/conference paper. Please submit your paper to http://mc.manuscriptcentral.com/acm in the TODAES section. Also, please write "SPECIAL ISSUE ON DEMONSTRABLE SOFTWARE SYSTEMS AND HARDWARE PLATFORMS II" on your cover page and in the notes section of the Web site submission form. We expect a shorter turnaround time for this special issue. About the SIGDA/DAC University Booth: The SIGDA/DAC University Booth provides an opportunity for the university community to demonstrate new EDA tools, design projects, and instructional materials at the Design Automation Conference. The University Booth also provides space for the presentation of EDA vendor literature and programs of interest to the university community. Student participants in the University Booth are typically provided with travel grants to defray the cost of attending the Design Automation Conference. In 2006, the booth had nearly 50 demonstrations from all over the United States, Canada, Brazil, Japan, Korea, France, Singapore, and Taiwan. In honor of our 20th anniversary in 2007 the booth was redesigned thanks to sponsorship by Mentor Graphics, Inc. Important Dates Extended Deadline: 8/27/07 Acceptance Notice: 2/04/08 Final Manuscript Due: 3/31/08 Guest Editors Alex K. Jones Univ. of Pittsburgh Pittsburgh, PA USA akjones@ece.pitt.edu Robert A. Walker Kent State Univ. Kent, OH USA walker@cs.kent.edu A PDF version of this announcement can be found at: http://www.sigda.org/programs/Ubooth/Ubooth2007/todaes_cfp.pdf ============================================================================== Call For Nominations ------------------------ 2007 ACM Outstanding Ph.D. Dissertation Award in EDA http://www.sigda.org/opda.html Submission Deadline: September 15, 2007 (postmarked) Award Description: Design automation has gained widespread acceptance by the VLSI circuits and systems design community. Advancement in computer- aided design (CAD) methodologies, algorithms, and tools has become increasingly important to cope with the rapidly growing design complexity, higher performance and low-power requirements, and shorter time-to-market demands. To encourage innovative, ground- breaking research in the area of electronic design automation, the ACM's Special Interest Group on Design Automation (SIGDA) has established an ACM award to be given each year to an outstanding Ph.D. dissertation that makes the most substantial contribution to the theory and/or application in the field of electronic design automation. The award consists of a certificate and a check for $1,000 and is presented at the Design Automation Conference, which is held in June/July of each year. The award is selected by a committee of experts from academia and industry in the field and appointed by ACM in consultation with the SIGDA Chair. Nomination Requirements and Procedure: * Each department of any university may nominate at most one Ph.D. dissertation whose final submission date is between July 1, 2006 and June 30, 2007. * Each nomination package must be postmarked by September 15 and should consist of: 1. Five copies of the dissertation, plus the PDF file of the dissertation sent via email. 2. A statement from the nominee, up to two pages in length, which explains the significance and major contributions of the work. 3. A nomination letter from nominee's department chair or dean of the school endorsing the application. 4. Up to three additional letters of recommendation from experts in the field. These letters may be included in the package or sent separately to the address below. Item 1 must be submitted in (preferably bound) hard copy form. Other items may be submitted as paper printouts or electronically. All the nomination materials should be mailed to: Prof. Radu Marculescu Attn: ACM Outstanding Ph.D. Dissertation Award in EDA Carnegie Mellon University Department of Electrical & Computer Engineering 5000 Forbes Ave. Pittsburgh, PA 15213-3890 Tel: (412) 268-8710 Fax: (412) 268-3204 Email: radum@ece.cmu.edu ============================================================================== Call For Papers ------------------------------ 14th IEEE International Symposium on Asynchronous Circuits and Systems 7th - 11th April 2008 Newcastle upon Tyne, UK The International Symposium on Asynchronous Circuits and Systems provides a high-quality forum for scientists and engineers to present their latest research findings. Authors are invited to submit full papers on all aspects of asynchronous design. Topics of interest include, but are not limited to: * Mixed synchronous/asynchronous architectures, interfaces, and circuits. * Design, synthesis and Verification techniques for GALS systems. * Synchronous-asynchronous interaction at different levels. * High-speed/low-power asynchronous logic, memories, and interconnects. * High-level design and synthesis of self-timed circuits. * Physical design of unclocked logic and pipelines. * Formal methods for correctness and performance analysis of asynchronous designs. * Test, reliability, security, and radiation tolerance. * CAD for asynchronous design and validation. * Asynchronous System-on-Chip (SoC), System-in-Package (SiP). * Novel asynchronous architectures. * Asynchrony and latency tolerance in system-level design. * Motivating case studies, comparisons, and applications. * Embedded System Design with asynchronous architectures/implementations. * Asynchronous design for manufacturing. Papers must be submitted via the conference web site. Papers will be evaluated by the program committee and reviews will be based on scientific merit, innovation, relevance, and presentation. New idea papers are encouraged, and the program committee recognizes that such papers may contain less evaluation than papers in established areas. Accepted papers will be published in an IEEE proceedings and distributed at the symposium. Please check the symposium website for up-to-date information: http://async.org.uk/async2008/ Important dates: Submission information: * Abstract registration: October 8, 2007 * Full paper submission: October 15, 2007 Notification of acceptance: December 12, 2007 Final version due: January 18, 2008 Paper format: Abstract of up to 150 words, 10 pages or fewer, including figures and bibliography, single spaced, 10pt or larger font size, IEEE double-column conference format. ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ============================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To manage your subscription, go to "Subscriber's corner" on http://listserv.acm.org/ - you need to login using the email address where this newsletter is delivered. First time users will be required to choose a password.) ==============================================================================