=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membersip. Circulation: 2,700 =============================================================================== 15 July 2007 ACM/SIGDA E-NEWSLETTER Vol. 37, No. 14 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel (2) Call For Nominations : 2007 ACM Outstanding Ph.D. Dissertation Award in EDA From: Radu Marculescu (3) 44th DAC Best Paper Honors From: DAC Press Release (4) Paper Submission Deadlines From: Hai Zhou (5) Upcoming Conferences and Symposia From: Hai Zhou (6) Upcoming Funding Opportunities From: Qinru Qiu (7) Call For Participations : HOT Chips 19 From: Alan Smith (8) Call for Papers : ASYNC 2008 From: Stephen A. Edwards =============================================================================== Dear ACM/SIGDA members, The "What is ..." column will continue in Fall of 2007. In this issue, we have included the "Call For Nominations for 2007 ACM Outstanding Ph.D. Dissertation Award in EDA". In addition, "SIGDA News" column contains a number of fresh headlines. We have also updated the contents of other regular columns. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Qing Wu, E-Newsletter Editor; Matthew Guthaus, E-Newsletter Associate Editor; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "'Expert' Reports on DATE, DAC Available to Public" http://eetimes.com/news/design/showArticle.jhtml?articleID=201000743 The "edacentrum," an independent organization that promotes research and development in electronic design automation, is making its reports available to the general public. The "edaTrend" 2007 conference reports cover this year' two leading EDA conferences: Design, Automation, and Test in Europe (DATE) Conference 2007, held in Nice, France, and the Design Automation Conference (DAC) 2007 held in San Diego, California. "IBM Researchers Develop Stable SRAM Operating at 6 GHz" http://embedded.com/showArticle.jhtml?articleID=201000835 At the VLSI Circuits Symposium held recently in Kyoto, Japan, IBM scientists revealed a prototype embedded SRAM chip set capable of reaching speeds beyond 6 GHz. Their accomplishment is nearly twice as fast as the SRAMs available today. "Semiconductor Chip Sales Grow by 2.4% to $20.3 Billion in May" http://edageek.com/2007/07/02/sia-may-2007/ Worldwide sales of semiconductors of $20.3 billion in May were 2.4 percent higher than the $19.8 billion reported for May of 2006, and 1.2 percent higher than the $20.0 billion reported for April 2007, the Semiconductor Industry Association (SIA) reported. "Is FPGA a Simpler Puzzle for ASIC Designers?" http://www.edn.com/index.asp?layout=article&articleid=CA6459058 Over the last 10 years, FPGA vendors have made great strides in overcoming the shortcomings of FPGAs and taking share from the ASIC market. In the late 1990s, FPGA vendors increased the capacity of their devices to rival midsized ASICs. Then, circa 2001, FPGA vendors improved the performance of their devices to compete with midsized ASICs. Though FPGAs still consume much more power than ASICs of comparable densities and performance, last year, FPGA vendors made great strides to stabilize the amount of power that FPGAs consume. "Double Digit Growth For the EDA Market Europe 2007" http://www10.edacafe.com/nbc/articles/view_article.php?section=CorpNews&articleid=406936 With a market sized at 780 million, up nearly 11% from the 700 million in 2005 (itself up 7% from 2004), the Electronic Design Automation market in Europe represents around one fifth of the worldwide EDA market. The European EDA market is dominated as is the global market by the so called Big Three: Cadence Design Systems, Mentor Graphics Inc and Synopsys, Inc. However, unlike its 3rd position in the worldwide ranking, Mentor Graphics is ranked 2nd in Europe in 2006, where it generates 28% of its worldwide business. "Researchers Call for More Funds, Easier Immigration" http://www.eetimes.com/showArticle.jhtml?articleID=201001733 The U.S. government needs to spend more money on long-term research and multi-disciplinary education and open its doors wider for international researchers. That was the conclusion of a panel of experts convened at a Microsoft Research event here Monday (July 16). Those conclusions will be spelled out in the report of a government task force to be published this summer. "Cadence Design Systems Acquires Invarium" http://edageek.com/2007/07/12/cadence-invarium/ Cadence Design Systems, Inc., the leader in global electronic-design innovation, announced that it has acquired Invarium, Inc., a San Jose-based developer of advanced lithography-modeling and pattern-synthesis technology. Invarium's pattern synthesis capabilities enable superior pattern resolution and faster yield ramp for designs targeted to 45-nanometer-and-below process technologies. This acquisition creates the path to the industry's leading DFM solution for functional and parametric yield improvement, enabling the prevention, detection, correction and optimization of manufacturing effects on advanced geometry designs. "PULLNANO Consortium Reveals 32nm, 22nm CMOS Results" http://edageek.com/2007/07/10/pullnano-32nm-22nm/ PULLNANO, a project sponsored by the European Commission within the 6th Framework Program (FP6), has reported several important results related to the future-generation 32nm and 22nm CMOS technology platforms, including the realization of a functional CMOS SRAM (Static Random Access Memory) demonstrator built using 32nm design rules. PULLNANO is a collective effort of 38 European partner organizations, including leading chip manufacturers, industry-orientated research institutions, universities and SMEs (Small and Medium Enterprises). The aim of PULLNANO is to develop advanced knowledge that will enable European chip manufacturers to maintain their strong presence in the worldwide microelectronics industry from 2010, when the 32nm generation of CMOS technology is expected to be commercially available. "Carbon Nanotube Transistors Get Faster" http://eetimes.com/news/design/showArticle.jhtml?articleID=200900208 A team of French researchers announced they have made transistors from carbon nanotubes on a silicon substrate. Scientists explained that these transistors, commonly used as automatic switches, can reach cutoff frequencies of 30 GHz. The previous record, reported by the same team in August 2006, has now been improved by a factor of 4. New prospects are opened up for mainstream applications that require high operating frequencies. "Floorplanning, RTL Synthesis Link Up for Chip-Level Interconnect" http://www.eetimes.com/news/design/showArticle.jhtml?articleID=200900266 Claiming a new "design with physical" approach that helps solve problems with chip-level interconnect, Cadence Design Systems this week plans to announce a new component of its Cadence Logic Design Team Solution. It integrates the Encounter RTL Compiler synthesis tool with the First Encounter floorplanning tool so that synthesis can get timing estimates from physical floorplanning data. "Running an FPGA at ASIC Speed" http://www.edn.com/article/CA6455605.html The hardware-emulation team at Texas Instruments is getting word about its next project: developing a prototype of the modem of a baseband-processor ASIC for next-generation wireless handsets. The prototype is necessary to help the software team test its code using real hardware as soon as possible, because the processor itself won't be ready for another 12 to 14 months. Getting this head start on software development is key to the product schedule, because the software effort represents most of the overall engineering effort. "Quest for Synthetic Organisms Calls for New Rules, Critics Say" http://www.wired.com/science/discoveries/news/2007/07/synthetic_bio When scientists recently announced that they'd successfully replaced the genome of one bacteria species with another, it was a key step forward for the emerging field of synthetic biology. The technique the J. Craig Venter Institute researchers used adds to the rapidly growing body of work by synthetic biologists who are designing genes and other cellular parts. They plan to custom-make microbes that can manufacture drugs, boost crops, clean up pollution and even generate fuel. "Intel to Lower Quad-Core Desktop Pricing" http://www.informationweek.com/news/showArticle.jhtml;jsessionid=25OMOGSTF1WPQQSNDLRSKH0CJUNN2JVN?articleID=201001672 Intel on Monday introduced a faster quad-core desktop processor that's less expensive than its previous top-end chip, an indication that a new round of price cuts are on the way as the chip giant looks to keep the price pressure on rival Advanced Micro Devices(AMD). "Intel, AMD Redesign MPUs for Faster Servers" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=200900641 The rapid adoption of virtualization is having a big impact on server design as server architects go back to the drawing boards to figure out how to build more virtualization-friendly features into their designs. "Virtualization has thrown us for a loop, quite honestly," said Shannon Poulin, Intel enterprise marketing manager, last month at an IDC conference on virtualization. Two years ago, less than 5% of the data center had been virtualized. By 2010, Intel projects that 25% of enterprise data center servers will be running in virtualization mode. Server design is trying to catch up with the trend, Poulin said. "Magnetic Doping Brightens OLEDs" http://www.eetimes.com/showArticle.jhtml?articleID=201001556 Efficiency is the name of the game for flat-panel display technologies. This is especially important for extending the battery life of cellphones, digital cameras, personal digital assistants and other portable devices that use organic LED displays. Now, Oak Ridge National Laboratory (ORNL) claims it can make OLEDs 30 percent more efficient by doping them with magnetic nanoparticles. As a bonus, the introduction of magnetism into the OLED material enables brightness to be controlled without the addition of electrical contacts. "New Nano Weapon Against Cancer" http://www.technologyreview.com/Nanotech/18999/ A new class of specially engineered nanoparticles that can target, image, and kill tumor cells could be a potent weapon against cancer. The new nanoengineered system, designed by physician and researcher James Baker and his colleagues at the University of Michigan, contains gold nanoparticles with branching polymers called dendrimers that sprout off the nanoparticle's surface. "Worldwide MEMS Systems Market Forecasted to Reach $72 Billion by 2011" http://www.azonano.com/news.asp?newsID=4479 The market for micro-electromechanical systems (MEMS), which includes products such as automobile airbag systems, display systems and inkjet cartridges totaled $40 billion in 2006, and is expected to top $72 billion by 2011, according to Global MEMS/Microsystems Markets and Opportunities, a comprehensive new market research report from SEMI and Yole Developpement. "Battery Powered All Electric Porsche To Hit The Road" http://www.azonano.com/news.asp?newsID=4467 In move bound to make Porsche purists gape, MIT students have been busy retrofitting a Porsche 914 to an all electric drive system. The electric Porsche proof of concept will be fitted with Valence batteries and is expected to have sound sports car performance. Although only having a range of around 100 miles before requiring a recharge of the batteries, this range is well withing the requirements of most motorists daily use. The application of nanotechnology to battery development is greatly increasing their efficiency and it can be expected that future generations of electric vehicles will have even more impressive performance. "Xilinx Rolls Out Integrated Software Environment WebPACK 9.2i" http://edageek.com/2007/07/10/xilinx-ise-webpack-92i/ Xilinx, Inc. announced immediate availability of Integrated Software Environment (ISE(TM)) WebPACK(TM) 9.2i -- he latest version of the company's free downloadable programmable logic design suite. The 9.2i version includes all the features and enhancements of Xilinx ISE Foundation(TM) 9.2i software with full support for optional embedded, digital signal processing (DSP) and real-time debug design flows. ISE WebPACK 9.2i software expands development options for FPGA designers with support for Microsoft Windows Vista. ISE WebPACK 9.2i is the only complete FPGA design suite offering a free, downloadable solution, with RTL simulation, for Microsoft Windows Vista as well as Microsoft Windows XP and Linux. "IEC, British Telecom Brainstorm on 21st Century Communications" http://edageek.com/2007/07/12/iec-bt/ The International Engineering Consortium (IEC) and Host Sponsor British Telecom (BT) led the industry last week in brainstorming educational content for the IEC's 21st Century Communications World Forum. Themed an "Innovation Imperative," the 21st Century Communications World Forum planning meeting took place with 75 leading telecommunications industry professionals. "Analog Devices, TSMC Team on 65nm Process for SoftFone Baseband Processor" http://edageek.com/2007/07/10/analog-devices-softfone-tsmc/ Analog Devices, Inc. and Taiwan Semiconductor Manufacturing Company, Ltd. announced a significant accomplishment in their longstanding relationship. With the application of TSMC's 65nm process technology to ADI's SoftFone(R) baseband processors, designs will benefit from lower cost and better power efficiency--important considerations for advanced multimedia applications in wireless handsets. "Under the Hood: Inside the Apple iPhone" http://eetimes.com/news/design/showArticle.jhtml?articleID=200001811 Semiconductor Insights' Allan Yogasingam waited in line for 12 hours and braved the elements get ahold of the just-released Apple iPhone. He and his intrepid co-workers kept the cameras rolling as they popped the cover and dove inside what is possibly the hottest consumer device on the planet (click icon for video:video icon). The teardown is a follow-up to the company's teardowns of the latest gaming systems (Opportunities abound in nex-gen gaming platforms) and provides insight into what exactly Apple is doing to make a strong entry into the cell phone market. Approximately 3 million iPhones were released in the United States at 6 pm local time on June 29th. The mass appeal and interest in the iPhone is a combination of Apple marketing, an interesting and interactive user interface, and the ability to integrate iTunes. "IPhone Code Trail Points to MBX Graphics Core" http://eetimes.com/news/design/showArticle.jhtml?articleID=200900740 Evidence had been building in recent days that the PowerVR MBX core from Imagination Technologies (Kings Langley, England) is providing the graphics processing in the Apple iphone. That would make for about five or six processor cores inside the iPhone all designed by U.K. companies but manufactured by others. Imagination has declined to confirm the design win although detective work by members of the Beyond 3D Forum has revealed references to MBX in Apple iPhone firmware. "SOS for Sinking Design Flow Methodology" http://eetimes.com/news/design/showArticle.jhtml?articleID=200900636 As we get down to 65-, 45- and 32-nanometer designs that are increasingly complex and harder to manufacture, we're assuredly going to run into design closure and manufacturability problems--to the extent that we'll effectively shut down chip design if we continue using our current design flows. These flows came into being in the 1980s, and we've been adding analysis and verification tools to them ever since, tweaking the design flow to fix problems. The result is a 20-plus-year-old design flow methodology that's burdened like an old boat encrusted with barnacles. This ship's going to sink. "Pause TV is Coming" http://eetimes.com/news/design/showArticle.jhtml?articleID=201000679 Get ready for Pause TV, a television receiver equipped with flash memory that lets TV viewers to pause for a fridge break or rewind in mid-broadcast for instant replays. A new TV prototype capable of pausing live TV broadcasts without the use of a hard disk drive is about to debut, according to industry sources, as early as next month at IFA, the world's largest consumer electronics trade show in Berlin. Commercial products are expected to reach the consumer market later this year or early 2008. "Walking Robot Offers Clues to Human Movement" http://eetimes.com/news/design/showArticle.jhtml?articleID=201001151 A walking robot that adapts to different terrain is helping scientists understand how humans move and could one day lead to improved treatment for spinal cord and other injuries, German researchers said on Friday. Previously, RunBot the robot's inventors said the 30-centimeter-tall machine could only walk forward on flat surfaces and would topple over when encountering a slope. "IEEE Meeting Advances Broadband Over Powerline Specs" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201001232 Broadband over powerline networking in the home came a step closer this week with major agreements concluded at the IEEE P1901 working group standardization effort that was held in Edinburgh, Scotland. All three clusters of the working group looking to standardize BPL Medium Access Control and Physical layer specifications - for access control, interoperability in the home, and coexistence - made important progress, according to Russell Haggar, VP of marketing at BPL chip developer SiConnect (Swindon, England). "MIT Spin-Off Tips Secret Behind Low-Power A/Ds" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=200001884 An MIT development called femtocharge technology is claimed to yield the coolest, lowest-power analog-to-digital (A/D) converters achieved to date, but until now the details have been a closely guarded secret. Now MIT spin-off Kenet Inc. (Woburn, Mass.) is revealing that instead of using power-hungry amplifiers between stages, the technique passes charge packets, such as charge-coupled devices (CCDs). "Panasonic Speeds Up Writing To Blu-Ray Discs" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=200900290 Panasonic on Tuesday introduced a write-once Blu-ray disc with a writing speed that's faster than other discs available today in the high-definition format. The consumer electronics company said the write-once disc has a 4x writing speed, versus 2x for most other Blu-ray discs. In addition, the single-sided disc is available in 25 Gbytes and 50 Gbytes. The latter version is dual layer, which means the disc doesn't have to be turned over while recording data. "Nantero, HP Explore Inkjet Printing of Nanotube Memory" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201000441 Nantero Inc. (Woburn, Mass.), a company developing a nonvolatile memory based on carbon nanotubes (CNTs), has said it is exploring flexible electronics applications with Hewlett Packard Co. (Palo Alto, Calif.). Nantero said it is working with HP to explore the use of HP inkjet technology and Nantero s carbon nanotube (CNT) formulation to create flexible electronics products and develop low-cost printable memory. "Jazz Semi to Fab Nanoradio's Radio IC" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=201001041 Nanoradio AB, the Swedish specialist developer of radio ICs targeted at the Wi-Fi and multimedia consumer electronics sectors, has chosen RF and analog foundry Jazz Semiconductor to make its parts on a 0.35-micron SiGe BiCMOS process. ============================================================================== Call For Nominations ------------------------ 2007 ACM Outstanding Ph.D. Dissertation Award in EDA http://www.sigda.org/opda.html Submission Deadline: September 15, 2007 (postmarked) Award Description: Design automation has gained widespread acceptance by the VLSI circuits and systems design community. Advancement in computer- aided design (CAD) methodologies, algorithms, and tools has become increasingly important to cope with the rapidly growing design complexity, higher performance and low-power requirements, and shorter time-to-market demands. To encourage innovative, ground- breaking research in the area of electronic design automation, the ACM's Special Interest Group on Design Automation (SIGDA) has established an ACM award to be given each year to an outstanding Ph.D. dissertation that makes the most substantial contribution to the theory and/or application in the field of electronic design automation. The award consists of a certificate and a check for $1,000 and is presented at the Design Automation Conference, which is held in June/July of each year. The award is selected by a committee of experts from academia and industry in the field and appointed by ACM in consultation with the SIGDA Chair. Nomination Requirements and Procedure: * Each department of any university may nominate at most one Ph.D. dissertation whose final submission date is between July 1, 2006 and June 30, 2007. * Each nomination package must be postmarked by September 15 and should consist of: 1. Five copies of the dissertation, plus the PDF file of the dissertation sent via email. 2. A statement from the nominee, up to two pages in length, which explains the significance and major contributions of the work. 3. A nomination letter from nominee's department chair or dean of the school endorsing the application. 4. Up to three additional letters of recommendation from experts in the field. These letters may be included in the package or sent separately to the address below. Item 1 must be submitted in (preferably bound) hard copy form. Other items may be submitted as paper printouts or electronically. All the nomination materials should be mailed to: Prof. Radu Marculescu Attn: ACM Outstanding Ph.D. Dissertation Award in EDA Carnegie Mellon University Department of Electrical & Computer Engineering 5000 Forbes Ave. Pittsburgh, PA 15213-3890 Tel: (412) 268-8710 Fax: (412) 268-3204 Email: radum@ece.cmu.edu ============================================================================== 44th DAC Best Paper Honors ------------------------------ SAN DIEGO, Calif. - June 19, 2007 - The 44th Design Automation Conference (DAC), awarded Best Paper honors to two noteworthy technical papers presented at this year's conference. "Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations," provides a breakthrough solution to a longstanding problem with timing closure. "Period Optimization for Hard Real-time Distributed Automotive Systems;" presents a new solution to the mapping problem for distributed automotive systems. The Best Paper awards were announced at DAC on June 8 before the Thursday keynote. "Both of this year's winning papers include outstanding research with tremendous impact for electronics design, and they are the result of highly productive interactions between academia and industry," said Steve Levitan, general chair, 44th DAC. "DAC continues to be the premier venue for presenting the latest research in the field of electronic design." The winning paper titled "Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations," by Shweta Srivastava, Univ. of Minnesota, Minneapolis, Minn., and her advisor, Jaijeet Roychowdhury, addresses a long-existing problem in timing closure for microprocessors: latch characterization. Identifying the performance characteristics of latches, specifically the set-up and hold times, has long been a time consuming process. In some initial research, presented earlier this year at DATE, Roychowdhury 's team demonstrated the basic approach which resulted in a factor of 10X speed increase, shortening the time required from three months to a couple of weeks. The next breakthrough came when the team applied some previously little known research in a new way: the existence of multiple set up and hold time delays for each latch. Previously, characterizing one pair of setup and hold times typically took many months for a cell library. Therefore in the event of timing closure problems, designers were required to change the latch, inevitably making other design sacrifices as a result. Knowing that for each latch any number of valid pairs exist which can be used for timing closure and analysis, Srivastava and Roychowdhury developed a new method for identifying them more quickly. The paper provides this method for doing the required computation in a smarter way, allowing a 20X increase for typical small latches and as a result, allowing designers greater choice and flexibility. The paper has already received strong interest from many EDA tool providers and microprocessor manufacturers. This research is also unique in that it adapted well-known techniques in mixed-signal and RF simulation (homotopy and shooting) to a digital design problem, thanks to Roychowdhury's group's prior experience with analog, RF and mixed-signal CAD. The second winning paper, "Period Optimization for Hard Real-time Distributed Automotive Systems," was written by Abhijit Davare and Qi Zhu, University of California, Berkeley, Marco Di Natale, General Motors Corp., Claudio Pinello, Cadence Design Systems, Inc., Sri Kanajan, General Motors Corp. with advisor Alberto Sangiovanni-Vincentelli, University of California, Berkeley. The paper, which tied to the automotive theme of this year's conference; looks at the mapping problem for distributed automotive systems, which is particularly relevant for the design of active safety applications such, as electronic stability control and parallel parking assist. These applications are deployed on architectures with multiple electronic control units (ECUs) interconnected by buses. Designers need to determine how to assign the activation periods for tasks executed on ECUs and messages transmitted on buses such that end-to-end latencies and other constraints are met. Until now, this problem has required a time-consuming manual process. The method outlined in the paper automates the period assignment stage within mapping. The approach is scalable, allowing realistic industrial problems to be solved within a few minutes. It is also flexible, in that designers can add system-specific constraints if desired. Alberto Sangiovanni-Vincentelli, advisor to Abhijit Davare and Qi Zhu at Berkeley, was instrumental in setting up the collaboration with General Motors and Cadence, and hosted Marco Di Natale from General Motors in Berkeley. Di Natale posed the problem and provided a deep understanding of the prior work in the area. Davare and Zhu developed the approach with help from Pinello and Kanajan. The paper reports two industrial-strength case studies, including an experimental vehicle system obtained from the collaboration with General Motors, which further strengthened the winning paper. Best Paper Selection Process Of the 161 papers presented at the 44th DAC, 15 papers were nominated by the technical subcommittees for consideration for Best Paper, six in the front-end and nine in the back-end. A special best paper selection committee comprised of seven distinguished individuals in the EDA community across faculty, industry and geographies, reviewed the nominated papers. They visited the best paper presentations at the conference, and in a closed meeting on Wednesday afternoon selected a best paper in the front-end and a best paper in the back-end category. ============================================================================== Submission deadlines: --------------------- VLSI'08 - Int'l Conference on VLSI Design (sponsored by SIGDA) ES'08 - Int'l Conference on Embedded Systems Hyderabad, India Jan 4-8, 2008 Deadline: Jul 18, 2007 (extended) http://vlsiconference.com/vlsi2008/ DATE'08 - Design Automation and Test in Europe (sponsored by SIGDA) Munich, Germany Mar 10-14, 2008 Deadline: Sep 9, 2007 http://www.date-conference.com/ IP-SOC'07 - IP Based SoC Design Grenoble, France Dec 5-6, 2007 Deadline: Sep 25, 2007 http://www.us.design-reuse.com/ipsoc2006/ ISCAS'08 - Int'l Symposium on Circuits and Systems Seattle, WA May 18-21, 2008 Deadline: Oct 5, 2007 http://iscas2008.org/ ISPD'08 - Int'l Symposium on Physical Design (sponsored by SIGDA) Portland, OR Apr 13-16, 2008 Deadline: Oct 7, 2007 http://www.ispd.cc/ SPL'08 - Southern Conference on Programmable Logic Bariloche-Patagonia, Argentina Mar 26-28, 2008 Deadline: Nov 1, 2007 http://www.splconf.org/ DAC'08 - Design Automation Conference (sponsored by SIGDA) Anaheim, CA Jun 9-13, 2008 Deadline: Nov 19, 2007 http://www.dac.com/ ============================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- MWSCAS/NEWCAS'07 - Int'l Midwest Symposium on Circuits and Systems/ Int'l NEWCAS Conference Montreal, Canada Aug 5-8, 2007 http://newcas.grm.polymtl.ca/ ISLPED'07 - Int'l Symposium on Low Power Electronics and Design Portland, OR Aug 27-29, 2007 http://www.islped.org/ FPL'07 - Int'l Conference on Field-Programmable Logic and Applications Amsterdam, Holland Aug 27-29, 2007 http://www.fpl.uni-kl.de/fpl/ DSD'07 - Euromicro Conference on Digital System Design Lubeck, Germany Aug 29-31, 2007 http://www.dsdconf.org/ PATMOS'07 - Power and Timing Modeling, Opt. & Sim. Goteborg, Sweden Sep 3-5, 2007 http://www.ce.chalmers.se/research/conference/patmos07/ SBCCI'07 - Symposium on Integrated and Systems Design (sponsored by SIGDA) Rio de Janeiro, Brazil Sep 3-6, 2007 http://www.sbcci.pads.ufrj.br/sbcci/index_sbcci.html PACT'07 - Int'l Conference on Parallel Architectures and Compilation Techniques Brasov, Romania Sep 15-19, 2007 http://www.pactconf.org/ CICC'07 - Custom Integrated Circuits Conference San Jose, CA Sep 16-19, 2007 http://www.ieee-cicc.org/ CODES+ISSS'07 - Int'l Conference on Hardware-Software Codesign and System Synthesis (sponsored by SIGDA) Salzburg, Austria sep 30-Oct 5, 2007 http://www.codes-isss.org/ VLSI-SoC'07 - Int'l Conference on Very Large Scale Integration Atlanta, GA Oct 15-17, 2007 http://www.vlsisoc2007.gatech.edu/ ICCAD'07 - Int'l Conference on Computer-Aided Design (sponsored by SIGDA) San Jose, CA Nov 4-8, 2007 http://www.iccad.com/ PDCS'07 - Int'l Conference on Parallel and Distributed Computing Systems Cambridge, MA Nov 19-21, 2007 http://www.iasted.org/conferences/home-590.html ICST'07 - Int'l Conference on Sensing Technology Palmerston North, New Zealand Nov 26-28, 2007 http://icst.massey.ac.nz/ BIOCAS'07 - Biomedical Circuits and Systems Conference London, UK Nov 27-30, 2007 http://biocas.grm.polymtl.ca/ MICRO'07 - Int'l Symposium on Microarchitecture Chicago, IL Dec 1-5, 2007 http://www.microarch.org/micro40/ ICPADS'07 - Int'l Conference on Parallel and Distributed Systems Hsinchu, Taiwan Dec 5-7, 2007 http://www.ccrc.nthu.edu.tw/icpads2007/ ICFPT'07 - Int'l Conference on Field-Programmable Technology Kitakyushu, Japan Dec 12-14, 2007 http://www.kameyama.ecei.tohoku.ac.jp/icfpt07/ EUC'07 - Int'l Conference on Embedded and Ubiquitous Computing Taipei, Taiwan Dec 17-20, 2007 http://www.cs.ccu.edu.tw/~shiwulo/euc07/ HiPC'07 - Int'l Conference on High Performance Computing Goa, India Dec 18-21, 2007 http://www.hipc.org/ ICM'07 - Int'l Conference on Microelectronics Cairo, Egypt Dec 29-31, 2007 http://www.ieee-icm.com/ ASP-DAC'08 - Asia and South Pacific Design Automation Conference (sponsored by SIGDA) Seoul, Korea Jan 21-24, 2008 http://www.aspdac.com/aspdac2008/ HiPEAC'08: Int'l Conference on High Performance Embedded Architectures & Compilers Goteborg, Sweden Jan 27-29, 2008 http://www.hipeac.net/hipeac2008/ ============================================================================== Upcoming Funding Opportunities -------------------------------- ASEE Naval Research Laboratory (NRL) Postdoctoral Fellowship Program Deadline: Continuous. Applications are accepted on an ongoing basis. http://www.asee.org/resources/fellowships/nrl/index.cfm AAWU International Fellowships Deadline: December 1, 2007 http://www.aauw.org/fga/fellowships_grants/international.cfm ACM Doctoral Dissertation Award Deadline: August 31, 2007 http://fundingopps.cos.com/alerts/33218?id=33218&if=alert NIH NLM Knowledge Management & Applied Informatics Grants Deadline: May 25, 2007 September 25, 2007 January 25, 2008 http://grants1.nih.gov/grants/guide/pa-files/PAR-07-236.html Continued Development and Maintenance of Software (R01) Deadline: May 17, 2007 September 13, 2007 http://grants1.nih.gov/grants/guide/pa-files/PAR-07-235.html NASA Applied Information Systems Research - NNH07ZDA001N-AISR Deadline: To be announced (TBA) http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId=%7B89FBF877-DD5F-AC6E-DAB3-AE19504EA70D%7D&path=open DOD Brain Network Analysis and Modeling for Communication and Orientation - BAA-07-036 Deadline: October 23, 2007 http://www.grants.gov/search/search.do?oppId=14530&mode=VIEW 21st Century Approach to Electronic Device Reliability - BAA-07-036 Deadline: October 23, 2007 http://www.grants.gov/search/search.do?oppId=14530&mode=VIEW Microsystems Technology Office-Wide BAA Deadline: January 14, 2008 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07%2D18/SynopsisP.html ASEE-NRL Postdoctoral Fellowship Program Deadline: Continuous http://hroffice.nrl.navy.mil/jobs/postdoc.htm University Research Instrumentation Program (DURIP) - AFOSR BAA 2007-9 Deadline: August 21, 2007 http://www.afosr.af.mil/ResearchAreas/funding_otherOpp.htm Cognitive Technology Threat Warning System (CT2WS) Deadline: April 11, 2008 http://fedbizopps.cos.com/cgi-bin/getRec?id=20070412a1 Warrior Systems Technologies - Body-Worn Systems, Hand Held Devices, and Smart-Lightweight Electronic Components/Modules for Soldier Protection, Knowledge Management and Cognitive Improvement Deadline: Continuous. (April 1, 2007 ~ March 31, 2009) https://www3.natick.army.mil/ssbaa.htm Homeland Security (2.2.1) - N61339-02-R-0071 Deadline: Continuous. This BAA expires on January 30, 2008 http://www1.fbo.gov/spg/DON/NAVAIR/N61339/N61339-02-R-0071/Attachments.html Microsystems Technology Office-Wide Deadline: January 14, 2009 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07-18/Attachments.html SPINS in Semiconductors Deadline: December 31, 2008 http://fundingopps.cos.com/alerts/57993 Artificial Intelligence Technologies Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/baa.htm Quantum Information Science and Technology Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Young Investigator Program (YIP) January 12, 2008 http://www.onr.navy.mil/sci_tech/3t/corporate/yip.asp High Density Optical Memory Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Quantum Electronic Solids Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Distributed Intelligence Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF Strategic Technologies for Cyberinfrastructure (STCI) Deadline : August 9, 2007 February 14, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=500066&org=NSF&sel_org=NSF&from=fund Engineering Design (ED) Deadline : October 1, 2007 February 15, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13340 Operations Research (OR) Deadline : October 1, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13341&org=NSF&from=fund Instrument Development for Biological Research (IDBR) Deadline: September 12, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=9187&org=NSF&from=home Cyberinfrastructure Training, Education, Advancement, and Mentoring for Our 21st Century Workforce (CI-TEAM) - NSF 07-564 Deadline: August 27, 2007 http://www.nsf.gov/pubs/2007/nsf07564/nsf07564.htm Sloan Foundation Sloan Research Fellowships Deadline: September 15, 2007 http://www.sloan.org/programs/scitech_fellowships.shtml Soroptimist International of the Americas, Inc. Women's Opportunity Awards Deadline: December 1, 2007 http://www.soroptimist.org/sia/AM/Template.cfm?Section=WOMEN_S_OPPORTUNITY_AWARDS ============================================================================== Call For Participations -------------------------- HOT Chips 19 A Symposium on High-Performance Chips August 19-21, 2007, Memorial Auditorium, Stanford University, Palo Alto, California HOT Chips brings together designers and architects of high-performance chips, software, and systems. Presentations focus on up-to-the-minute real developments. This symposium is the primary forum for engineers and researchers to highlight their leading-edge designs. Three full days of tutorials and technical sessions will keep you on top of the industry. See http://www.hotchips.org for registration information, local arrangements, location, etc. Registration: Early Registration: June 1, 2007 to July 31, 2007 Tutorials Only Conference Only Both ACM/IEEE Members $100 $295 $395 Non-Members $125 $395 $520 Student Members $85 $85 $170 Student Non-Members $90 $110 $200 Late Registration: After July 31st, 2007 Tutorials Only Conference Only Both ACM/IEEE Members $175 $475 $650 Non-Members $200 $575 $775 Student Members $95 $145 $240 Student Non-Members $100 $150 $250 Registration fees for Tutorials include a printed set of tutorial notes, continental breakfast, lunch, coffee break, and invitation to the evening Wine and Cheese Reception on Sunday, August 19, 2007. Registration fees for the Conference include a flash drive containing a set of the conference proceedings (printed sets are available for purchase with advance registration), Monday night dinner, continental breakfasts, lunches and coffee breaks during the two days (August 20-21, 2007) of the conference. It also includes an invitation to the evening Wine and Cheese Reception on Sunday, August 19, 2007. Hot Chips is A Symposium of the Technical Committee on Microprocessors and Microcomputers of the IEEE Computer Society and the IEEE Solid State Circuits Society ============================================================================== Call for Papers ------------------------------ 14th IEEE International Symposium on Asynchronous Circuits and Systems 7th - 11th April 2008 Newcastle upon Tyne, UK The International Symposium on Asynchronous Circuits and Systems provides a high-quality forum for scientists and engineers to present their latest research findings. Authors are invited to submit full papers on all aspects of asynchronous design. Topics of interest include, but are not limited to: * Mixed synchronous/asynchronous architectures, interfaces, and circuits. * Design, synthesis and Verification techniques for GALS systems. * Synchronous-asynchronous interaction at different levels. * High-speed/low-power asynchronous logic, memories, and interconnects. * High-level design and synthesis of self-timed circuits. * Physical design of unclocked logic and pipelines. * Formal methods for correctness and performance analysis of asynchronous designs. * Test, reliability, security, and radiation tolerance. * CAD for asynchronous design and validation. * Asynchronous System-on-Chip (SoC), System-in-Package (SiP). * Novel asynchronous architectures. * Asynchrony and latency tolerance in system-level design. * Motivating case studies, comparisons, and applications. * Embedded System Design with asynchronous architectures/implementations. * Asynchronous design for manufacturing. Papers must be submitted via the conference web site. Papers will be evaluated by the program committee and reviews will be based on scientific merit, innovation, relevance, and presentation. New idea papers are encouraged, and the program committee recognizes that such papers may contain less evaluation than papers in established areas. Accepted papers will be published in an IEEE proceedings and distributed at the symposium. Please check the symposium website for up-to-date information: http://async.org.uk/async2008/ Important dates: Submission information: * Abstract registration: October 8, 2007 * Full paper submission: October 15, 2007 Notification of acceptance: December 12, 2007 Final version due: January 18, 2008 Paper format: Abstract of up to 150 words, 10 pages or fewer, including figures and bibliography, single spaced, 10pt or larger font size, IEEE double-column conference format. ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ============================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To manage your subscription, go to "Subscriber's corner" on http://listserv.acm.org/ - you need to login using the email address where this newsletter is delivered. First time users will be required to choose a password.) ==============================================================================