=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membersip. Circulation: 2,700 =============================================================================== 15 June 2007 ACM/SIGDA E-NEWSLETTER Vol. 37, No. 12 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) 44th DAC Best Paper Honors From: DAC Press Release (3) What is Eavesdropping on Laptops Through Walls? Author: Tom Simonite, New Scientist From: Igor Markov (4) Paper Submission Deadlines From: Hai Zhou (5) Upcoming Conferences and Symposia From: Hai Zhou (6) Upcoming Funding Opportunities From: Qinru Qiu (7) Table of Contents : ACM TODAES (8) Call for Papers : PhD Forum of 2007 VLSI-SoC From: Matthew Guthaus (9) Call for Papers : ASP-DAC 2008 From: Hai Zhou =============================================================================== Dear ACM/SIGDA members, In this issue, we have reprinted the "What is Eavesdropping on Laptops Through Walls?" column in the previous newsletter. In addition, the "SIGDA News" column contains a number of fresh headlines. We have also updated the contents of other regular columns. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Tony Givargis, E-Newsletter Associate Editor; Matthew Guthaus, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "IMEC Group Takes Multi-Gate Transistors to New Dimensions" http://www.eetimes.com/showArticle.jhtml?articleID=199903620 At the VLSI symposium in Kyoto, Japan, semiconductor research center IMEC announced significant progress in its efforts aiming at sub-32nm technologies. The results presented focus on multi-gate field effect transistors (MugFETs) with Infineon claiming to have achieved the lion's share of the research results. The three-dimensional MugFET, a specific implementation of the FinFET approach, is said to be a major challenge for future chip generations. While it can help to drive down size, switching time, and, most important, leakage current in small geometry chips, it is more difficult to build compared to today's two-dimensional (planar) single-gate transistors. Ingredients of this transistor are advanced high-k gate dielectrics and metal gates. Since doping fluctuations in nanoscale planar devices are a concern in further scaling, FinFETs can operate without channel dopants. The transistors shown have been produced using 193nm immersion lithography and dry etching. According to Infineon, the transistors feature a 90 percent reduction in off current and a 50 percent reduction in transistor switching power over today's 65-nm standard CMOS transistors, creating a significant energy savings potential for next-but-one generation chips. "TI Enters High-K Dielectrics Era" http://www.eetimes.com/showArticle.jhtml?articleID=199903583 Texas Instruments entered the high-k dielectrics arena, announcing plans to integrate this material for its high-performance chips at the 45-nm node. The chip maker also plans to deploy metal gates at 45-nm, but TI did not elaborate on the specifics. Meanwhile, TI will first deploy its high-k materials on the microprocessor front, reportedly for Sun Microsystems Inc.'s Sparc devices. TI manufacturers Sparc chips on a foundry basis for Sun. In its approach, TI will leverage a chemical vapor deposition (CVD) process to deposit hafnium silicon oxide (HfSiO), followed by a reaction with a downstream nitrogen plasma process to form HfSiON or hafnium silicon oxynitride. The technology will reduce leakage by more than 30 times per unit area, as compared with commonly used silicon oxide materials for gate dielectrics, said Ben McKee, vice president of CMOS development at TI. IBM, Intel and NEC have separately announced processes that make use of high-k. In recent times, TI has tweaked its fab strategy. Moving to remain competitive in what has become a brave new world of IC manufacturing, TI recently disclosed the details of its revised "hybrid" fab strategy. The chip maker is bolstering its in-house efforts in analog production, but it is also shifting more of its logic-based IC work and process flow to the foundries. "It's Time To Lift The Burden From Logic Designers" http://www.elecdesign.com/Articles/ArticleID/15768/15768.html These are not easy times for logic designers. As geometries shrink and chips grow ever larger and more complex, more and more design decisions are being pushed up to the RTL stage. When these decisions are made incorrectly, the result is long iterative loops between back-end processes and RTL, leading to unpredictable tape-out dates. "EDA Pioneer to Receive 2007 IEEE Robert N. Noyce Medal" http://www.chipdesignmag.com/display.php?articleId=1363 The IEEE has named Aart de Geus as the recipient of its 2007 IEEE Robert N. Noyce Medal, recognizing his pioneering role in establishing electronic design automation (EDA) as a productive and efficient way of designing and producing integrated circuits and circuit boards. The IEEE is the world's leading professional association for the advancement of technology. "Delirium Over Power Dilemma" http://www.cieonline.co.uk/cie2/articlen.asp?pid=1616&id=16967 Can system-level innovations solve the low power/ process-tolerance dilemma? Nilanjan Banerjee and Kaushik Roy take a look. While CMOS technology has successfully served the industry over the past 30 years, it's encountering several major barriers at sub-65nm process nodes. This is due to higher levels of integration and physical limitations of the devices. The two major challenges that IC designers face today are power dissipation and process variations. "FPGA Explosion Will Test EDA" http://www.elecdesign.com/Articles/ArticleID/15910/15910.html Anyone who has seen the transformation of the electronics design market from fixed-chip development to programmable devices can attest to the dramatic impact that FPGAs have made on both electronic product development and the miniaturization of electronics. As these devices get larger and more capable, an increasing number of designers are marching toward FPGAs each and every day. According to research firm Gartner/Dataquest, this year will see nearly 89,000 FPGA design starts, and will swell to 112,000 in 2010-some 25 times that of ASICs. "On The Brink Of Artificial Life" http://www.businessweek.com/magazine/content/07_26/b4040047.htm?chan=top+news_top+news+index_technology Craig Venter says success is near, but critics blast efforts to patent synthetic organisms. First he succeeded in reading humanity's genetic code. Now gene pioneer J. Craig Venter believes he is within weeks or months of creating the world's first free-living artificial organism in his laboratory. It won't be much to look at-a tiny bacterium with only a few hundred genes. But if it's truly feasible, he says, "it will be one of the bright milestones in human history, changing our conceptual view of life." "Experts: Synthetic Biology May Spawn Biohackers" http://www.eetimes.com/showArticle.jhtml;jsessionid=TPBKVQD3PVI00QSNDLPCKHSCJUNN2JVN?articleID=22101632 Design automation systems tailored to the task of genetic engineering could prove to be double-edged tools. While they represent a central thrust of the emerging synthetic biology movement, they also can lead to the accidental or deliberate creation of pathogenic biological components. ============================================================================== 44th DAC Best Paper Honors ------------------------------ SAN DIEGO, Calif. - June 19, 2007 - The 44th Design Automation Conference (DAC), awarded Best Paper honors to two noteworthy technical papers presented at this year's conference. "Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations," provides a breakthrough solution to a longstanding problem with timing closure. "Period Optimization for Hard Real-time Distributed Automotive Systems;" presents a new solution to the mapping problem for distributed automotive systems. The Best Paper awards were announced at DAC on June 8 before the Thursday keynote. "Both of this year's winning papers include outstanding research with tremendous impact for electronics design, and they are the result of highly productive interactions between academia and industry," said Steve Levitan, general chair, 44th DAC. "DAC continues to be the premier venue for presenting the latest research in the field of electronic design." The winning paper titled "Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations," by Shweta Srivastava, Univ. of Minnesota, Minneapolis, Minn., and her advisor, Jaijeet Roychowdhury, addresses a long-existing problem in timing closure for microprocessors: latch characterization. Identifying the performance characteristics of latches, specifically the set-up and hold times, has long been a time consuming process. In some initial research, presented earlier this year at DATE, Roychowdhury 's team demonstrated the basic approach which resulted in a factor of 10X speed increase, shortening the time required from three months to a couple of weeks. The next breakthrough came when the team applied some previously little known research in a new way: the existence of multiple set up and hold time delays for each latch. Previously, characterizing one pair of setup and hold times typically took many months for a cell library. Therefore in the event of timing closure problems, designers were required to change the latch, inevitably making other design sacrifices as a result. Knowing that for each latch any number of valid pairs exist which can be used for timing closure and analysis, Srivastava and Roychowdhury developed a new method for identifying them more quickly. The paper provides this method for doing the required computation in a smarter way, allowing a 20X increase for typical small latches and as a result, allowing designers greater choice and flexibility. The paper has already received strong interest from many EDA tool providers and microprocessor manufacturers. This research is also unique in that it adapted well-known techniques in mixed-signal and RF simulation (homotopy and shooting) to a digital design problem, thanks to Roychowdhury's group's prior experience with analog, RF and mixed-signal CAD. The second winning paper, "Period Optimization for Hard Real-time Distributed Automotive Systems," was written by Abhijit Davare and Qi Zhu, University of California, Berkeley, Marco Di Natale, General Motors Corp., Claudio Pinello, Cadence Design Systems, Inc., Sri Kanajan, General Motors Corp. with advisor Alberto Sangiovanni-Vincentelli, University of California, Berkeley. The paper, which tied to the automotive theme of this year's conference; looks at the mapping problem for distributed automotive systems, which is particularly relevant for the design of active safety applications such, as electronic stability control and parallel parking assist. These applications are deployed on architectures with multiple electronic control units (ECUs) interconnected by buses. Designers need to determine how to assign the activation periods for tasks executed on ECUs and messages transmitted on buses such that end-to-end latencies and other constraints are met. Until now, this problem has required a time-consuming manual process. The method outlined in the paper automates the period assignment stage within mapping. The approach is scalable, allowing realistic industrial problems to be solved within a few minutes. It is also flexible, in that designers can add system-specific constraints if desired. Alberto Sangiovanni-Vincentelli, advisor to Abhijit Davare and Qi Zhu at Berkeley, was instrumental in setting up the collaboration with General Motors and Cadence, and hosted Marco Di Natale from General Motors in Berkeley. Di Natale posed the problem and provided a deep understanding of the prior work in the area. Davare and Zhu developed the approach with help from Pinello and Kanajan. The paper reports two industrial-strength case studies, including an experimental vehicle system obtained from the collaboration with General Motors, which further strengthened the winning paper. Best Paper Selection Process Of the 161 papers presented at the 44th DAC, 15 papers were nominated by the technical subcommittees for consideration for Best Paper, six in the front-end and nine in the back-end. A special best paper selection committee comprised of seven distinguished individuals in the EDA community across faculty, industry and geographies, reviewed the nominated papers. They visited the best paper presentations at the conference, and in a closed meeting on Wednesday afternoon selected a best paper in the front-end and a best paper in the back-end category. ============================================================================== What is Eavesdropping on Laptops Through Walls? -------------------------------------------------- Tom Simonite, New Scientist http://www.newscientist.com/blog/technology/2007/04/seeing-through-walls.html ============================================================================== Submission deadlines: --------------------- HiPEAC'08: Int'l Conference on High Performance Embedded Architectures & Compilers Goteborg, Sweden Jan 27-29, 2008 Deadline: Jun 16, 2007 http://www.hipeac.net/hipeac2007/ ICM'07 - Int'l Conference on Microelectronics Cairo, Egypt Dec 29-31, 2007 Deadline: Jun 30, 2007 (extended) http://www.ieee-icm.com/ ICFPT'07 - Int'l Conference on Field-Programmable Technology Kitakyushu, Japan Dec 12-14, 2007 Deadline: Jun 25, 2007 http://www.kameyama.ecei.tohoku.ac.jp/icfpt07/ ICST'07 - Int'l Conference on Sensing Technology Palmerston North, New Zealand Nov 26-28, 2007 Deadline: Jun 29, 2007 http://icst.massey.ac.nz/ BIOCAS'07 - Biomedical Circuits and Systems Conference London, UK Nov 27-30, 2007 Deadline: Jul 2, 2007 http://biocas.grm.polymtl.ca/ ASP-DAC'08 - Asia and South Pacific Design Automation Conference (sponsored by SIGDA) Seoul, Korea Jan 21-24, 2008 Deadline: Jul 10, 2007 http://www.aspdac.com/aspdac2008/ VLSI'08 - Int'l Conference on VLSI Design (sponsored by SIGDA) ES'08 - Int'l Conference on Embedded Systems Hyderabad, India Jan 4-8, 2008 Deadline: Jul 10, 2007 http://vlsiconference.com/vlsi2008/ DATE'08 - Design Automation and Test in Europe (sponsored by SIGDA) Munich, Germany Mar 10-14, 2008 Deadline: Sep 9, 2007 http://www.date-conference.com/ ============================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- CAV'07 - Int'l Conference on Computer Aided Verification Berlin, Germany Jul 3-7, 2007 http://www.cav2007.org/ ASAP'07 - Int'l Conference on Application-specific Systems, Architectures and Processors Montreal, Canada Jul 9-11, 2007 http://asap-conference.org/ ACSD'07 - Int'l Conference on Application of Concurrency to System Design (Sponsored by SIGDA) Bratislava, Slovak Republic Jul 10-13 2007 http://www.acsd.sk/ MWSCAS/NEWCAS'07 - Int'l Midwest Symposium on Circuits and Systems/ Int'l NEWCAS Conference Montreal, Canada Aug 5-8, 2007 http://newcas.grm.polymtl.ca/ FPL'07 - Int'l Conference on Field-Programmable Logic and Applications Amsterdam, Holland Aug 27-29, 2007 http://www.fpl.uni-kl.de/fpl/ DSD'07 - Euromicro Conference on Digital System Design Lubeck, Germany Aug 29-31, 2007 http://www.dsdconf.org/ PATMOS'07 - Power and Timing Modeling, Opt. & Sim. Goteborg, Sweden Sep 3-5, 2007 http://www.ce.chalmers.se/research/conference/patmos07/ SBCCI'07 - Symposium on Integrated and Systems Design (sponsored by SIGDA) Rio de Janeiro, Brazil Sep 3-6, 2007 http://www.sbcci.pads.ufrj.br/sbcci/index_sbcci.html PACT'07 - Int'l Conference on Parallel Architectures and Compilation Techniques Brasov, Romania Sep 15-19, 2007 http://www.pactconf.org/ CICC'07 - Custom Integrated Circuits Conference San Jose, CA Sep 16-19, 2007 http://www.ieee-cicc.org/ CODES+ISSS'07 - Int'l Conference on Hardware-Software Codesign and System Synthesis (sponsored by SIGDA) Salzburg, Austria sep 30-Oct 5, 2007 http://www.codes-isss.org/ VLSI-SoC'07 - Int'l Conference on Very Large Scale Integration Atlanta, GA Oct 15-17, 2007 http://www.vlsisoc2007.gatech.edu/ ICCAD'07 - Int'l Conference on Computer-Aided Design (sponsored by SIGDA) San Jose, CA Nov 4-8, 2007 http://www.iccad.com/ PDCS'07 - Int'l Conference on Parallel and Distributed Computing Systems Cambridge, MA Nov 19-21, 2007 http://www.iasted.org/conferences/home-590.html MICRO'07 - Int'l Symposium on Microarchitecture Chicago, IL Dec 1-5, 2007 http://www.microarch.org/micro40/ ICPADS'07 - Int'l Conference on Parallel and Distributed Systems Hsinchu, Taiwan Dec 5-7, 2007 http://www.ccrc.nthu.edu.tw/icpads2007/ EUC'07 - Int'l Conference on Embedded and Ubiquitous Computing Taipei, Taiwan Dec 17-20, 2007 http://www.cs.ccu.edu.tw/~shiwulo/euc07/ HiPC'07 - Int'l Conference on High Performance Computing Goa, India Dec 18-21, 2007 http://www.hipc.org/ ============================================================================== Upcoming Funding Opportunities -------------------------------- ASEE Naval Research Laboratory (NRL) Postdoctoral Fellowship Program Deadline: Continuous. Applications are accepted on an ongoing basis. http://www.asee.org/resources/fellowships/nrl/index.cfm AAWU International Fellowships Deadline: December 1, 2007 http://www.aauw.org/fga/fellowships_grants/international.cfm ACM Doctoral Dissertation Award Deadline: August 31, 2007 http://fundingopps.cos.com/alerts/33218?id=33218&if=alert NIH NLM Knowledge Management & Applied Informatics Grants Deadline: May 25, 2007 September 25, 2007 January 25, 2008 http://grants1.nih.gov/grants/guide/pa-files/PAR-07-236.html Continued Development and Maintenance of Software (R01) Deadline: May 17, 2007 September 13, 2007 http://grants1.nih.gov/grants/guide/pa-files/PAR-07-235.html NASA Applied Information Systems Research - NNH07ZDA001N-AISR Deadline: To be announced (TBA) http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId=%7B89FBF877-DD5F-AC6E-DAB3-AE19504EA70D%7D&path=open DOD University Research Instrumentation Program (DURIP) - AFOSR BAA 2007-9 Deadline: August 21, 2007 http://www.afosr.af.mil/ResearchAreas/funding_otherOpp.htm Cognitive Technology Threat Warning System (CT2WS) Deadline: April 11, 2008 http://fedbizopps.cos.com/cgi-bin/getRec?id=20070412a1 Warrior Systems Technologies - Body-Worn Systems, Hand Held Devices, and Smart-Lightweight Electronic Components/Modules for Soldier Protection, Knowledge Management and Cognitive Improvement Deadline: Continuous. (April 1, 2007 ~ March 31, 2009) https://www3.natick.army.mil/ssbaa.htm Homeland Security (2.2.1) - N61339-02-R-0071 Deadline: Continuous. This BAA expires on January 30, 2008 http://www1.fbo.gov/spg/DON/NAVAIR/N61339/N61339-02-R-0071/Attachments.html Microsystems Technology Office-Wide Deadline: January 14, 2009 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07-18/Attachments.html SPINS in Semiconductors Deadline: December 31, 2008 http://fundingopps.cos.com/alerts/57993 Artificial Intelligence Technologies Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/baa.htm Quantum Information Science and Technology Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Young Investigator Program (YIP) January 12, 2008 http://www.onr.navy.mil/sci_tech/3t/corporate/yip.asp High Density Optical Memory Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Quantum Electronic Solids Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Distributed Intelligence Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF Instrument Development for Biological Research (IDBR) Deadline: September 12, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=9187&org=NSF&from=home Cyberinfrastructure Training, Education, Advancement, and Mentoring for Our 21st Century Workforce (CI-TEAM) - NSF 07-564 Deadline: August 27, 2007 http://www.nsf.gov/pubs/2007/nsf07564/nsf07564.htm CreateiveIT (NSF 07-562) Deadline: July 23, 2007 http://www.nsf.gov/pubs/2007/nsf07562/nsf07562.htm Accelerating Discovery in Science and Engineering Through Petascale Simulations and Analysis (PetaApps) - NSF 07-559 Deadline: July 23, 2007 http://www.nsf.gov/pubs/2007/nsf07559/nsf07559.htm Biological Databases and Informatics - NSF 05-577 Deadline: July 9, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=5444 Sloan Foundation Sloan Research Fellowships Deadline: September 15, 2007 http://www.sloan.org/programs/scitech_fellowships.shtml ============================================================================== Table of Contents ------------------- ACM Transactions on Design Automation of Electronic Systems (TODAES) Volume 12 , Issue 2 (April 2007) Editorial Nikil Dutt http://portal.acm.org/ft_gateway.cfm?id=1230801&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Disjunctive image computation for software verification Chao Wang, Zijiang Yang, Franjo Ivanv.i., Aarti Gupta http://portal.acm.org/ft_gateway.cfm?id=1230802&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Transition-overhead-aware voltage scheduling for fixed-priority real-time systems Bren Mochocki, Xiaobo Sharon Hu, Gang Quan http://portal.acm.org/ft_gateway.cfm?id=1230803&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Prediction of leakage power under process uncertainties Hongliang Chang, Sachin S. Sapatnekar http://portal.acm.org/ft_gateway.cfm?id=1230804&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 A model-based extensible framework for efficient application design using FPGA Sumit Mohanty, Viktor K. Prasanna http://portal.acm.org/ft_gateway.cfm?id=1230805&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 A predictive decode filter cache for reducing power consumption in embedded processors Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau http://portal.acm.org/ft_gateway.cfm?id=1230806&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 DRDU: A data reuse analysis technique for efficient scratch-pad memory management Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt http://portal.acm.org/ft_gateway.cfm?id=1230807&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Low test application time resource binding for behavioral synthesis Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi http://portal.acm.org/ft_gateway.cfm?id=1230808&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 A critical-path-aware partial gating approach for test power reduction Mohammed Elshoukry, Mohammad Tehranipoor, C. P. Ravikumar http://portal.acm.org/ft_gateway.cfm?id=1230809&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Forming N-detection test sets without test generation Irith Pomeranz, Sudhakar M. Reddy http://portal.acm.org/ft_gateway.cfm?id=1230810&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 The exact channel density and compound design for generic universal switch blocks Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung http://portal.acm.org/ft_gateway.cfm?id=1230811&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 ============================================================================== Call for Papers ----------------- PhD Forum Call for Paper VLSI-SoC 2007 15-17 October 2007 Georgia Institute of Technology Altanta, Georgia, U.S.A. The PhD Forum at VLSI-SoC 2007 Conference is a poster session included as part of the conference program, aiming at the exchange of ideas and experiences of PhD students from different parts of the world. Elected PhD students will have an opportunity to discuss their thesis and research work with specialists within the system and design automation community. This offers a good opportunity for students to receive valuable feedback on their work and to gain exposure to the job market. Furthermore, this forum also provides a great chance for industry to meet junior researchers, giving the avenue for incorporating the latest research developments into their companies. *Eligibility The author must have completed at least one year of a PhD program. *Presentation Posters will be introduced in the PhD Forum Session (2 minute time slot, one slide) and next presented in a full one-hour Poster Session. *Publication Accepted abstracts will be published as papers (6 pages maximum) in a separate VLSI-SoC'07 PhD CD-ROM Proceedings. *Grants for PhD students VLSI-SoC 2007 finances a limited number of travel grants for PhD students, through the Technical Committee TC-10 (Computer Students Technology) of International Federation for Information Processing. In principle grants are restricted to support students that cannot be supported by their institutions. This rule gives preference to students being enrolled in Africa, Latin America, Eastern Europe including Russia, and Asia (except Israel, Japan, South Korea and Taiwan). The percentage covered by a grant should be at least 50% of the total costs. *How to Submit A one-page extended abstract of the dissertation plus one page for figures in PDF format. The one-page limit on the abstract text and figures will be strictly enforced. Send submission to waynecheng@mail.nctu.edu.tw before June 25, 2007. ============================================================================== Call for Papers ----------------- ASP-DAC 2008 Asia and South Pacific Design Automation Conference 2008 http://www.aspdac.com/aspdac2008/ January 21-24, 2008 COEX, Seoul, Korea Aims of the Conference: ASP-DAC 2008 is the thirteenth in a series of annual international conferences on VLSI design automation. Asia and South Pacific region is one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances in the technologies related to Electronic Design Automation (EDA) and discussing the future directions. The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. A wide variety of those scientists, engineers, and students who are interested in theoretical issues in EDA are also welcome. Areas of Interest: Original papers on, but not limited to, the following areas are invited. [1] System Level Design: System VLSI and SOC design methods, System specification, Specification languages, Design languages, Hardware-software co-design, Co-simulation, Co-verification, Platform-based design, Design reuse and IP's [2] Embedded and Real-Time Systems: Low power system design, Network on chip, Communication architecture, Memory architecture, Real-time OS and middleware, Compilation techniques, ASIP synthesis [3] Behavioral/Logic Synthesis and Optimization: Behavioral/RTL synthesis, Technology-independent optimization, Technology mapping, Interaction between logic design and layout, Sequential and asynchronous logic synthesis [4] Validation and Verification for Behavioral/Logic Design: Logic simulation, Symbolic simulation, Formal verification, Equivalence checking, Transaction-level/RTL and gate-level modeling and validation [5] Physical Design (Routing): Routing, Repeater issues, Interconnect optimization, Interconnect planning, Module generation, Layout verification [6] Physical Design (Placement): Placement, Floorplanning, Partitioning, Hierarchical design [7] Timing, Power, Signal/Power Integrity Analysis and Optimization: Timing analysis, Power analysis, Signal/power integrity, Clock and global signal design [8] Interconnect, Device and Circuit Modeling and Simulation: Interconnect modeling, Interconnect extraction, Package modeling, Circuit simulation, Device modeling/simulation, Library design, Design fabrics, Design for manufacturability, Yield optimization, Reliability analysis, Emerging technologies [9] Test and Design for Testability: Test design, Fault modeling, ATPG, BIST and DFT, Memory, core and system test [10] Analog, RF and Mixed Signal Design and CAD: Analog/RF synthesis, Analog layout, Verification, Simulation techniques, Noise analysis, Analog circuit testing, Mixed-signal design considerations [11] Leading Edge Design Methodology for SOCs and SIPs: Design methodology for Microprocessors, DSP, IP-core, multimedia processors, wireless communication systems, A/D mixed circuits, Memories, Sensors, MEMS chips, FPGAs, Novel reconfigurable systems, Rapid prototyping ASP-DAC 2008 University LSI Design Contest encourages submitting original papers on LSI design and implementation at universities and other educational organizations. Submission of Papers: Deadline for submission: 5 pm KST, July 10 (Tue), 2007 Notification of acceptance: September 28 (Fri), 2007 Deadline for final version: 5 pm KST, November 16 (Fri), 2007 Panels, Special Sessions and Tutorials: Suggestions and proposals are welcome and have to be addressed to the Conference Secretariat (e-mail:aspdac2008@aspdac.com) no later than 5 pm KST, June 8 (Fri.), 2007. Prospective Sponsors: ACM SIGDA, IEEE Circuits and Systems Society, IEEK (The Institute of Electronics Engineers of Korea) ASP-DAC2008 Chairs: General Chair: Chong-Min Kyung (KAIST) Technical Program Co-Chairs: Kiyoung Choi (Seoul National Univ.), Soonhoi Ha (Seoul National Univ.) Technical Program Vice Chair: Ren-Song Tsay (National Tsing Hua Univ.) Conference Secretariat: Please contact Conference Secretariat ( e-mail:aspdac2008@aspdac.com), if you have questions or comments. Specification of the paper submission format will be available at the WEB site: http://www.aspdac.com/aspdac2008/ ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. 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