=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membersip. Circulation: 2,700 =============================================================================== 1 March 2007 ACM/SIGDA E-NEWSLETTER Vol. 37, No. 5 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What is Universal Serial Bus (USB) ? Author: Dan Harmon, Texas Instruments Inc. From: Igor Markov (3) Special Feature : Interview with Tony Tether, the DARPA director Conducted by: Noah Shachtman, Wired From: Igor Markov (4) Paper Submission Deadlines From: Hai Zhou (5) Upcoming Conferences and Symposia From: Hai Zhou (6) Call For Papers : Special Section on Networks-on-Chips: Modeling, Analysis and Optimization From: Radu Marculescu (7) Call For Papers : 2007 International Workshop on Logic and Synthesis From: Marc Riedel (8) Call For Papers : Special Issue: Circuits and Systems for Real-Time Security and Copyright Protection of Multimedia International Journal of Computers and Electrical Engineering (Elsevier Ltd.) From : Saraju P. Mohanty (9) Upcoming Funding Opportunities From: Qinru Qiu (10) Call for Submissions: 10th Annual ACM/SIGDA Ph.D. Forum at DAC From: Elaheh Bozorgzadeh =============================================================================== Dear ACM/SIGDA members, This issue's "What is ..." column is linked to the article "Which version of USB is right for your application?" by Dan Harmon, in Planet Analog. We have also included a special feature "Interview with Tony Tether, the DARPA director". In addition, the "SIGDA News" column contains a number of fresh headlines. We have also updated the contents of other regular columns. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Tony Givargis, E-Newsletter Associate Editor; Matthew Guthaus, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "IBM Sees Immersion at 22nm, Pushes out EUV" http://www.eetimes.com/showArticle.jhtml?articleID=197008463 IBM Corp. Friday (Feb. 23) outlined its lithography roadmap, saying that it would extend 193-nm immersion lithography down to the 22-nm node for logic production. In other words, extreme ultraviolet (EUV) lithography could get pushed out again, as the technology is not expected to be ready for the early development work at the 22-nm node for logic, according to IBM's lithography guru. "Wet lithography" will first be used at the 45-nm node, and IBM will extend 193-nm immersion down to the 32-nm node (45-nm half-pitch) for logic. "NEC Shuts Fabs, Exits Structured ASICs" http://www.eetimes.com/showArticle.jhtml?articleID=197008125 Coping with a ''crisis'' amid losses in its business, troubled NEC Electronics Corp. Thursday (Feb. 22) announced a three-year restructuring plan that included the exit from the structured ASIC and single-chip cell phone sectors. The company, which is also terminating 600 engineers, will consolidate its nine front-end manufacturing lines in Japan to four. "AMD Chipset with Built-in ATI Graphics, No Graphics Card Needed" http://www.pcworld.com/article/id,129466-c,graphicschips/article.html Advanced Micro Devices (AMD) today announced the availability of its 690 chipset, the company's first integrated chipset for AMD processors that includes the ATI Radeon X1250 graphics processor. Integrating the Radeon X1250 graphics processor into the 690 chipset means PCs based on the chipset will not require an add-in graphics card. And by building the chipset itself instead of relying on partner companies, AMD will gain competitive leverage against Intel Corp., said Chris Evenden, director of public relations for visual and media business at AMD. "Graphene Transistor to Rival Silicon, Say Researchers" http://eetimes.eu/197700700 Researchers at the University of Manchester, working with a group at the Max Planck Institute in Germany, claim to have created transistors that are just one atom-thick and less than 50 atoms wide from a new class of material. The novel transistors operate at room temperature making them potentially viable for future electronic components. Circuits using this technology would include the central element, or "quantum dot", semitransparent barriers to control the movement of individual electrons, interconnects and logic gates . all made entirely of graphene. "How Steve Jobs Blew his iPhone Keynote" http://www.computerworld.com/action/article.do?command=viewArticleBasic&articleId=9008439 Steve Jobs' blockbuster keynote address at last week's Macworld was brilliantly and powerfully delivered -- one of his best ever. It was also a colossal mistake. "New AMD Quad-core Processor Improves Floating-point and Integer Performance" http://www.eetimes.com/showArticle.jhtml?articleID=197700269 Advanced Micro Devices upcoming Barcelona processor will sport floating-point performance 42 percent higher than Intel's current top-of-the line CPU, the Xeon X5355 also known as Clovertown. Mario Rivas, general manager of AMD's microprocessor group, said Barcelona will also provide a double-digit leap in integer performance over the quad-core Xeon, though he declined to be more specific. "Intel Offers Phase-Change Memory" http://www.eetimes.com/showArticle.jhtml?articleID=197800524 Intel Corp. (Santa Clara, Calif.) is preparing to sample a 90-nm 128-Mbit phase change memory to customers in the first half of 2007. Mass production could begin before the end of 2007. Intel Corp. and STMicroelectronics NV announced they had teamed up their research on chalcogenide-based phase-change memory as a likely successor to flash as a non-volatile memory, in June 2006. Intel's 128-Mbit chips had demonstrated 100,000,000 cycles endurance and are projected to preserve data for "much greater than 10 years". "Cutting FPGA Design Time" http://www.newelectronics.co.uk/article/index.aspx?articleid=M4FJ3s1XVlQeiVy19_Kn5QI26W4-aIJV3lEw8Wgb6XEA For many FPGA designs, basic knowledge of the place and routing capabilities of modern PLD design tools, as well as a minimum of design preferences, is sufficient to produce reasonable results. But if a critical performance metric needs to be achieved, a more sophisticated approach is needed. The tools embedded within today.s pld software suites can help save time and money during the design implementation stage. The principles are outlined using Lattice Semiconductor.s ispLEVER as an example. "Design Verification, Process Technology...The Wheel Goes 'round Again" http://www.edn.com/index.asp?layout=article&articleid=CA6418218&industryid=2813 Recent technology and product announcements remind me of the saying, .Everything old is new again.. This phrase has been popping into mind more frequently as industry pundits herald new bottlenecks and incremental solutions to process- and design-tool issues as revolutionary. For design and EDA veterans, again hearing these discussions jogs the memory a bit. "Sparks Fly at EDA 'Troublemakers' Panel at DVCon" http://www.eetimes.com/showArticle.jhtml?articleID=197008441 The annual "EDA Bigwigs" panel at the Design and Verification Conference (DVCon) was renamed the "Troublemaker's Panel" this year for good reason. Confronted with provocative questions, EDA vendor representatives debated such topics as low-power standards, Cadence Design Systems' Skill language, and outsourcing to India. As in previous years, the DVCon panel was moderated by John Cooley, whose Deepchip web site listed "edgy questions" sent in by EDA users prior to the panel. Companies represented in the Thursday (Feb. 22) panel included Cadence, Mentor Graphics, Synopsys, Magma Design Automation, Sequence Design, Clear Shape Technologies, and Forte Design, in addition to EDA analyst Gary Smith. "Windows Vista Worse For User Efficiency Than XP" http://www.it-enquirer.com/main/ite/more/pfeiffer_vista/ Pfeiffer Consulting released a report on User Interface Friction, comparing Windows Vista/Aero with Windows XP and Mac OS X. The report concludes that Vista/Aero is worse in terms of desktop operations, menu latency, and mouse precision than XP . which was and still is said to be a lot worse on those measures than Mac OS X. The report was independently financed. The IT-Enquirer editor has read the report and summarized the most important findings. "Startup: OPC Alternative May Extend Dry Steppers" http://www.eetimes.com/showArticle.jhtml?articleID=197009069 Luminescent Technologies is reporting on the latest results of its inverse lithography technology as applied to 45- and 32-nanometer chips at the SPIE Advanced Lithography Conference, running here Feb. 25-March 2. Among the findings is that ILT can address the problem of line-end shortening in the poly and diffusion layers at 45 nm, Luminescent said. Manufacturers are exploring the possibility of extending their dry steppers at the 45-nm node, delaying the move to immersion lithography. "Freescale Simplifies EDA Tool Flows" http://www.eetimes.com/showArticle.jhtml?articleID=197700473 Freescale Semiconductor has reported significant design efficiency improvements and a sizeable reduction in the number of EDA "tool flows" the semiconductor maker supports in its global development and design activities around the world. The new design milestones were achieved, in part, through a collaborative multi-year agreement that designated Cadence Design Systems as Freescale's primary EDA vendor. "It was not easy" Chekib Akrout, vice president, design technology for Freescale (Austin, TX), noted of the design system overhaul, still ongoing, that has resulted in a "streamlined tool flow" that cut the number of supported tool flows "from more than 15 to 3 or 4" across "all tools, methodologies and design groups" in its primary analog, analog-mixed signal and digital lines. "Tools reduce clock tree power by 25%, Magma claims" http://www.eetimes.com/showArticle.jhtml?articleID=197100022 Magma introduced a pair of low-power IC implementation and analysis tools that the company claims have been shown to reduce power consumption in nanometer ICs by 25 percent. Talus Power offers advanced power optimization and management techniques and a Gas Station methodology making it easier to handle complex floor plans in a multi-Vdd design flow, Magma said. Gas Stations automatically handle top-level nets that cut across switched domains by creating mini islands for the repeaters and buffers, the company said. Clock tree power reduction is achieved through a variety of optimization techniques such as power-aware buffering, sizing and flop clustering, physically aware clock-gate cloning and un-cloning, activity-based clock gating, optimal buffer insertion and balancing to minimize capacitance and minimizing skew buffers. "AMD tips quad-core performance" http://www.eetimes.com/showArticle.jhtml?articleID=197700269 Advanced Micro Devices upcoming Barcelona processor will sport floating-point performance 42 percent higher than Intel's current top-of-the line CPU, the Xeon X5355 also known as Clovertown. The news marked the first performance numbers AMD has provided for the chip that packs four Opteron cores on a single die and will be in production this fall. AMD has been under pressure from archrivals Intel and Nvidia. Intel is shipping multiple quad-core processors using a system-in"package approach, claiming it has retaken the performance lead in x86 CPUs. Nvidia shipped a new generation graphics controller last fall, a move the graphics division of AMD has not yet answered. "Integrated DFM solutions still lacking, presenter says" http://www.eetimes.com/showArticle.jhtml?articleID=197700500 EDA has done a great job of raising awareness of design-for-manufacturing (DFM) issues, but integrated DFM solutions remain scarce, according to Walter Ng, senior director of platform alliances at Chartered Semiconductor Manufacturing. "There are some good point tools out there," Ng said. "But those point tools have limited value unless we can integrate them into the flow." Ng said the alliance is pushing the vendors to include chemical mechanical polishing (CMP)-, lithography- and critical area analysis (CAA) into tool flows. Ng noted that there remains no consensus on the definition of DFM, saying that the differences in designer approaches to the problem are often dramatically different. While the conventional wisdom suggests that DFM means taking a more conservative approach to design to improve yield, some designers see it as an opportunity to do more aggressive design, Ng said. "Synthetic Biology: Scientists Gone Wild" http://bridgenews.org/news/0207/sbberserk A new report by the ETC Group concludes that the social, environmental and bio-weapons threats of synthetic biology surpass the possible dangers and abuses of biotechnology. "Call for Papers: IWLS 2007" http://www.iwls.org/ The International Workshop on Logic and Synthesis will be held May 30 - June 1, 2007 in San Diego (co-located with DAC). IWLS provides a research forum for the exchange of ideas pertaining to all aspects of synthesis, optimization, and verification of integrated circuits and systems. The emphasis is on novelty and intellectual rigor. The workshop encourages early dissemination of ideas and results. Accepted papers are distributed only to IWLS participants. Topics of interest include (but are not limited to): synthesis and optimization; power and timing analysis; testing and verification; architectures and compilation; design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged. "Realtime Garbage Collection" http://www.acmqueue.com/modules.php?name=Content&pa=printer_friendly&pid=454&page=1 Traditional computer science deals with the computation of correct results. Realtime systems interact with the physical world, so they have a second correctness criterion: they have to compute the correct result within a bounded amount of time. Simply building functionally correct software is hard enough. When timing is added to the requirements, the cost and complexity of building the software increase enormously. "Is Nanotechnology Rushing Into A Repeat Of The Biotechnology Backlash" http://www.azonano.com/Details.asp?ArticleID=1868 Global sales of nanoproducts were worth US$32 billion last year and are forecast to grow to US$1 trillion by 2011. But if you've failed to notice that the science of the small has left the lab, youre not alone. Nanotechnology is being commercialised outside of general public awareness or debate, without any serious attempt to involve the community in decision making about its introduction, and in the absence of regulatory oversight to protect workers, the public and the environment from nanotechnology's risks. "The Basics of Interlaced Video and the Techniques Used in De-interlacing" http://www.digitaltvdesignline.com/howto/showArticle.jhtml;jsessionid=3DX1JD5PMQ43GQSNDLPSKH0CJUNN2JVN?articleID=197007830 Traditional televisions use a Cathode Ray Tube, or CRT. Your TV screen is actually the end of this tube, which is painted on the inside with phosphor " a chemical that glows when hit by an electron beam. Near the front of the tube (the back of your TV), there is an 'electron gun' that sends a beam of electrons towards the screen. The electronics in the TV allow the gun to be aimed, which allows the entire front face of the tube to be 'painted' with the electron beam. This causes the front of the tube to glow, and makes the pictures we see. "The Digital Challenge: Making Easy-to-Use Devices" http://www.electronicdesign.com/yellowbrix/story.cfm?AD=1&AD=1&story_id=103646208 What makes something well designed? Millions of words have been written on the subject, but if you boil them down to basics, you end up with four questions. What does it do? How does it look? What's new about it? How will it affect the environment? "Unlicensed Communications Products and the FCC" http://www.wirelessdesignmag.com/ShowPR.aspx?PUBCODE=055&ACCT=0000100&ISSUE=0702&RELTYPE=FE&PRODCODE=00000&PRODLETT=B During the past two decades, the Federal Communications Commission has made substantial strides in encouraging the deployment of unlicensed communications networks, that is, low-power radio frequency (RF) services that are operated without FCC licenses. ============================================================================== What is Universal Serial Bus (USB) ? --------------------------------------- Dan Harmon, Texas Instruments Inc. http://www.planetanalog.com/showArticle.jhtml?articleID=197006216 ============================================================================== Special Feature ----------------- Interview with Tony Tether, the DARPA director http://blog.wired.com/defense/2007/02/tony_tether_has_1.html ============================================================================== Submission deadlines: --------------------- MWSCAS/NEWCAS'07 - Int'l Midwest Symposium on Circuits and Systems/ Int'l NEWCAS Conference Montreal, Canada Aug 5-8, 2007 Deadline: Mar 2, 2007 (extended) http://newcas.grm.polymtl.ca/ ASAP'07 - Int'l Conference on Application-specific Systems, Architectures and Processors Montreal, Canada July 9-11, 2007 Deadline: Mar 5, 2007 (extended) http://asap-conference.org/ DSD'07 - Euromicro Conference on Digital System Design Lubeck, Germany Aug 29-31, 2007 Deadline: Mar 1, 2007 http://www.dsdconf.org/ ISLPED'07 - Int'l Symposium on Low Power Electronics (sponsored by SIGDA) Portland, OR Aug. 27-29, 2007 Deadline: Mar 2, 2007 (extended) http://www.islped.org/ IWLS'07 - Int'l Workshop on Logic & Synthesis (sponsored by SIGDA) San Diego, CA May 30-Jun 1, 2007 Deadline: Mar 2, 2007 http://www.iwls.org/ PATMOS'07 - Power and Timing Modeling, Opt. & Sim. Goteborg, Sweden Sep 3-5, 2007 Deadline: Mar 5, 2007 http://www.ce.chalmers.se/research/conference/patmos07/ FPL'07 - Int'l Conference on Field-Programmable Logic and Applications Amsterdam, Holland Aug 27-29, 2007 Deadline: Mar 18, 2007 http://www.fpl.uni-kl.de/fpl/ PACT'07 - Int'l Conference on Parallel Architectures and Compilation Techniques Brasov, Romania Sep 15-19, 2007 Deadline: Mar 26, 2006 http://www.pactconf.org/ SBCCI'07 - Symposium on Integrated and Systems Design (sponsored by SIGDA) Rio de Janeiro, Brazil Sep 3-6, 2007 Deadline: Apr 2, 2007 http://www.sbcci.pads.ufrj.br/sbcci/index_sbcci.html CICC'07 - Custom Integrated Circuits Conference San Jose, CA Sep 16-19, 2007 Deadline: Apr 9, 2007 http://www.ieee-cicc.org/ ICCAD'07 - Int'l Conference on Computer-Aided Design (sponsored by SIGDA) San Jose, CA Nov 4-8, 2007 Deadline: Apr 11, 2007 http://www.iccad.com/ CODES+ISSS'07 - Int'l Conference on Hardware-Software Codesign and System Synthesis (sponsored by SIGDA) Salzburg, Austria sep 30-Oct 5, 2007 Deadline: Apr 15, 2007 http://www.codes-isss.org/ EUC'07 - Int'l Conference on Embedded and Ubiquitous Computing Taipei, Taiwan Dec 17-20, 2007 Deadline: May 17, 2007 http://csie.ntu.edu.tw/~euc07/ ICPADS'07 - Int'l Conference on Parallel and Distributed Systems Hsinchu, Taiwan Dec 5-7, 2007 Deadline: May 20, 2007 http://www.ccrc.nthu.edu.tw/icpads2007/ ============================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- GLSVLSI'07 - Great Lakes Symposium on VLSI (sponsored by SIGDA) Stresa-Largo Maggiore, Italy Mar 11-13, 2007 http://www.glsvlsi.org/ LATW'07 - Latin-American Test Workshop Peru Mar 11-14, 2007 http://www.latw.net/ ASYNC'07: Int'l Symposium on Asynchronous Circuits and Systems Berkeley, CA Mar 12-14, 2007 http://conferences.computer.org/async2007/ SLIP'07 - System Level Interconnect Prediction Workshop (sponsored by SIGDA) Austin, TX Mar 17-18, 2007 http://www.sliponline.org/ ISPD'07 - Int'l Symposium on Physical Design (sponsored by SIGDA) Austin, TX Mar 18-21, 2007 http://www.ispd.cc/ ISQED'07 - Int'l Symposium on Quality Electronic Design (sponsored by SIGDA) San Jose, CA Mar 26-28, 2007 http://www.isqed.org/ DATE'07 - Design, Automation, and Test in Europe (sponsored by SIGDA) Nice, France Apr 16-20 http://www.date-conference.com/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 http://www.nocsymposium.org/ ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 http://www.inf.ufrgs.br/isvlsi2007/ RSP'07 - Int'l Workshop on Rapid System Prototyping Porto Alegre, Brazil May 28-30, 2007 http://www.rsp-workshop.org/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 http://www.iess.org/ ICICDT'07 - Int'l Conference on IC Design & Technology Austin, TX May 30-Jun 1, 2007 http://www.icicdt.org/ MEMOCODE'07 - Int'l Conference on Formal Methods and Models for Codesign (sponsored by SIGDA) Nice, France May 30-Jun 1, 2007 http://memocode.irisa.fr/ IWLS'07 - Int'l Workshop on Logic & Synthesis (sponsored by SIGDA) San Diego, CA May 30-Jun 1, 2007 http://www.iwls.org/ MSE'07 - Int'l Conference on Microelectronic Systems Education San Diego, CA Jun 3-4, 2007 http://www.mseconference.org/ DAC'07 - Design Automation Conference (sponsored by SIGDA) San Diego, CA Jun 4-8, 2007 http://www.dac.com/ CAV'07 - Int'l Conference on Computer Aided Verification Berlin, Germany Jul 3-7, 2007 http://www.cav2007.org/ ACSD'07 - Int'l Conference on Application of Concurrency to System Design (Sponsored by SIGDA) Bratislava, Slovak Republic Jul 10-13 2007 http://www.acsd.sk/ MWSCAS/NEWCAS'07 - Int'l Midwest Symposium on Circuits and Systems/ Int'l NEWCAS Conference Montreal, Canada Aug 5-8, 2007 http://newcas.grm.polymtl.ca/ ============================================================================== Call for Papers ------------------ Special Section on Networks-on-Chips: Modeling, Analysis and Optimization IEEE Transactions on Computers seeks original manuscripts for a Special Section on Networks-on-Chip (NoCs) scheduled to appear in the August issue of 2008. Topics of interest are recent advances in all aspects of NoCs, including, but not limited to: - Synthesis, mapping, routing, scheduling - Modeling and performance analysis - Low-power, reliability, and fault-tolerant issues - Resource and QoS management. Reconfigurability. - Programming models and protocols - Synchronous and asynchronous communication. Clocking issues - Testing and benchmarking - Design flows and tools - Case studies and prototypes - Applications to multimedia, games, automotive, nano-systems, etc. Important dates: Submission Deadline: July 2, 2007 Reviews Completed: October 15, 2007 Major Revisions Due: December 14, 2007 Notification of Final Acceptance: March 14, 2008 Publication Materials for Final Manuscripts Due: April 4, 2008 GUEST EDITOR: Radu Marculescu Carnegie Mellon University Pittsburgh, PA, 15213-3890, USA radum@cmu.edu More info is available at http://csdl2.computer.org/comp/trans/tc/2007/03/t0432.pdf ============================================================================== IWLS'07 Call for Papers ------------------------ http://www.iwls.org/ The International Workshop on Logic and Synthesis will be held May 30 - June 1, 2007 in San Diego (co-located with DAC). IWLS provides a research forum for the exchange of ideas pertaining to all aspects of synthesis, optimization, and verification of integrated circuits and systems. The emphasis is on novelty and intellectual rigour. The workshop encourages early dissemination of ideas and results. Accepted papers are distributed only to IWLS participants. Topics of interest include (but are not limited to): synthesis and optimization; power and timing analysis; testing and verification; architectures and compilation; design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged. ============================================================================== Call for Papers ----------------- Special Issue: Circuits and Systems for Real-Time Security and Copyright Protection of Multimedia International Journal of Computers and Electrical Engineering (Elsevier Ltd.) (http://www.elsevier.com/wps/find/journaldescription.cws_home/367/description) Guest Editor(s): -- Saraju P. Mohanty, University of North Texas, email: smohanty@cse.unt.edu. -- Nasir Memon, Polytechnic University, email: memon@poly.edu. -- Karam S. Chatha, Arizona State University, email: kchatha@asu.edu. Following the explosive growth of the Internet, concerns about protection and enforcement of IP rights of digital content involved in transactions have been mounting. Easy unauthorized replication and manipulation with inexpensive tools has worsened the scenario. Due to this, the movie/audio industry loses several billions of dollars every year. Hence, DRM (Digital Rights Management) systems are necessary for establishing ownership rights, tracking usage, ensuring authorized access, preventing illegal replication, and facilitating content authentication. Such DRM systems may need various techniques including, encryption, watermarking, steganography, scrambling, digital certificates, secure communications protocols, etc. In the last decade, significant research progress has been made to develop these techniques which primarily work offline. However, in case of emerging applications, such as, digital television broadcasting, internet protocol television (IP-TV), video on demand, pay-TV, electronic passport (e-passport), credit cards, driving licenses, etc. security and copyright protection mechanisms have to work in real-time. Consequently, appliances, like digital cameras, network processors, mobile/video phones, graphics processing units, DVD player, etc. need to be equipped with such mechanisms. In these situations, software only solutions may not be adequate to provide real-time performance, rather hardware assisted solutions is needed for easy integration with multimedia hardware, low-power consumption, higher reliability/availability, and low-cost compared. The guest editors invite original manuscripts addressing the above challenges. The topics of research interest include, but not limited to: -- Real-time performance integrated circuits for DRM techniques. -- Operating-system and (micro) architecture-level support for security and copyright protection. -- Methods to integrate security and copyright protection mechanism in embedded architectures. -- Building SoCs such as camera, mobile phones, network processors with DRM technology. -- Building media processors, graphics processing units with DRM technology. -- Techniques for secure multimedia broadcasting in wireless systems. -- Security and copyright techniques for home entertainment, such as IP-TV and digital TV, etc. -- Techniques for real-time multimedia processing in encryption and/or watermarking domain. -- Design of side-channel-resistant embedded systems to enable attack-proof DRM development. -- Low-power DRM technology for portable appliances. Submission Information: Manuscripts should be emailed to the guest editors (smohanty@cse.unt.edu and memon@poly.edu and kchatha@asu.edu) as pdf files. The maximum page limit for a manuscript is 25 pages. The pdf file should be named using last name of the first author followed by a keyword from the paper title. For example, the filename for authors S. Mohanty and N. Memon submitting the paper titled: .On Watermarking Technique.s Developments. would be Mohanty-Watermarking. Guidelines for manuscript preparation can be found at: http://www.elsevier.com/wps/find/journaldescription.cws_home/367/authorinstructions. Schedule: -- Paper Submission Deadline: 15th June 2007 -- Notification of Acceptance or Request for Revision (if any): 15th August 2007 -- Notification of Revised Papers Acceptance: 31st August 2007 -- Camera Ready Final Version Due: 30th September 2007 -- Appearance of Special Issue: December 2007 / Early 2008 Questions and More Information: Please feel free to contact the guest editors. ============================================================================== Upcoming funding opportunities ------------------------------- NIH NLM Knowledge Management & Applied Informatics Grants Deadline: May 25, 2007 September 25, 2007 January 25, 2008 http://grants1.nih.gov/grants/guide/pa-files/PAR-07-236.html Continued Development and Maintenance of Software (R01) Deadline: May 17, 2007 September 13, 2007 http://grants1.nih.gov/grants/guide/pa-files/PAR-07-235.html NASA Applied Information Systems Research - NNH07ZDA001N-AISR Deadline: To be announced (TBA) http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId=%7B89FBF877-DD5F-AC6E-DAB3-AE19504EA70D%7D&path=open DOD Microsystems Technology Office-Wide Deadline: January 14, 2009 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07-18/Attachments.html SPINS in Semiconductors Deadline: December 31, 2008 http://fundingopps.cos.com/alerts/57993 Artificial Intelligence Technologies Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/baa.htm Quantum Information Science and Technology Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Young Investigator Program (YIP) January 12, 2008 http://www.onr.navy.mil/sci_tech/3t/corporate/yip.asp High Density Optical Memory Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Quantum Electronic Solids Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Distributed Intelligence Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF Advanced Learning Technologies (ALT) (NSF 06-535) Deadline: April 25, 2007 http://www.nsf.gov/pubs/2006/nsf06535/nsf06535.htm DARPA Cognitive Information Processing Technology (BAA02-21) Deadline: June 5, 2007 http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm DARPA Tactical Technology Office (TTO) Innovative Tactical Technologies - BAA07-20 Deadline: April 20, 2007 February 28, 2008 http://fedbizopps.cos.com/cgi-bin/getRec?id=20070223a15 James S. McDonnell Foundation Studying Complex Systems Deadline: Continuous http://www.jsmf.org/programs/cs/ ============================================================================== Call for Submissions --------------------- 10th Annual ACM/SIGDA Ph.D. Forum at DAC Tuesday, 5 June 2007 6:30-8:00 pm Sails Pavilion, San Diego Convention Center San Diego, California Submission deadline: February 16, 2007 Notification of acceptance: March 28, 2007 http://www.sigda.org/daforum/ ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ============================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To manage your subscription, go to "Subscriber's corner" on http://listserv.acm.org/ - you need to login using the email address where this newsletter is delivered. First time users will be required to choose a password.) ==============================================================================