=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membersip. Circulation: 2,700 =============================================================================== 1 January 2007 ACM/SIGDA E-NEWSLETTER Vol. 37, No. 1 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What Are Practical Applications of Statistical Static Timing Analysis? Authors: Khurana and Michael Jacobs from Cadence Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Upcoming Funding Opportunities Qinru Qiu (6) Call for Participation - SELSE-3 Workshop Silicon Errors in Logic - System Effects Cristian Constantinescu =============================================================================== Dear ACM/SIGDA members, Happy New Year! The "What is/are ...?" column for this issue is linked to the article "Practical Applications of Statistical Static Timing Analysis" by Parveen Khurana and Michael Jacobs from Cadence, which appeared in EE Times in December 2006. Besides, the "SIGDA News" column contains a number of fresh headlines. We have also updated the contents of other regular columns. We welcome Prof. Matthew Guthaus of UC Santa Cruz --- our newest associate editor responsible for transitioning the newsletter to HTML. Over the next few months, we plan to improve the page layout and enrich the newsletter with better graphics. Subscribers using older mail clients such as elm and pine should not be affected and will still receive the ASCII version of the newsletter. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Tony Givargis, E-Newsletter Associate Editor; Matthew Guthaus, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "EDA Icon Richard Newton Dies After Battling Cancer" http://eetimes.com/news/design/showArticle.jhtml?articleID=196800538&printable=true A. Richard Newton, one of the most influential founders of the electronic design automation (EDA) industry, has died of pancreatic cancer at 56. Newton, who played key roles in the formation of both Cadence Design Systems and Synopsys, was dean of the college of engineering at the University of California at Berkeley. Newton was a professor in the department of electrical engineering and computer science at Berkeley, and was the founding director of the MARCO/DARPA Gigascale Systems Research Center for design and test. Among other topics, Newton oversaw research in Spice simulation, mixed-mode simulation, and CAD frameworks. "Analyst Gary Smith: Top 10 EDA Topics for 2007" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=196702472 Veteran EDA analyst Gary Smith, founder and chief analyst of Gary Smith EDA, has provided a "top ten list" of hot topics for electronic design in 2007. Smith was Gartner Dataquest's chief EDA analyst until that firm suddenly closed its CAD research group in October 2006. The top ten topics, with explanations by Smith, follow. Smith noted that they aren't in any particular order of importance, and that the most significant, in fact, is number ten (multicore design). "EDA '07 Forecast: Strong, but Watch the Bumps" http://www.eetimes.com/news/design/showArticle.jhtml?articleID=196800350&printable=true The EDA industry grew faster than expected in 2006 and should have another good year in store, according to executives from large and small EDA companies. But a shakeout among design-for-manufacturability (DFM) startups could result in a bumpy ride, some warned. "Apple Announced iPhone and AppleTV" http://www.usatoday.com/tech/products/2007-01-09-iphone-goodies_x.htm Apple, Inc. has recently changed its official name from Apple Computer, Inc to reflect the increasing focus on consumer electronics. This week, Apple announced a new iPod/cell phone hybrid with a 3.5" screen that runs MacOS and is thinner than any such device offered by competitors. It will be offerend exclusively through AT&T Cingular Wireless starting in June. In the meantime, AppleTV, the newly renamed device that allows users to stream movies, music, photos, podcasts and TV shows to home entertainment systems, will ship in February. The 40-gigabyte machine will cost $299. "Solar Cells and The Promise of Nanotechnology" http://www.azonano.com/Details.asp?ArticleID=1815 Long touted as the solution to pollution and energy problems the world over, photovoltaic solar cells have never made a major impact on large scale electricity production. In fact, in 2000, commercial electricity production from solar, geothermal and natural heat sources only accounted for 0.5% of global supply. "5 Disruptive Technologies To Watch In 2007" http://www.embedded.com/shared/printableArticle.jhtml?articleID=196800357 2007 will be the year when a host of hot technologies which have been percolating around the mainstream rise high on the radar screens of CIOs and IT managers. "Challenges in Using Multiple Cores" http://www.eetimes.com/showArticle.jhtml?articleID=196701586 Next year promises some stepwise advances, including the advent of the first multicore benchmarks and applications programming interfaces. But in time it may also be remembered as the year the industry realized what designers of multicore software and interconnects already know: Many years of hard work lie ahead. "Newer Hardware Acceleration and Verification Systems Bringing Something New to the Table" http://www.elecdesign.com/Articles/ArticleID/14418/14418.html Hardware-based verification systems have seriously outgrown their reputation of a few years ago. They are no longer those behemoth boxes that sit in the corner of the lab for use only by a select few. They are becoming much more widely available and user-friendly . and not just for those that can afford such verification horsepower. The newer systems today are much more versatile verification systems that can be leveraged across the entire design and verification teams. These systems are not just raw performance or hardware boxes populated with the latest FPGA chips . in fact, this could not be further from the truth. "German EDA Startup Opens Silicon Valley Office" http://www.edn.com/article/CA6402954.html?ref=nbednnenews&industryid=2813 Munich-based OneSpin Solutions opened on December 1 a sales, marketing and field applications engineering office in Sunnyvale, Calif. to address what it says it growing demand for its formal verification software tools. OneSpin provides a functional register transfer-level (RTL) verification tool to allow functional sign-off for complex digital modules and intellectual property (IP) by detecting functional errors in the RTL, to ultimately save semiconductor companies millions of dollars in re-design and re-spin costs and speeding their time to market. "Solid-State PCs: Computing's Next Horizon" http://www.macnewsworld.com/story/must-read/54830.html Coming to computer stores in the not-too-distant future will be a new type of PC. It will not have a hard drive, and the operating system will be burned onto a chip, making malware manipulations and viruses problems of the past. "Unlocking Concurrency" http://www.acmqueue.com/modules.php?name=Content&pa=printer_friendly&pid=444&page=1 Multicore architectures are an inflection point in mainstream software development because they force developers to write parallel programs. In a previous article in Queue, Herb Sutter and James Larus pointed out, "The concurrency revolution is primarily a software revolution. The difficult problem is not building multicore hardware, but programming it in a way that lets mainstream applications benefit from the continued exponential growth in CPU performance." "CEO Interview: Scott McGregor of Broadcom" http://www.electronicsweekly.com/Articles/2006/12/19/40390/CEO+Interview+Scott+McGregor+of+Broadcom.htm Scott McGregor, president and CEO of Broadcom, sat down with Electronic News and Electronic Business to talk about the future of electronics, inventory glitches and new business and technology models. What follows are excerpts of that conversation. "The Top Ten Hang-ups in Digital Home Networking" http://www.eetimes.com/showArticle.jhtml?articleID=196800481 The home network is the next big frontier in electronics, but it's still untamed territory today. A few data points provide a snapshot of the opportunities. Market watcher iSuppli Corp. (El Segundo, Calif.) predicts shipments of products with integrated wired home networking will rise by more than a factor of 10 in the next four years, to hit 223.8 million units in 2010. Parks Associates estimates the number of North American homes with networked digital-video recorders more than tripled from 400,000 in 2005 to 1.7 million by the end of 2006. But there are no easy pickings in this gold rush. Engineers face historic levels of complexity building the digital home for several reasons. An unprecedented number of players are competing for a piece of the action. Coordination between these would-be architects is minimal. "Quantum Confinement Ups Optical-film Efficiency" http://www.eetimes.com/showArticle.jhtml?articleID=196800660 Researchers in China and Belgium developed new organic "chromophore" materials that are 50% more sensitive than anything previously tested. Chromophores have been prime candidates for organic dye-sensitized solar cells, since they emit electrons when light is shone on them. But the new chromophore molecular configuration incorporates quantum confinement into each cell, greatly increasing chromophore efficiency. Experts point out another possible application --- "you can coat a chip with an electro-optical polymer impregnated with dye molecules, and since the fraction of reflected polarized light is proportional to the electric field at that point in the circuit, you can effectively watch the gates turn on and off as the circuit is doing its thing." ============================================================================== What Are Practical Applications of Statistical Static Timing Analysis? ----------------------------------------------------------------------- Parveen Khurana and Michael Jacobs Cadence Design Systems, Inc. http://www.eetimes.com/showArticle.jhtml?articleID=196700482 ============================================================================== Submission deadlines: --------------------- ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 Deadline: Jan 3, 2006 (extended) http://www.inf.ufrgs.br/isvlsi2007/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 Deadline: Jan 5, 2007 (extended) http://www.iess.org/ RSP'07 - Int'l Workshop on Rapid System Prototyping Porto Alegre, Brazil May 28-30, 2007 Deadline: Jan 7,2007 http://www.rsp-workshop.org/ MSE'07 - Int'l Conference on Microelectronic Systems Education San Diego, CA Jun 3-4, 2007 Deadline: Jan 15, 2007 http://www.mseconference.org/ CAV'07 - Int'l Conference on Computer Aided Verification Berlin, Germany Jul 3-7, 2007 Deadline: Jan 28, 2007 http://www.cav2007.org/ ICICDT'07 - Int'l Conference on IC Design & Technology Austin, TX May 30-Jun 1, 2007 Deadline: Feb 15, 2007 http://www.icicdt.org/ MWSCAS/NEWCAS'07 - Int'l Midwest Symposium on Circuits and Systems/ Int'l NEWCAS Conference Montreal, Canada Aug 5-8, 2007 Deadline: Feb 20, 2007 http://newcas.grm.polymtl.ca/ IWLS'07 - Int'l Workshop on Logic & Synthesis San Diego, CA May 30-Jun 1, 2007 Deadline: Mar 2, 2007 http://www.iwls.org/ FPL'07 - Int'l Conference on Field-Programmable Logic and Applications Amsterdam, Holland Aug 27-29, 2007 Deadline: Mar 18, 2007 http://www.fpl.uni-kl.de/fpl/ PACT'07 - Int'l Conference on Parallel Architectures and Compilation Techniques Brasov, Romania Sep 15-19, 2007 Deadline: Mar 26, 2006 http://www.pactconf.org ICCAD'07 - Int'l Conference on Computer-Aided Design San Jose, CA Nov 4-8, 2007 Deadline: Apr 11, 2007 http://www.iccad.com/ ============================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- ThETA'07 - Int'l Conference on Thermal Issues in Emerging Technologies: Theory and Applications Cairo, Egypt Jan 3-6, 2007 http://www.thetaconf.org VLSI'07 - Int'l Conference on VLSI Design Bangalore, India Jan 6-10, 2007 http://www.vlsiconference.com/2007/ ASPDAC'07 - Asia and South Pacific Design Automation Conference Yokohama, Japan Jan 23-26, 2007 http://www.aspdac.com/aspdac2007/ FPGA'07 -Int'l Symposium on Field-Programmable Gate Arrays Monterey, CA Feb 18-20, 2007 http://conferences.ece.ubc.ca/isfpga2007/ TAU'07 - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Austin, TX Feb 26-27, 2007 http://www.tauworkshop.com/ SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 http://www.splconf.org/ GLSVLSI'07 - Great Lakes Symposium on VLSI Stresa-Largo Maggiore, Italy Mar 11-13, 2007 http://www.glsvlsi.org/ LATW'07 - Latin-American Test Workshop Peru Mar 11-14, 2007 http://www.latw.net/ ASYNC'07: Int'l Symposium on Asynchronous Circuits and Systems Berkeley, CA Mar 12-14, 2007 http://conferences.computer.org/async2007/ SLIP'07 - System Level Interconnect Prediction Workshop Austin, TX Mar 17-18, 2007 http://www.sliponline.org/ ISPD'07 - Int'l Symposium on Physical Design Austin, TX Mar 18-21, 2007 http://www.ispd.cc/ DATE'07 - Design, Automation, and Test in Europe Nice, France Apr 16-20 http://www.date-conference.com/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 http://www.nocsymposium.org/ ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 http://www.inf.ufrgs.br/isvlsi2007/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 http://www.iess.org/ ICICDT'07 - Int'l Conference on IC Design & Technology Austin, TX May 30-Jun 1, 2007 http://www.icicdt.org/ IWLS'07 - Int'l Workshop on Logic & Synthesis San Diego, CA May 30-Jun 1, 2007 Deadline: Mar 2, 2007 http://www.iwls.org/ MSE'07 - Int'l Conference on Microelectronic Systems Education San Diego, CA Jun 3-4, 2007 http://www.mseconference.org/ DAC'07 - Design Automation Conference San Diego, CA Jun 4-8, 2007 http://www.dac.com/ ============================================================================== Upcoming funding opportunities ------------------------------- DOD High Density Optical Memory Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Quantum Electronic Solids Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Distributed Intelligence Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Young Faculty Award Deadline: December 5, 2006 http://www.grants.gov/search/search.do?oppId=10908&mode=VIEW Experimental and Theoretical Development of Quantum Information Science Deadline: December 11, 2006 http://www.arl.army.mil/main/Main/DownloadedInternetPages/CurrentPages/DoingBusinesswithARL/research/QC06Final6Jul06.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF Theoretical Foundations 2007 (TF07) (NSF 07-525) Deadline: January 19, 2007 - February 19, 2007 http://www.nsf.gov/pubs/2007/nsf07525/nsf07525.htm Emerging Models and Technologies for Computation (EMT) (NSF 07-523) Deadline: February 14, 2007 http://www.nsf.gov/pubs/2007/nsf07523/nsf07523.htm Engineering Design (ED) Deadline: January 15, 2007 - February 15, 2007 September 1, 2007 - October 1, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13340 Computer Systems Research (CSR) (NSF 07-504) Deadline: January 17, 2007 http://www.nsf.gov/pubs/2007/nsf07504/nsf07504.htm Strategic Technologies for Cyberinfrastructure (STCI) Deadline: February 8, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=500066&org=NSF&sel_org=NSF&from=fund Software Development for Cyberinfrastructure (SDCI) (NSF 07-503) Deadline: January 22, 2007 http://www.nsf.gov/pubs/2007/nsf07503/nsf07503.htm Cyber Trust (CT) (NSF 07-500) Deadline: January 8, 2007 http://www.nsf.gov/pubs/2007/nsf07500/nsf07500.htm Information and Intelligent Systems: Advancing Human-Centered Computing, Information Integration and Informatics, and Robust Intelligence (NSF 06-572) Deadline: October 19, 2006 for Large Projects November 02, 2006 for Medium Projects December 06, 2006 for Small Projects http://www.nsf.gov/pubs/2006/nsf06572/nsf06572.htm Advanced Learning Technologies (ALT) (NSF 06-535) Deadline: April 25, 2007 http://www.nsf.gov/pubs/2006/nsf06535/nsf06535.htm DARPA Cognitive Information Processing Technology (BAA02-21) Deadline: June 5, 2007 http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm NASA Applied Information Systems Research Deadline: January 30, 2007 http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId={0B64DB41-8F7D-C949-44CD-9D04A484B653}&path=open ============================================================================== Call for Participation ------------------------ SELSE-3 Workshop, Silicon Errors in Logic - System Effects April 3rd & 4th, 2007 Austin, Texas The growing complexity and shrinking geometries of modern device technologies are making these high-density, low-voltage devices increasingly susceptible to influences from electrical noise, process variation, and natural radiation interference. System-level effects of these errors can be far reaching. Growing concern about intermittent errors, erratic storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practices in system-level error management. Participants from industry and academia explore both current technologies and future research direction (including nanotechnology). We are interested in soliciting papers that cover system-level effects of errors from a variety of perspectives: architectural, logical and circuit-level, and semiconductor processes. Case studies are also solicited. Key areas of interest are (but not limited to): * Technology trends and the impact on error rates. * New error mitigation techniques. * Characterizing the overhead and design complexity of error mitigation * techniques. * Case studies describing the engineering tradeoffs necessary to decide what * mitigation technique to apply. * Experimental data. * System-level models: derating factors and validation of error models. * Error handling protocols (higher-level protocols for robust system design). Authors are requested to submit their extended abstracts for review before December 20, 2006. Guidelines for submission are available at www.selse.org. Submissions should be PDF or Microsoft Word files that do not exceed four printed pages. Customary terms for copyright agreement and non-confidentiality will apply. Authors will be notified of paper outcome by March 2, 2007. The camera-ready formatted papers are due on March 23, 2007. Registration information is posted on the workshop website: www.selse.org Organizing committee: Workshop Co-chairs Wendy Bartlett (HP) Pia Sanda (IBM) Program Co-chairs Dennis Abts (Cray) Subhasish Mitra (Stanford) Web Chair Jeff Wilkinson (Medtronic) Publications Chair Norbert Seifert (Intel) Publicity Co-Chairs Cristian Constantinescu (Intel) Babak Falsafi (CMU) Local Arrangements Chair Nur Touba (UT Austin) Finance Co-chairs Nhon Quach (AMD) Vivian Zhu (Texas Instr) Panel Co-Chairs Ishwar Parulkar (Sun) Josep Torrellas (Univ Illinois) Advisory Committee Sarita Adve (Univ Illinois) Ravi Iyer (Univ Illinois) Chuck Moore (AMD) Lisa Spainhower (IBM) ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ============================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To manage your subscription, go to "Subscriber's corner" on http://listserv.acm.org/ - you need to login using the email address where this newsletter is delivered. First time users will be required to choose a password.) ==============================================================================