=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membersip. Circulation: 2,700 =============================================================================== 1 December 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 23 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What is SMT (Satisfiability Modulo Theories)? Contributing author: Karem Sakallah University of Michigan Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Call For Proposals - SIN'2007 Atilla Elci (6) Upcoming Funding Opportunities Qinru Qiu (7) Call For Papers - SIES 2007 José Carlos Metrôlho =============================================================================== Dear ACM/SIGDA members, In this issue, we include the new "What is SMT (Satisfiability Modulo Theories)?" column. The "SIGDA News" column contains a number of fresh headlines from our news editors. We have also updated the contents of other regular columns. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "Silicon Is a Superconductor" http://physicsweb.org/articles/news/10/11/19/1 Silicon -- the archetypal semiconductor -- has at long last been shown to demonstrate superconductivity. By substituting 9% of the silicon atoms with boron atoms, Physicists in France have found that the resistance of the material drops sharply when cooled below 0.35 K (Nature 444 465). "Synopsys Builds Supercomputer for EDA Work" http://www.hpcwire.com/hpc/1114736.html Synopsys Inc., a provider of semiconductor design software, has announced it is the first electronic design automation (EDA) company to be included on a list of sites operating the world's most powerful supercomputers. The Synopsys-built supercomputer was ranked as the 242nd most powerful supercomputer in the world based on the Linpack benchmark. The Synopsys machine was built to perform production runs with intense compute needs. Synopsys constructed the supercomputer in less than four months using commodity Linux servers, delivering up to ten times the software performance of traditional legacy computing systems in certain applications. Synopsys' supercomputer achieved benchmark results surpassing 3.7 teraflops -- roughly equivalent to 18,000 personal computers all working together at the same time to solve the same problem. "'Obvious' Patents Questioned in Supreme Court" http://www.washingtonpost.com/wp-dyn/content/article/2006/11/24/AR2006112400736.html On Nov 28, the Supreme Court is hearing arguments on what's obvious when older inventions are combined to create something new. The law says an invention that's "obvious" isn't patentable, but the definition isn't clear despite decades of litigation. Microsoft Corp., Cisco Systems Inc., Intel Corp. and other New Economy companies have filed briefs calling for a change to the system. But Johnson & Johnson, GE and DuPont, have filed their own brief arguing that major changes to the patent system would jeopardize billions of dollars invested in product innovation. "Commentary: EDA's Identity Problem" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=193700551 Stark juxtapositions in my recent travels: Last week, I was in Arizona for the second annual MEMS Executive Congress, listening to really interesting panels in which executives probed for new business opportunities. MEMS has always been next year's technology, but this time there was an optimism in the air that was undeniable. "256GB of Storage on a Sheet of Paper" http://www.techworld.com/storage/news/index.cfm?newsID=7424 Files such as text, images, sounds and video clips are encoded in "rainbow format" as coloured circles, triangles, squares and so on, and printed as dense graphics on paper at a density of 2.7GB per square inch. The paper can then be read through a specially developed scanner and the contents decoded into their original digital format and viewed or played. "Dr Google to the Rescue" http://domain-b.com/infotech/itfeature/20061121_google.htm Research in Australia indicates that Google searches can emerge as a valuable resource for physicians in diagnosing rare disorders. Akhila Thyli Hemanth reports. "Osram Makes Car Headlight From Five LEDs" http://www.electronicsweekly.com/Articles/2006/11/28/40242/Osram+makes+car+headlight+from+five+LEDs.htm Osram has revealed details of LEDs aimed specifically at vehicle headlights. The arrangement of five chips in a row simulates the low beam light pattern of conventional light sources, Osram spokeswoman Marion Reichl told EW. "Other arrangements could be possible. "EDA Sees The Very Good, The Good, And The Ugly" http://www.elecdesign.com/Articles/Index.cfm?AD=1&ArticleID=14107 Yet another growthless year for the EDA industry has passed. EDA retains its status as the mother of all enabling technologies for the global electronics industry. But like Rodney Dangerfield, it continues to get no respect. The holiday season is upon us, and many millions of highly complex ASICs and systems-on-a-chip will be sold in smartphones, video iPods, computers, cameras, and other consumer electronics. But EDA, without whose tools and design flows those ICs would never exist, remains mired as a $4 billion industry as it has for several years now. And $4 billion is rather paltry for an industry with such a vital role in the success of the worldwide electronics industry. "Nanoknives Built at NIST To Be Used to Cut Cells" http://blogs.zdnet.com/emergingtech/?p=418 Researchers at the National Institute of Standards and Technology (NIST) and the University of Colorado at Boulder (CU) have designed a carbon nanotube knife that, in theory, would work like a tight-wire cheese slicer. In a paper presented this month at the 2006 International Mechanical Engineering Congress and Exposition*, the research team announced a prototype nanoknife that could, in the future, become a tabletop tool of biology, allowing scientists to cut and study cells more precisely than they can today. To design the nanoknife, the NIST and CU scientists welded a carbon nanotube between two electrochemically sharpened tungsten needles. In the resulting prototype, the nanotube stretches between two ends of a tungsten wire loop. The knife resembles a steel wire that cuts a block of cheese. "Tic-Toc at 430-THz" http://eetimes.com/news/latest/showArticle.jhtml?articleID=196600576 A new atomic clock is based on the heavy metal strontium and uses a laser lattice to suspend super-cooled atoms. It boasts a 430-THz time base . 40,000 times faster than the current 9.19-GHz cesium-based atomic clocks. The strontium-based clock was demonstrated recently by the Commerce Department's National Institute of Standards and Technology (NIST) with help from the University of Colorado at Boulder and JILA (formerly the Joint Institute for Laboratory Astrophysics). The strontium-based approach could also serve as a storage mechanism for future quantum computers. "Java - 45%, C/C++ at 40%, and C# at 32%." http://www.eweek.com/article2/0,1895,2065392,00.asp According to Evans Data's Fall 2006 North American Development Survey, Java now holds the market penetration lead at 45 percent, followed by C/C++ at 40 percent, and C# at 32 percent. "Offshoring: Risk to U.S. Innovation?" http://www.eetimes.com/showArticle.jhtml?articleID=195900181 The U.S. engineering community is wrestling with the quickening pace of offshoring-and what, if anything, should be done about it. As they work to document the extent of offshoring in areas such as chip design, experts are trying to get their arms around globalization's implications for the engineering profession and, more important, for the future of U.S. innovation. Recent examinations of the issue by some of the profession's top thinkers have found that the United States remains the world's leader in areas like advanced chip design. But there's concern that the U.S. lead could be shrinking and that rising costs, competitive pressures and the global transmission of intellectual property are reshaping the engineering profession and the nature of innovation in ways that are just beginning to be understood. "Under Circuit Void Makes for Thinnest Chips" http://www.eetimes.com/showArticle.jhtml?articleID=196500079 The Institute for Microelectronics Stuttgart (IMS) has developed a method to create integrated circuit die that are just 20 microns thick. The institute claims these are the world's thinnest silicon chips. The work was done in cooperation with the University of Stuttgart and is the subject of late paper accepted for the forthcoming International Electron Devices Meeting (IEDM). IMS has been able to reduce the previous state-of-the-art by an order of magnitude by using a manufacturing technique to form cavities under the chips-to-be at a distance of a few micrometers beneath the wafer surface prior to the integration of the electronic circuitry. After the circuits have been formed in the top layer the chips are broken off the wafer surface rather than being diced from thinned wafers. Silicon wafers, as processed, typically have a thickness of about one millimeter in order to provide sufficient mechanical stability and stiffness for reliable processing in automated silicon process lines. Recently, there has been interest in thin chips for applications embedded in paper and on flexible foils and for stacking in three-dimensional circuits. "Si2 Seeks to Standardize and Distribute Process Design Kits" http://www.eetimes.com/showArticle.jhtml?articleID=194400734 A growing movement to bring some standardization to foundry process design kits may crack open an analog and custom IC design market long dominated by Cadence Design Systems. The kits, called PDKs, contain the design rules, device models, schematic symbols, technology files, parameterized cells (p-cells) and fixed layouts that analog and custom digital designers need to design ICs. In an initial step toward PDK standardization, the Silicon Integration Initiative (Si2) is preparing to distribute a standard symbol set that represents active and passive devices. The set, donated by Cadence, was transferred to Si2 from Accellera in June, but the OpenKit Initiative that produced it has apparently not survived. "UMC Produces 45-nm SRAM chip" http://www.eetimes.com/showArticle.jhtml?articleID=194500177 Foundry United Microelectronics Corp. has cleared a key 45-nanometer process hurdle by producing an SRAM chip with a bit cell size of less than 0.25 micron squared. To do it, engineers applied all the latest process tools, including immersion lithography, ultra shallow junctions, mobility enhancement tricks, and low-k dielectrics. UMC plans to enter pilot production of 45 nm next year. It said compared to its 65-nm process, the new 45-nm process offers a 50 percent 6-transistor SRAM cell size shrink, and a 30 percent performance gain. "Magma Buys a Yield Analysis Company" http://www.eetimes.com/showArticle.jhtml?articleID=194700054 Promising to build a new bridge between the semiconductor fabrication environment and IC design, Magma Design Automation has purchased Knights Technology, a provider of IC yield management and failure analysis software solutions since 1987. Knights Technology was a subsidiary of FEI Company, a provider of "nanotech" tools such as scanning electron microscopes. Knights offers CAD navigation and yield management software that uses manufacturing engineering systems (MES) data from the fabrication equipment used on the semiconductor foundry floor. It's an area from which EDA tools have not pulled data in the past, and it will enable a new generation of design tools, said Rajeev Madhavan, Magma CEO. "In Depth Review of Treo 680" http://mytreo.net/archives/2006/11/in-depth-review-of-treo-680.html http://reviews.cnet.com/Palm_Treo_680_Cingular/4514-6452_7-32156094.html?part=cnet&subj=Palm+Treo+680+(Cingular) The rumors started many months ago about a smaller PalmOS Treo with an internal antenna. Some of the rumors suggested that the new Treo would come in different colors and might even be less expensive than the Treo 650 or 700p. A few of these rumors proved to be true when Palm announced the upcoming release of the Treo 680, but there are still many unanswered questions such as the price and release date. It's time to put an end to the rumors, because the new Palm Treo 680 is finally here and just in time for Christmas! "BlueSpec Rolls Out Virtual Prototyping Support" http://www.eetimes.com/showArticle.jhtml?articleID=195900174 Targeting an emerging niche within electronic system-level (ESL) design, Bluespec Inc. this week will roll out a new version of its Bluesim simulator that supports virtual prototyping for software development and hardware validation. Shiv Tasker, Bluespec's CEO, said his company's constructs let users build cycle-approximate and cycle-accurate transaction-level models. That allows simulation speeds ranging between 4x and 1,000x faster than RTL simulation, he said, depending on the level of detail in the model. Bluesim doesn't support untimed transaction-level models, however; it is a two-state, cycle-accurate simulator. One of the new features in Bluesim is a direct C-language interface that is said to eliminate co-simulation overhead. George Harper, vice president of marketing at Bluespec, said users can make direct C calls, interface directly to C-language testbenches and run functional blocks that contain C-language algorithms. "Criminal Code: The Making of a Cybercriminal" http://www.acmqueue.com/modules.php?name=Content&pa=printer_friendly&pid=435&page=1 First-ever narrative chronicles one man's transition from small-time hacker to big-time crook. "BuckyBalls - A Nanotechnology Building Block, How To Make Them, History, Properties and Applications" http://www.azonano.com/Details.asp?ArticleID=1781 Just as the key building block to life on earth is the carbon atom, carbon is the key to one of the most promising branches of nanotechnology. Much of the current research and commercialisation of nanotechnology relies on tubes, wires and balls made from carbon atoms. All are known by a number of names. "HP Labs Touts Server Cooling Advances" http://www.computerworld.com/action/article.do?command=viewArticleBasic&articleId=9005486&intsrc=hm_list Hewlett-Packard Co.'s HP Labs research center has developed a new approach to cooling data centers that involves adjusting air conditioning systems to changing server loads more precisely than current systems can. "Multiflow USB Controller Optimizes Handset Data Flow" http://www.edn.com/index.asp?layout=articlePrint&articleID=CA6391010 Almost every mobile handset these days includes a target USB interface that users can employ to link a PC and the handset. For applications such as sporadically updating a handset's contacts, a relatively simple USB implementation serves well. But Cypress argues that, with more and more handsets featuring multimedia capabilities and cameras and that those features require that the USB connection be able both to achieve 480-Mbps data rates and to achieve that performance in a variety of multitasking scenarios. "Low-Cost Kits: The New FPGA-Designer Trend" http://facilities.broadcastnewsroom.com/articles/viewarticle.jsp?id=84749 In the 1970s, low-density and power-hungry TTL packages filled every digital designer's schematics. But, before long, silicon architect Ron Cline at Signetics developed the world's first PLA (programmable-logic arraya device that could pack multiple TTL functions on a single chip by configuring fuses between its AND-OR gate planes. Since that time, programmable logic has evolved to the point that today's FPGAs (field-programmable gate arrays) routinely furnish as many as 10 million gates to address complex applications, notably within the communications infrastructure. And there's no sign of any slowdown in this burgeoning market; market-research company In-Stat estimates that the $1.895 billion 2005 FPGA market will balloon to $2.7567 billion by 2010. "Commodity Processor Chaos or Convergence?" http://www.hpcwire.com/hpc/1134768.htmlIn this week's issue of HPCwire, Scott Michel's feature article -- GPGPU Computing And the Heterogeneous Multi-Core Future -- discusses how commodity accelerators like GPUs and the Cell BE processor are helping to set the stage for heterogeneous multi-core computing. In doing so he provides some context for the emerging model of heterogeneous processing. He also talks about some of the important challenges that are being confronted, including software compatibility, compiler technologies and language environments. "Shorten EDA Cycles With Storage Acceleration" http://www.elecdesign.com/Articles/ArticleID/14251/14251.html EDA users face a number of challenging constraints when designing products and the process can stress their underlying corporate information-technology (IT) infrastructure. In particular, the data-storage foundation is susceptible to limitations in a number of common scenarios. ============================================================================== What is SMT (Satisfiability Modulo Theories)? --------------------------------------------- Karem Sakallah University of Michigan Before answering this question it seems appropriate to seek an answer to the simpler question "What is Satisfiability?" Satisfiability is the problem of determining if the variables of a given Boolean function can be assigned in such a way as to make the function evaluate to 1. Equally important is to determine that no such assignments exist, implying that the function is identically 0 for all possible variable assignments. In this latter case, we would say that the function is unsatisfiable; otherwise it is satisfiable. To emphasize the binary nature of this problem, it is frequently referred to as Boolean or propositional satisfiability. The shorthand "SAT" is also commonly used to denote it, with the implicit understanding that the function and its variables are all binary-valued. The formal definition of SAT actually requires the function to be expressed in the so-called conjunctive normal form (CNF), i.e., as an AND of ORs. In this form, each OR term is called a clause and acts as a constraint on the possible values of its variables. For example the clause (A OR ~B OR C) is satisfied by all 0-1 value assignments to A, B, and C except A = C = 0 and B =1. A formula in CNF can, therefore, be viewed as a system of simultaneous constraints in the space of binary assignments to its variables. To put this in a broader context, it is useful to note the existence of other types of "systems of simultaneous constraints," such as systems of linear inequalities over real or integer variables which are used to model the set of feasible assignments (a.k.a. the feasible region) in linear and integer linear programs. The feasible region of a CNF formula contains precisely those variable assignments that make the formula evaluate to 1. SAT holds the distinction of being the first decision problem proved to be NP-complete [1, 2]. But beyond this theoretical significance, efficient and scalable algorithms for SAT that were developed over the last decade have contributed to dramatic advances in our ability to automatically solve problem instances involving tens of thousands of variables and millions of constraints. Examples of such problems in EDA include routing of FPGAs [3], combinational equivalence checking [4], model checking [5], verification of pipelined microprocessors [6], logic synthesis [7], etc. In fact, a SAT solving engine is now considered to be an essential component in the EDA toolbox and all EDA vendors provide such a capability (usually behind the scenes.) A SAT solver employs a systematic backtracking search procedure to explore the (exponentially-sized) space of variable assignments looking for satisfying assignments. The basic search procedure was proposed in two seminal papers in the early 60s [8, 9] and is now commonly referred to as the Davis-Putnam-Logemann-Loveland (DPLL) algorithm. Modern SAT solvers (developed in the last ten years) augment the basic DPLL search algorithm with efficient conflict analysis, clause learning, non-choronological backtracking (aka backjumping), as well as "two-watched-literals" unit propagation, adaptive branching, and random restarts [10-12]. These "extras" to the basic systematic search have been empirically shown to be essential for handling the large SAT instances that arise in EDA. Modern SAT solvers are also having significant impact on the fields of software verification, constraint solving in artificial intelligence, and operations research, among others. Which brings us to SMT! Formally speaking, an SMT instance is a formula in quantifier-free first-order logic, and SMT is the problem of determining whether such a formula is satisfiable. But let's not get too carried away with formalism! Imagine a Boolean SAT instance in which some of the binary variables are replaced by "predicates" over a suitable set of non-binary variables. A predicate is basically a binary-valued function of non-binary variables. Example predicates include (integer) linear inequalities (e.g., 3x + 2y . z >= 4) or equalities involving so-called uninterpreted terms and function symbols (e.g., f(f(u, v), v) = f(u, v) where f is some unspecified function of two unspecified arguments.) We are still dealing with a satisfiability problem, except that its solution now depends on our ability to determine the satisfiability of the underlying predicates. These predicates are classified according to the "theory" they belong to. For instance, linear inequalities over real variables are evaluated using the rules of the theory of linear real arithmetic, whereas predicates involving uninterpreted terms and function symbols are evaluated using the rules of the theory of uninterpreted functions with equality (sometimes referred to as the empty theory). Other commonly-encountered theories include the theories of arrays and list structures (useful for modeling and verifying software programs), and the theory of bit vectors (useful in modeling and verifying hardware designs). Subtheories are also possible: for example, difference logic is a subtheory of linear arithmetic in which each inequality is restricted to have the form x . y <= c for variables x and y and constant c. In summary, then, an SMT instance is a generalization of a Boolean SAT instance in which various sets of variables are replaced by predicates from a variety of underlying theories. Obviously, SMT formulas provide a much richer modeling language than is possible with Boolean SAT formulas. For example, an SMT formula allows us to model the datapath operations of a microprocessor at the word rather than the bit level. Still, early attempts for solving SMT instances involved translating them to Boolean SAT instances (e.g., a 32-bit integer variable would be encoded by 32 bit variables with appropriate weights and word-level operations such as 'plus' would be replaced by lower-level logic operations on the bits) and passing this (much larger) formula to a Boolean SAT solver. This approach has its merits: by pre-processing the SMT formula into an equivalent Boolean SAT formula we can use existing Boolean SAT solvers "as-is" and leverage their performance and capacity improvements over time. On the other hand, the loss of the high-level semantics of the underlying theories means that the Boolean SAT solver has to work a lot harder than necessary to discover "obvious" facts (such as x + y = y + x for integer addition.) This observation was the impetus behind the development, over the last couple of years, of a number of SMT solvers that tightly integrate the Boolean reasoning of a DPLL-style search with theory-specific solvers that handle conjunctions (ANDs) of predicates from a given theory. Dubbed DPLL(T) [13], this architecture gives the responsibility of Boolean reasoning to the DPLL-based SAT solver which, in turn, interacts with a solver for theory T through a well-defined interface. The theory solver need only worry about checking the feasibility of conjunctions of theory predicates passed on to it from the SAT solver as it explores the Boolean search space of the formula. For this integration to work well, however, the theory solver must be able to participate in propagation and conflict analysis, i.e., it must be able to infer new facts from already established facts, as well as to supply succinct explanations of infeasibility when theory conflicts arise. In other words, the theory solver must be incremental and backtrackable. An annual SMT solver competition was initiated last year and has sparked a great deal of interest among developers and users from a wide range of disciplines. Yices, the winner of this year's SMT competition (held in August at the Computer-Aided Verification conference) has all of these features, including a clever incremental Simplex algorithm for the theory of linear arithmetic that integrated quite well within the DPLL framework. As an EDA professional, consider adding SAT and SMT solvers to your arsenal of tools, and think of innovative ways of applying them in the design and verification flow. They are readily available in the public domain, and are remarkably easy to use (e.g., MiniSAT which won this year's SAT competition is roughly 600 lines of C++!). Useful Links: SAT 2007: Tenth International Conference on Theory and Applications of Satisfiability Testing (http://sat07.ecs.soton.ac.uk/) MiniSAT Page (http://www.cs.chalmers.se/Cs/Research/FormalMethods/MiniSat/MiniSat.html) SMT-LIB: The Satisfiability Module Theories Library (http://combination.cs.uiowa.edu/smtlib/) Yices: An SMT Solver (http://yices.csl.sri.com/) Selected References [1] M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness: W. H. Freeman and Company, 1979. [2] S. A. Cook, "The Complexity of Theorem Proving Procedures," in Proc. 3rd Ann. ACM Symp. on Theory of Computing, pp. 151-158, Association for Computing Machinery, 1971. [3] G.-J. Nam, K. A. Sakallah, and R. Rutenbar, "A New FPGA Detailed Routing Approach via Search-Based Boolean Satisfiability," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 6, pp. 674-684, 2002. [4] J.-P. Marques-Silva and T. Glass, "Combinational Equivalence Checking Using Satisfiability and Recursive Learning," in Proc. Design, Automation and Test in Europe Conference, pp. 145-149, 1999. [5] E. Clarke, A. Biere, R. Raimi, and Y. Zhu, "Bounded Model Checking Using Satisfiability Solving," Formal Methods in System Design, vol. 19, no. 1, 2001. [6] R. E. Bryant, S. M. German, and M. N. Velev, "Microprocessor Verification Using Efficient Decision Procedures for a Logic of Equality with Uninterpreted Functions," in Analytic Tableaux and Related Methods, pp. 1-13, 1999. [7] M. Perkowski and A. Mishchenko, "Logic Synthesis for Regular Layout using Satisfiability," in Proc. Intl Workshop on Boolean Problems, 2002. [8] M. Davis and H. Putnam, "A Computing Procedure for Quantification Theory," Journal of the Association for Computing Machinery, vol. 7, no., pp. 201-215, 1960. [9] M. Davis, G. Logemann, and D. Loveland, "A Machine Program for Theorem-Proving," Communications of the ACM, vol. 5, no. 7, pp. 394-397, 1962. [10] J. P. Marques-Silva and K. A. Sakallah, "GRASP: A Search Algorithm for Propositional Satisfiability," IEEE Transactions on Computers, vol. 48, no. 5, pp. 506-521, 1999. [11] M. W. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: engineering an efficient SAT solver," in Proc. 38th ACM/IEEE Design Automation Conference, pp. 530-535, Las Vegas, Nevada, 2001. [12] N. Een and N. Sorensson, "An Extensible SAT-solver," in Satisfiability Workshop, 2003. [13] C. Tinelli, "A DPLL-based Calculus for Ground Satisfiability Modulo Theories," in Europ. Conf. on Logic in AI (JELIA), pp., 2002. ============================================================================== Submission deadlines: --------------------- SLIP'07 - System Level Interconnect Prediction Workshop Austin, TX Mar 17-18, 2007 Deadline: Dec 1, 2006 (extended) http://www.sliponline.org/ TAU'07 - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Austin, TX Feb 26-27, 2007 Deadline: Dec 4, 2006 (extended) http://www.tauworkshop.com/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 Deadline: Dec 8, 2006 (extended) http://www.nocsymposium.org/ ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 Deadline: Dec 15, 2006 http://www.inf.ufrgs.br/isvlsi2007/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 Deadline: Dec 20, 2006 http://www.iess.org/ MSE'07 - Int'l Conference on Microelectronic Systems Education San Diego, CA Jun 3-4, 2007 Deadline: Jan 15, 2007 http://www.mseconference.org/ CAV'07 - Int'l Conference on Computer Aided Verification Berlin, Germany Jul 3-7, 2007 Deadline: Jan 28, 2007 http://www.cav2007.org/ ICICDT'07 - Int'l Conference on IC Design & Technology Austin, TX May 30-Jun 1, 2007 Deadline: Feb 15, 2007 http://www.icicdt.org/ MWSCAS/NEWCAS'07 - Int'l Midwest Symposium on Circuits and Systems/ Int'l NEWCAS Conference Montreal, Canada Aug 5-8, 2007 Deadline: Feb 20, 2007 http://newcas.grm.polymtl.ca/ IWLS'07 - Int'l Workshop on Logic & Synthesis San Diego, CA May 30-Jun 1, 2007 Deadline: Mar 2, 2007 http://www.iwls.org/ FPL'07 - Int'l Conference on Field-Programmable Logic and Applications Amsterdam, Holland Aug 27-29, 2007 Deadline: Mar 18, 2007 http://www.fpl.uni-kl.de/fpl/ PACT'07 - Int'l Conference on Parallel Architectures and Compilation Techniques Brasov, Romania Sep 15-19, 2007 Deadline: Mar 26, 2006 http://www.pactconf.org ICCAD'07 - Int'l Conference on Computer-Aided Design San Jose, CA Nov 4-8, 2007 Deadline: Apr 11, 2007 http://www.iccad.com/ ============================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- IP-SOC'06 - IP Based SoC Design Grenoble, France Dec 6-7, 2006 http://www.us.design-reuse.com/ipsoc2006/ ThETA'07 - Int'l Conference on Thermal Issues in Emerging Technologies: Theory and Applications Cairo, Egypt Jan 3-6, 2007 http://www.thetaconf.org VLSI'07 - Int'l Conference on VLSI Design Bangalore, India Jan 6-10, 2007 http://www.vlsiconference.com/2007/ ASPDAC'07 - Asia and South Pacific Design Automation Conference Yokohama, Japan Jan 23-26, 2007 http://www.aspdac.com/aspdac2007/ FPGA'07 -Int'l Symposium on Field-Programmable Gate Arrays Monterey, CA Feb 18-20, 2007 http://conferences.ece.ubc.ca/isfpga2007/ TAU'07 - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Austin, TX Feb 26-27, 2007 http://www.tauworkshop.com/ SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 http://www.splconf.org/ GLSVLSI'07 - Great Lakes Symposium on VLSI Stresa-Largo Maggiore, Italy Mar 11-13, 2007 http://www.glsvlsi.org/ LATW'07 - Latin-American Test Workshop Peru Mar 11-14, 2007 http://www.latw.net/ ASYNC'07: Int'l Symposium on Asynchronous Circuits and Systems Berkeley, CA Mar 12-14, 2007 http://conferences.computer.org/async2007/ SLIP'07 - System Level Interconnect Prediction Workshop Austin, TX Mar 17-18, 2007 http://www.sliponline.org/ ISPD'07 - Int'l Symposium on Physical Design Austin, TX Mar 18-21, 2007 http://www.ispd.cc/ DATE'07 - Design, Automation, and Test in Europe Nice, France Apr 16-20 http://www.date-conference.com/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 http://www.nocsymposium.org/ ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 http://www.inf.ufrgs.br/isvlsi2007/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 http://www.iess.org/ ICICDT'07 - Int'l Conference on IC Design & Technology Austin, TX May 30-Jun 1, 2007 http://www.icicdt.org/ IWLS'07 - Int'l Workshop on Logic & Synthesis San Diego, CA May 30-Jun 1, 2007 Deadline: Mar 2, 2007 http://www.iwls.org/ MSE'07 - Int'l Conference on Microelectronic Systems Education San Diego, CA Jun 3-4, 2007 http://www.mseconference.org/ DAC'07 - Design Automation Conference San Diego, CA Jun 4-8, 2007 http://www.dac.com/ ============================================================================== Call For Proposals -------------------- International Conference on Security of Information and Networks (SIN 2007) May 8-10, 2007 Salamis Bay Conti Resort Hotel, Gazimagusa (TRNC), North Cyprus. Proposals are invited for SIN 2007 Conference which will comprise invited talks, refereed papers, workshops and tutorials. Due dates for proposals are 31st December 2006 for workshops, 14 February 2007 for regular papers, and 21 February 2007 for tutorials proposals. Broad areas of interest in security will include, but are not limited to, the following: Access control and intrusion detection Cryptographic techniques and key management Information assurance Network security and protocols Security in information systems Security tools and development platforms Security ontology, models, protocols & policies Standards, guidelines and certification Detailed info on SIN 2007 is available at URL http://www.sinconf.org Enquiries: Atilla Elci, aelci@acm.org, T: +903926302843 F: +903923650711 Skype: atillaelci Supported by IEEE Turkey Branch & IEEE Computer Society Turkey Section. ============================================================================== Upcoming funding opportunities ------------------------------- DOD High Density Optical Memory Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Quantum Electronic Solids Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Distributed Intelligence Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Young Faculty Award Deadline: December 5, 2006 http://www.grants.gov/search/search.do?oppId=10908&mode=VIEW Experimental and Theoretical Development of Quantum Information Science Deadline: December 11, 2006 http://www.arl.army.mil/main/Main/DownloadedInternetPages/CurrentPages/DoingBusinesswithARL/research/QC06Final6Jul06.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF Theoretical Foundations 2007 (TF07) (NSF 07-525) Deadline: January 19, 2007 - February 19, 2007 http://www.nsf.gov/pubs/2007/nsf07525/nsf07525.htm Emerging Models and Technologies for Computation (EMT) (NSF 07-523) Deadline: February 14, 2007 http://www.nsf.gov/pubs/2007/nsf07523/nsf07523.htm Engineering Design (ED) Deadline: January 15, 2007 - February 15, 2007 September 1, 2007 - October 1, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13340 Computer Systems Research (CSR) (NSF 07-504) Deadline: January 17, 2007 http://www.nsf.gov/pubs/2007/nsf07504/nsf07504.htm Strategic Technologies for Cyberinfrastructure (STCI) Deadline: February 8, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=500066&org=NSF&sel_org=NSF&from=fund Software Development for Cyberinfrastructure (SDCI) (NSF 07-503) Deadline: January 22, 2007 http://www.nsf.gov/pubs/2007/nsf07503/nsf07503.htm Cyber Trust (CT) (NSF 07-500) Deadline: January 8, 2007 http://www.nsf.gov/pubs/2007/nsf07500/nsf07500.htm Information and Intelligent Systems: Advancing Human-Centered Computing, Information Integration and Informatics, and Robust Intelligence (NSF 06-572) Deadline: October 19, 2006 for Large Projects November 02, 2006 for Medium Projects December 06, 2006 for Small Projects http://www.nsf.gov/pubs/2006/nsf06572/nsf06572.htm Advanced Learning Technologies (ALT) (NSF 06-535) Deadline: April 25, 2007 http://www.nsf.gov/pubs/2006/nsf06535/nsf06535.htm DARPA Cognitive Information Processing Technology (BAA02-21) Deadline: June 5, 2007 http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm NASA Applied Information Systems Research Deadline: January 30, 2007 http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId={0B64DB41-8F7D-C949-44CD-9D04A484B653}&path=open ============================================================================== Call For Papers --------------------- SIES'2007 IEEE 2nd International Symposium on Industrial Embedded Systems July 4-6, 2007, Hotel Costa da Caparica, Lisbon, Portugal -------------------------------------------------------------------- Conference web site: http://www.uninova.pt/sies2007/ -------------------------------------------------------------------- Sponsored by: IEEE Industrial Electronics Society and Universidade Nova de Lisboa-FCT-DEE -------------------------------------------------------------------- AIM The aim of the symposium is to bring together researchers and practitioners from industry and academia and provide them with a platform to report on recent developments, deployments, technology trends and research results, as well as initiatives related to embedded systems and their applications in a variety of industrial environments. -------------------------------------------------------------------- TOPICS OF INTEREST Embedded Systems: Design and Validation of Embedded Systems; Real-Time Issues; Models of Embedded Computation and Formal Methods; HW/SW Co-Design; Design and Verification Languages; Operating Systems and Quasi-Static Scheduling; Timing and Performance Analysis; Power Aware Embedded Computing; Adaptive Embedded Systems; Security in Embedded Systems. System-on-Chip and Network-on-Chip Design & Testing: Design of Application-Specific Instruction-Set Processors; Design and Programming of Embedded Multiprocessors; SoC Communication and Architectures; NoC Communication and Architectures; Design of SoC/NoC; Platform-Based Design for Embedded Systems; Reconfigurable Platforms; Multiprocessor SoC Platforms and Tools; Testing of Embedded Core-based Integrated Circuits. Networked Embedded Systems: Design Issues for Networked Embedded; Middleware Design and Implementation for Networked Embedded Systems; Self Adaptive Networked Entity Sensor Networks: Architectures, Energy-Efficient Medium Access Control, Time Synchronization Issues, Distributed Localization Algorithms, Routing, Distributed Signal Processing, Security. Embedded Applications: Industrial Automation and Controls; Automotive Applications; Avionics Applications; Building Automation and Control; Power (Sub-)Station Automation and Control; Intelligent Sensors, etc. ; design, maintenance, fault tolerance & dependability, networks, infrastructure, safety and security. -------------------------------------------------------------------- SOLICITED PAPERS : - Long Papers: limited to 8 double column pages. - Industry Practice: limited to 8 double column pages. - Work-in-Progress: limited to 4 double column pages. -------------------------------------------------------------------- AUTHOR'S SCHEDULE: Long papers Deadline for submission of long papers: February 4, 2007 Notification of acceptance for long papers: March 18, 2007 Final manuscripts due for long papers: April 22, 2007 Work-in-Progress and Industry Practice Deadline for submission of WIP & IP papers: April 1, 2007 Notification of acceptance of WIP and IP papers: April 22, 2007 Final manuscripts due for WIP & IP papers: May 6, 2007 -------------------------------------------------------------------- SPECIAL SESSION ORGANIZATION : To enhance the technical program and focus on specific topics and areas, the SIES'2007 Symposium will include special sessions, in addition to regular ones. Special sessions can cover subjects or cross-subjects belonging to the topics of interest, or novel topics related with the ones identified within the topics of interest. Special sessions can also have the drive from specific R&D projects or clusters of projects, namely EU-sponsored R&D projects. -------------------------------------------------------------------- COMMITTEES -------------------------------------------------------------------- SIES'2007 General Co-Chairs: Luis Gomes, Univ. Nova Lisboa, Portugal Eric Dekneuvel, I3S/UNSA, France SIES'2007 Program Co-Chairs: Josi Barata, Univ. Nova Lisboa, Portugal Nicolas Navet, Loria, France Tei-Wei Kuo, National Taiwan University, Taiwan SIES'2007 Work in Progress Co-Chairs: Lucia Lo Bello, University of Catania, Italy Marcian Cirstea, Anglia Ruskin University, UK SIES'2007 Industry Liaison Committee Andrea Andenna, ABB Corporate Research, Switzerland Armando Walter Colombo, Schneider Electric, Germany Joao Miguel Fernandes (chair), Univ. Minho, Portugal Vladimir Oplustil, UNIS, Czech Replublic Jianli Xu, Nokia, Finland SIES'2007 International Advisory Committee Charles Andre, I3S/UNSA, France Giuseppe Buja, University of Padova, Italy Carlo Cecati, University of L'Aquila, Italy Carlos Couto, University of Minho, Portugal Paul Drews, APS - European Centre for Mechatronics, Germany Leopoldo Franquelo, Universidad de Sevilla, Spain A. Steiger Gargco, Univ. Nova de Lisboa, Portugal J. David Irwin, Auburn University, USA Karel Jezernik, Uni. Maribor, Slovenia Hermann Kopetz, Vienna University of Technology, Austria Ian Phillips, ARM, UK Juan Pimentel, Kettering University, USA Francoise Simonot-Lion, LORIA, France P. S. Thiagarajan, National University of Singapore, Singapore Bogdan Wilamosvski, Auburn University, USA Alex Yakovlev, Univ. Newcastle, UK Jing Bing Zhang, SIMTech, Singapore Richard Zurawski (Chair), ISA Group., USA SIES'2007 Publicity Committee Luis Almeida, Univ. Aveiro, Portugal Ricardo Machado, Univ. Minho, Portugal Josi Carlos Metrolho, I.P.Castelo Branco, Portugal Christer Norstrom, Mdlardalen University, Sweden SIES Series Steering Committee Eric Dekneuvel, I3S/UNSA , France Luis Gomes, Univ. Nova Lisboa, Portugal (chair) James C. Hung, Univ. of Tennessee, USA Richard Zurawski, ISA Group., USA SIES'2007 Publication Chair Joco Paulo Barros, ESTIG/UNL/UNINOVA, Portugal SIES'2007 Local Organizing Committee: Aniks Costa, UNL/UNINOVA, Portugal Regina Frei, Univ. Nova Lisboa, Portugal Luis Gomes, UNL/UNINOVA, Portugal Rodolfo Oliveira, UNL/UNINOVA, Portugal Rui Pais, ESTIG/UNL/UNINOVA, Portugal Rui Tavares, UNL/UNINOVA, Portugal ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. 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