=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membersip. Circulation: 2,700 =============================================================================== 15 November 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 22 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What are Carbon Nanotubes? (Reprinted from November 1 issue) Contributing author: Kaustav Banerjee University of California-Santa Barbara Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Call For Papers - SIES 2007 José Carlos Metrôlho (6) Upcoming Funding Opportunities Qinru Qiu (7) Call For Workshop Proposals - COMPSAC 2007 Atilla Elçi (8) Conference Proceedings Added to the ACM Digital Library (9) Table of Contents - the Lastest Issue of ACM Trans. on Design Automation =============================================================================== Dear ACM/SIGDA members, This issue includes the new set of SIGDA news. We have updated the lists of upcoming deadlines and events, as well as the funding opportunities. The "Call For Papers" of SIES'2007 is included. In addition, we have reprinted the "What is" column, the "Call For Workshop Proposals" of COMPSAC 2007, the table of contents for recent conference proceedigns and the table of contents for the lastest issue of TODAES. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "Intel Debuts Quad-Core Processors Ahead of AMD" http://www.edn.com/index.asp?layout=articlePrint&articleID=CA6390916 Intel Corp. today announced shipping of its first quad core processor families, the highly anticipated Quad-Core Xeon 5300 for business and Intel Core 2 Extreme quad-core for gamers. "Every Vista Computer Gets Its Own Domain Name" http://apcmag.com/node/4332 http://www.itworld.com/Comp/2218/061107msvista/index.html Every new Windows Vista computer will be given its own domain name to access files remotely. There is a catch though: to use it one must be using IPv6. Is the push for Vista also going to be the push finally to switch everything from IPv4 to IPv6? Microsoft, meanwhile, is trying to convince businesses to adopt both Vista and Office 2007 at once. "Cadence Affirms 2007 DAC Exhibit" http://www.eetimes.com/showArticle.jhtml?articleID=193600732 After a long wait and much industry speculation, Cadence Design Systems confirmed Wednesday (Nov. 8) that it has reserved booth space at the 44th Design Automation Conference (DAC) set for June 4-8, 2007 in San Diego, Calif. Cadence raised eyebrows at a meeting at this year's DAC when it failed to arrange booth space for the following year's show, as is customary for the big EDA vendors. Cadence had already scaled down its exhibit for the 2006 DAC, and a total pullout by the EDA industry's largest vendor would have had a profound impact on the EDA industry's premier conference. Gabe Moretti, editor of CMP Media's EDA DesignLine, said in his Nov. 7 blog that Lee Wood, exhibit manager of the 44th DAC, reported receiving a contract from Cadence reserving 2400 square feet of floor space for their exhibit booth. Cadence confirmed the report, noting that its booth number will be 2753. "The $100 Laptop: What Went Wrong" http://articles.moneycentral.msn.com/Investing/Extra/The100DollarLaptop.aspx Over the past few years, various initiatives have been proposed to equip Third World countries -- especially those in Africa -- with cheap computers. Believers in the concept that computers will solve all the world's ills are behind much of this. The article says: "The entire idea may be misguided and counterproductive. At least that's what Stanford journalism lecturer an Africa watcher G. Pascal Zachary thinks. The basic argument is that with $100 you could almost feed a village for a year, so why waste that sum on a laptop? What are they thinking? The fact that these people need electricity more than they need a laptop is only part of the problem. The real problem is lost mind share. The people are harmed because these sorts of schemes are sopping up mind-share time of the people who might be doing something actually useful." "Inside Sony's PlayStation 3" http://www.eetimes.com/showArticle.jhtml?articleID=194400567 Geoffrey MacGillivray, technology manager for memory at Semiconductor Insights, got hold of some of the first PS3s and videotaped as he took it apart. The article describes what he found inside and includes links to pictures and video. "Microsoft Office 2007 Already Cracked" http://www.platinax.co.uk/news/12-11-2006/microsoft-office-2007-already-cracked/ Even before final release to beta testers, cracked versions of Microsoft's completed Office 2007 have already been posted online. "Cracked software" means that the digital protections have been by-passed, often by usually a single registration key to activate a version for distibution. "Intel Researching 'Carbon Nanotubes' for Chip Design" http://www.engadget.com/2006/11/13/intel-researching-carbon-nanotubes-for-chip-design While Moore's Law has held up pretty well over the last 40 years, it may not be able to stay true forever. It turns out that as the components inside semiconductors get smaller and smaller, electrical resistance goes up, thereby reducing performance; experts say that eventually there will be a breaking point for "copper interconnects," reaching the point where Moore's Law falls apart. Scientists have been well aware of this roadblock, and have invested heavily in everything from quantum computing to optical processors. Intel is also working on a solution for this electrical engineering problem by attempting to determine whether these semiconductor interconnects can be replaced by carbon nanotubes . "Designers Give CAD Research Gurus an Earful" http://www.eetimes.com/showArticle.jhtml?articleID=193700610 There are a number of major holes in the IC design flow, and more research and development are urgently needed to fill them. That was the message at last week's International Conference on Computer-Aided Design here, as chip designers spoke of their difficulties in coping with reliability, power, clocking, statistical timing, verification and analog/ mixed-signal design. ICCAD is traditionally a conference for CAD researchers, and around 80 percent of the 127 papers came from academia. But this year the organizers decided to do something different by adding a "designer's perspectives" track. "Our goal is to bridge the gap between practitioners and research," said ICCAD general chair Soha Hassoun, an associate professor of electrical engineering and computer science at Tufts University (Medford, Mass.), in opening remarks at the conference. "We would like them [designers] to tell you [researchers] what critical issues should drive CAD research in the next few years." "Commentary: Why It's Time to Redefine ESL" http://www.eetimes.com/showArticle.jhtml?articleID=193501682 Electronic system level (ESL) has frequently been characterized as the new frontier in the EDA industry as we move to higher levels of abstraction and advanced automation. However, there have been few companies able to deliver solutions that offer the ease of adoption, robustness, and measurable value necessary to support a sustained, profitable business. This is mostly because the ESL "definition" itself has remained ambiguous, causing many to wonder - what really is ESL and will it ever deliver on its promises? "State of the Computer Book Market, Q306, Part 2" http://radar.oreilly.com/archives/2006/11/state_of_the_co_1.html The decline of Java book sales has accelerated, while C# books have continued their steady increase. When you aggregate books on both C# ".Net Languages" (books that cover both C# and VB.Net), the C# book market is now about 12% larger than Java. (Of course, some of those .Net Languages book purchasers could be buying them for their coverage of VB.) Javascript book sales are up 152% -- actually less than we expected given the new release of JavaScript this fall. If you aggregate sales of ActionScript books with JavaScript (and ActionScript is, after all, a dialect of JavaScript), it is now the 2nd largest language (after Java), in terms of book sales. (It's third if you aggregate the ".Net languages" category entirely to VB rather than to C#) "Dell Announces Quad-Core Precision, PowerEdge Systems" http://www.dailytech.com/article.aspx?newsid=4836 Dell is bringing Intel's quad-core processors to the server and workstation market with new 5300 series quad-core Xeon processors and the Core 2 Extreme quad-core QX6700 processor. Dell claims that its new Xeon 5300 series servers are 63% faster than dual-core four-socket servers and offers up to a 40% improvement in performance per watt. Likewise, the Precision 690 and 490 workstations provide up to a 54% performance increase in multi-threaded applications over comparable dual-core systems. "Sun Opens Up Source Code for Java, Claims Broader Adoption than Windows" http://www.mercurynews.com/mld/mercurynews/15984341.htm Sun Microsystems starting today is providing free access to most of the source code for its popular Java programming language. By releasing the code under the most common type of license in the open source community and relinquishing control, Sun is acknowledging the rising importance of the software development community where programmers share their code with each other for free and hoping it will help fuel the Santa Clara company's financial turnaround. Java now runs on more than 3.8 billion cell phones, smart cards, desktop computers, and other devices -- making it more widely adopted than the Windows, Linux and Solaris operating systems combined, according to Sun. Now, the world's 4 million Java developers can get a crack at most of the source code for the standard, enterprise and mobile editions of Java. The mobile edition alone contains 6 million lines of code, or 100,000 printed pages. The rest of the code is slated to be open-sourced by the end of March. "Scientific American 50: Trends in Research, Business and Policy" http://www.sciam.com/article.cfm?articleID=CA0C1B39-E7F2-99DF-3E9C70D833C09DD4 http://www.sciam.com/article.cfm?articleID=CA663E2C-E7F2-99DF-3B212D4B44CF6D05 A number of researchers, business and policy leaders are honored by Scientific American in this annual top-50 list. Technical breakthroughs of past year include self-balancing walking robots, fast sequencing of human DNA, virus-based self-assembly, single-chip quantum computers, and many others. "Unlimited Cell-phone Calling with Skype via a 3G Connection" http://crave.cnet.co.uk/mobiles/0,39029453,49285322,00.htm This new service, called X-series, is part of a new alliance made up of Skype, Sling Media, Yahoo, Nokia, Google, eBay, Microsoft, Orb and Sony Ericsson. According to the article, users will also be able to 'search Google and Yahoo, send MSN instant messages to their friends, watch their TVs from a Slingbox, access their computer at home with Orb and buy or sell stuff on eBay.' Users will only get charged a monthly fee for access, in a similar way to broadband charges." "Thinking Computers Getting More Creative" http://www.bradenton.com/mld/bradenton/business/15983762.htm For all their brainpower, computers can be dumb, misunderstanding simple instructions because they lack the intuition and flexibility of humans. Computer scientists say it's taken longer than they ever thought, but there are now examples of what approaches a thinking machine. At IBM's computational biology center in New York, a computer called Blue Gene is helping researchers study how human cells - including brain cells - operate. The machine is more than a supercomputer. It displays considerable intelligence and is even creating models to suggest how cells work, said Ajay Royyuru, senior manager at the center. "Students Write EDA Tools in One Day" http://www.eetimes.com/news/design/showArticle.jhtml?articleID=193700717 Think commercial EDA development schedules are tough? At the fifth annual CADathlon at the recent International Conference on Computer Aided Design (ICCAD), teams of students had just one day to solve selected problems by developing EDA software. "'Platform Innovation' Will Drive EDA, Speaker Says" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=193700404 The EDA industry is poised to enter a new era of innovation centered around design implementation "platforms," according to Leon Stok, director of EDA for IBM's Systems and Technology Group. Stok gave a keynote address here Wednesday (Nov. 8) at the International Conference on Computer Aided Design (ICCAD). "We are on the brink of a new era in design automation, an era that will spawn a whole new wave of innovation and excitement," Stok said. "So let us start the journey." "Low Power Raises the Heat" http://www.edn.com/index.asp?layout=article&articleid=CA6390071&ref=nbednnenews&industryid=2816 Electronic News sat down to discuss low-power design issues with Simon Bloch, general manager for the design creation and synthesis division at Mentor Graphics; Roger Carpenter, VP of strategic technology at Magma Design Automation; Vic Kulkarni, president and CEO of Sequence; and Shiv Tasker, president and CEO of Bluespec. What follows are excerpts of that conversation. "Benefits of FPGA Coprocessing" http://neasia.nikkeibp.com/neasia/005541 High-performance DSP platforms, traditionally based on general-purpose DSP processors running algorithms developed in C, have been migrating towards the use of an FPGA pre-processor or coprocessor. Doing so can provide significant performance, power, and cost advantages. Even with these considerable advantages, design teams accustomed to working on processor-based systems may avoid using FPGAs because they lack the hardware skills necessary to use one as a coprocessor. Unfamiliarity with traditional hardware design methodologies such as VHDL and Verilog limits or prevents the use of an FPGA, often resulting in more expensive and power-hungry designs. A new group of emerging design tools called ESL (electronic system level) promises to address this methodology issue, allowing processor-based developers to accelerate their designs with programmable logic while maintaining a common design methodology for hardware and software. "Logic Design Gets Scheduling Boost" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=193401200 Years of point tools have resulted in an unpredictable IC logical design flow with many iterations, according to representatives of Cadence Design Systems Inc. That company this week is promising to bring "schedule predictability" to RTL design with its Logic Design Team Solution, which provides integrated packages of the company's front-end design tools. "New-Generation Semiconductor Fabrics Need New Tools Approach" http://www.chipdesignmag.com/print.php?articleId=567?issueId=17 The growth engine of the semiconductor industry is showing a new trend line in the fabric space. At one time in the mid-'80s, we tracked custom design, gate arrays, and application-specific integrated circuits (ASICs). ASICs became the fabric of choice throughout the '90s. They continue to be the market leader in terms of power, performance, and area. Due to increasing system and silicon complexity, however, the ASIC design cost has skyrocketed. "Multiple Video Standards - No Problem, Support Them All" http://www.chipdesignmag.com/print.php?articleId=715?issueId=0 At the ARM Developers Conference, Imagination Technologies displayed both their design services and IP products. What made them standout from the crowd, which was large, were two key features that allow for rapid SOC and end product development. These two features are multi-standard support and a software support and product development environment. "Home Automation Net Challenges Insteon, ZigBee" http://www.embedded.com/shared/printableArticle.jhtml?articleID=194400231 A startup developing Wi-Fi access points announced Tuesday (Nov. 14) that it will offer free software it has developed for wireless home automation networking. "Improving The Transient Immunity of Your Microcontroller-Based Embedded Design" http://www.embedded.com/shared/printableArticle.jhtml?articleID=194300451 When it comes to protecting their designs from a variety of transient electrical disturbances, developers of microcontroller-based embedded systems in consumer, industrial, and automotive electronics are caught between the rock and the hard place. On the one hand, more sophisticated and noise-sensitive microcontrollers (MCUs), with high integration, tighter process requirements and lower voltage requirements are moving into designs that are increasingly hazardous with respect to electromagnetic interference (EMI) and electrostatic discharge (ESD). "Mixed-Signal SOC Designs Get Flash for Auto and Industrial Applications" http://www.edn.com/index.asp?layout=articlePrint&articleID=CA6390936 The term "SOC" (system on chip) typically conjures thoughts of the incredibly dense digital IC that lies at the heart of a consumer-electronics product, but designers targeting auto, industrial, and similar applications need SOCs, as well. But these applications demand complex analog functions and tolerance of high-voltage environments. AMI Semiconductor targets such needs with its 0.35-micron Smart Power SOC process for custom-IC and structured-ASIC designs, and now designers can add flash memory to such designs. ============================================================================== What are Carbon Nanotubes? ------------------------------ Kaustav Banerjee University of California-Santa Barbara Carbon materials are found in a variety of forms (known as isomers) due to the various distinct types of valence bonds that a carbon atom can form. While the diamond and graphite forms and their applications have been widely known, carbon nanotubes (CNTs) came into the limelight only in 1991 when they were experimentally observed using transmission electron microscopy by Sumio Iijima at NEC in Japan [1]. Since then, a flurry of research activities ranging from basic science to highly applied concepts related to CNTs have been reported in the literature. From a purely physics perspective, the one-dimensional nature of carbon nanotubes allows a whole new range of theoretical and experimental analysis that is not feasible with two- and three-dimensional materials. On the other hand, the outstanding properties of CNTs have made them prime candidates for future nanoelectronic devices and interconnects. CNTs exhibit extraordinary strength and unique electrical properties, and are efficient conductors of heat. In this article, I will focus on the prospects of carbon nanotubes in VLSI. As we know, VLSI is essentially CMOS (silicon) based and face several fundamental challenges-both in terms of device and interconnect (copper) scaling [2]. Metallic and Semiconducting Nanotubes A carbon nanotube is a one-atom thick sheet of graphite (called graphene) rolled up into a seamless cylinder with diameter of the order of a nanometer [3]. This results in an essentially one-dimensional nanostructure (i.e., length to diameter ratio exceeds 10,000). There are two main types of carbon nanotubes: single-walled nanotubes (SWCNTs) and multi-walled nanotubes (MWCNTs). In SWCNTs the cylindrical structure consists of a single layer of graphene with typically observed diameters < 2 nm. MWCNTs consist of multiple concentric cylinders or the graphene sheet is simply rolled in around itself resembling a scroll of parchment. Most experimentally observed CNTs are multi-walled structures with outer most shell diameters exceeding 10 nm. Since current conduction in a MWCNT is known to be mostly confined to the outermost single-walled nanotube and since band gap of a SWCNT varies inversely with its diameter, MWCNTs are metallic in nature. SWCNTs can be either metallic or semiconducting depending on the way the roll-up of the graphene sheet occurs---an aspect termed as Chirality, and if all the roll-up types are realized with equal probability, 1/3 of the SWCNTs end up being metallic and 2/3 semiconducting. Thus, when CNTs are fabricated either by arc growth, laser ablation or chemical vapor deposition (CVD), a mixture of metallic and semi-conducting nanotubes is formed. Carbon Nanotube Interconnects Metallic CNTs have aroused a lot of research interest in their applicability as VLSI interconnects of the future because of their extremely desirable properties of high mechanical and thermal stability, high thermal conductivity and large current carrying capacity [4, 5]. An isolated CNT can carry current densities in excess of 1000 MA/sq-cm without any signs of damage even at an elevated temperature of 250 degree C, thereby eliminating electromigration reliability concerns that plague Cu interconnects. Recent modeling work comparing the performance, power dissipation and thermal/reliability aspects of CNT interconnect to scaled copper interconnects have shown that CNT bundle interconnects can potentially offer significant advantages over copper [6, 7]. Additionally, the concept of hybrid CNT/Cu interconnects-employing CNT vias in tandem with copper interconnects has been shown to offer remarkable advantages from a reliability/thermal-management perspective [7]. More information on state-of-the-art of CNT interconnects (including their fabrication) can be found in [8, 9]. Carbon Nanotube Transistors Semiconducting CNTs have been used to fabricate field effect transistors (CNTFETs), which show tremendous promise due to their superior electrical characteristics over silicon based MOSFETs [10, 11]. Since electron mean free path in SWCNTs can exceed 1 micrometer, CNTFETs exhibit near-ballistic transport characteristics resulting in very high speed devices. In fact, CNT devices are projected to be operational in the frequency range of hundreds of GHz [12]. Recent work detailing the advantages and disadvantages of various forms of CNTFETs have also shown that the tunneling based CNTFET offers significantly better characteristics compared to other CNTFET structures [13]. This device has been found to be superior in terms of subthreshold slope--a very important property for low power applications. Design and Design Automation Challenges Although CNT devices and interconnects have been separately shown to be promising in their own respects, there have been few efforts to successfully combine them in a realistic circuit. Most CNTFET structures employ the silicon substrate as a back gate. Applying different back gate voltages might become a concern when designing large circuits out of these devices. Several top-gated structures have also been demonstrated, which can alleviate this concern [14, 15]. Recently, a fully integrated logic circuit built on a single nanotube has been reported [16]. However, this circuit also employs a back-gate. Additionally, there are still several process related challenges that need to be addressed before CNT-based devices and interconnects can enter mainstream VLSI process. This makes it an exciting and open field for research. Problems like purification, separation of carbon nanotubes, control over nanotube length, chirality and desired alignment, low thermal budget as well as high contact resistance are yet to be fully resolved. Although these are serious technological challenges, innovative ideas have been proposed to build practical transistors out of nano-networks [17]. Since lack of control on chirality produces a mix of metallic as well as semiconducting CNTs from any fabrication process and it is difficult to control the growth direction of the CNTs, random arrays of SWCNTs (that are easily produced) have been proposed to build thin film transistors [17]. This idea can be further exploited to build practical CNT based transistors and circuits without the need for precise growth and assembly. Finally, while it is important to have physical implementations of large CNT circuits, it is also imperative to develop the ability to perform detailed modeling, analysis and simulation of such circuits. Not only will this require a correct understanding of the physics of these individual devices and interconnects, but will also present significant challenges in terms of novel design automation techniques that can comprehend effects such as uncertainties and variations in design parameters (due to lack of control) as well as probabilistic designs (such as in nano-networks). Moreover, the outstanding thermal conductivity of CNTs and their mesoscopic properties can be exploited to address a variety of key technological issues including chip-level thermal management as well as design of ultra high-density passive circuit elements (such as capacitors and inductors) that are widely employed in high-frequency mixed-signal and radio-frequency ICs. The CNT interconnect structures also offer exciting prospects for system level architectural innovations including design of ultra high-bandwidth networks-on-chip, very low-latency memory addressing, and robust power distribution networks. References: [1] S. Iijima, "Helical Microtubules of Graphitic Carbon," Nature, Vol. 354, pp. 56-58, 1991. [2] ITRS, "International Technology Roadmap for Semiconductors-2005 edition," SIA, Available online: http://www.itrs.net 2005. [3] M.S. Dresselhaus, G. Dresselhaus and Ph. Avouris, Editors, Carbon Nanotubes: Synthesis, Structure, Properties and Applications, Springer-Verlag, 2000. [4] F. Kreupl, et al., "Carbon Nanotubes in Interconnect Applications," Microelectronic Engineering, 64, pp. 399-408, 2002. [5] J. Li, et al., "Bottom-up Approach for Carbon Nanotube Interconnects," Applied Physics Letters, Vol. 82, No. 15, pp. 2491-2493, April 2003. [6] N. Srivastava and K. Banerjee, "Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications," ICCAD, 2005, pp. 383-390. [7] N. Srivastava, R.V. Joshi and K. Banerjee, "Carbon Nanotube Interconnects: Implications for Performance, Power Dissipation and Thermal Management," IEDM, 2005, pp. 257-260. [8] K. Banerjee and N. Srivastava, "Are Carbon Nanotubes the future of VLSI Interconnections?", ACM Design Automation Conference, 2006, pp. 809-814. [9] K. Banerjee, S. Im and N. Srivastava, "Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?" IEEE Nano Networks Conference, 2006. [10] P. Avouris, et al., "Carbon Nanotube Electronics," Proc. IEEE, Vol. 91, pp. 1772-1784, 2003. [11] S. Wind, J. Appenzeller, and P. Avouris, "Lateral scaling in CN fieldeffect transistors," Phys. Rev. Lett., Vol. 91, pp. 058 301-1-058 301-4, 2003. [12] S. Hasan, S. Salahuddin, M. Vaidyanathan and M. A. Alam, "High-Frequency Performance Projections for Ballistic Carbon-Nanotube Transistors," IEEE Transactions on Nanotechnology, Vol. 5, No. 1, pp. 14-22, 2006. [13] J. Appenzeller, et al., "Comparing Carbon Nanotube Transistors - The Ideal Choice: A Novel Tunneling Device Design," IEEE TED, Vol. 52, No. 12, pp. 2568-2576, 2005. [14] S. J. Wind, J. Appenzeller, R. Martel, V. Derycke and Ph. Avouris, "Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes," Applied Physics Letters, Vol. 80, No. 20, 3817 - 3819, 2002. [15] D. V. Singh, K. A. Jenkins, J. Appenzeller, D. Neumayer, A. Grill and H.-S. P. Wong, "Frequency Response of Top-Gated Carbon Nanotube Field-Effect Transistors," IEEE Transactions on Nanotechnology, Vol. 3, No. 3, pp. 383-387, 2004. [16] Z. Chen, J. Appenzeller, Y.-M. Lin, J. Sippel-Oakley, A. G. Rinzler, J. Tang, S. J. Wind, P. M. Solomon and Ph. Avouris, "An Integrated Logic Circuit Assembled on a Single Carbon Nanotube," Science, Vol. 311, p. 1735, 2006. [17] E. S. Snow, J. P. Novak, P. M. Campbell, and D. Park "Random networks of carbon nanotubes as an electronic material," Applied Physics Letters, Vol. 82, No. 13, pp. 2145 - 2147, 2003. ============================================================================== Submission deadlines: --------------------- GLSVLSI'07 - Great Lakes Symposium on VLSI Stresa-Largo Maggiore, Italy Mar 11-13, 2007 Deadline: Nov 17, 2006 (extended) http://www.glsvlsi.org/ LATW'07 - Latin-American Test Workshop Peru Mar 11-14, 2007 Deadline: Nov 12, 2006 http://www.latw.net/ DAC'07 - Design Automation Conference San Diego, CA Jun 4-8, 2007 Deadline: Nov. 20, 2006 http://www.dac.com/ SLIP'07 - System Level Interconnect Prediction Workshop Austin, TX Mar 17-18, 2007 Deadline: Nov 24, 2006 http://www.sliponline.org/ TAU'07 - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Austin, TX Feb 26-27, 2007 Deadline: Nov 27, 2006 http://www.tauworkshop.com/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 Deadline: Dec 1, 2006 http://www.nocsymposium.org/ ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 Deadline: Dec 15, 2006 http://www.inf.ufrgs.br/isvlsi2007/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 Deadline: Dec 20, 2006 http://www.iess.org/ MSE'07 - Int'l Conference on Microelectronic Systems Education San Diego, CA Jun 3-4, 2007 Deadline: Jan 15, 2007 http://www.mseconference.org/ ICICDT'07 - Int'l Conference on IC Design & Technology Austin, TX May 30-Jun 1, 2007 Deadline: Feb 15, 2007 http://www.icicdt.org/ ============================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- CSS'06 - Conference on Circuits, Signals and Systems San Francisco, CA Nov 20-22, 2006 http://www.iasted.org/newsletter/2006/css2.htm IP-SOC'06 - IP Based SoC Design Grenoble, France Dec 6-7, 2006 http://www.us.design-reuse.com/ipsoc2006/ ThETA'07 - Int'l Conference on Thermal Issues in Emerging Technologies: Theory and Applications Cairo, Egypt Jan 3-6, 2007 http://www.thetaconf.org VLSI'07 - Int'l Conference on VLSI Design Bangalore, India Jan 6-10, 2007 http://www.vlsiconference.com/2007/ ASPDAC'07 - Asia and South Pacific Design Automation Conference Yokohama, Japan Jan 23-26, 2007 http://www.aspdac.com/aspdac2007/ FPGA'07 -Int'l Symposium on Field-Programmable Gate Arrays Monterey, CA Feb 18-20, 2007 http://conferences.ece.ubc.ca/isfpga2007/ TAU'07 - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Austin, TX Feb 26-27, 2007 http://www.tauworkshop.com/ SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 http://www.splconf.org/ GLSVLSI'07 - Great Lakes Symposium on VLSI Stresa-Largo Maggiore, Italy Mar 11-13, 2007 http://www.glsvlsi.org/ LATW'07 - Latin-American Test Workshop Peru Mar 11-14, 2007 http://www.latw.net/ ASYNC'07: Int'l Symposium on Asynchronous Circuits and Systems Berkeley, CA Mar 12-14, 2007 http://conferences.computer.org/async2007/ SLIP'07 - System Level Interconnect Prediction Workshop Austin, TX Mar 17-18, 2007 http://www.sliponline.org/ ISPD'07 - Int'l Symposium on Physical Design Austin, TX Mar 18-21, 2007 http://www.ispd.cc/ DATE'07 - Design, Automation, and Test in Europe Nice, France Apr 16-20 http://www.date-conference.com/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 http://www.nocsymposium.org/ ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 http://www.inf.ufrgs.br/isvlsi2007/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 http://www.iess.org/ ICICDT'07 - Int'l Conference on IC Design & Technology Austin, TX May 30-Jun 1, 2007 http://www.icicdt.org/ MSE'07 - Int'l Conference on Microelectronic Systems Education San Diego, CA Jun 3-4, 2007 http://www.mseconference.org/ DAC'07 - Design Automation Conference San Diego, CA Jun 4-8, 2007 http://www.dac.com/ ============================================================================== Call For Papers --------------------- SIES'2007 IEEE 2nd International Symposium on Industrial Embedded Systems July 4-6, 2007, Hotel Costa da Caparica, Lisbon, Portugal -------------------------------------------------------------------- Conference web site: http://www.uninova.pt/sies2007/ -------------------------------------------------------------------- Sponsored by: IEEE Industrial Electronics Society and Universidade Nova de Lisboa-FCT-DEE -------------------------------------------------------------------- AIM The aim of the symposium is to bring together researchers and practitioners from industry and academia and provide them with a platform to report on recent developments, deployments, technology trends and research results, as well as initiatives related to embedded systems and their applications in a variety of industrial environments. -------------------------------------------------------------------- TOPICS OF INTEREST Embedded Systems: Design and Validation of Embedded Systems; Real-Time Issues; Models of Embedded Computation and Formal Methods; HW/SW Co-Design; Design and Verification Languages; Operating Systems and Quasi-Static Scheduling; Timing and Performance Analysis; Power Aware Embedded Computing; Adaptive Embedded Systems; Security in Embedded Systems. System-on-Chip and Network-on-Chip Design & Testing: Design of Application-Specific Instruction-Set Processors; Design and Programming of Embedded Multiprocessors; SoC Communication and Architectures; NoC Communication and Architectures; Design of SoC/NoC; Platform-Based Design for Embedded Systems; Reconfigurable Platforms; Multiprocessor SoC Platforms and Tools; Testing of Embedded Core-based Integrated Circuits. Networked Embedded Systems: Design Issues for Networked Embedded; Middleware Design and Implementation for Networked Embedded Systems; Self Adaptive Networked Entity Sensor Networks: Architectures, Energy-Efficient Medium Access Control, Time Synchronization Issues, Distributed Localization Algorithms, Routing, Distributed Signal Processing, Security. Embedded Applications: Industrial Automation and Controls; Automotive Applications; Avionics Applications; Building Automation and Control; Power (Sub-)Station Automation and Control; Intelligent Sensors, etc. ; design, maintenance, fault tolerance & dependability, networks, infrastructure, safety and security. -------------------------------------------------------------------- SOLICITED PAPERS : - Long Papers: limited to 8 double column pages. - Industry Practice: limited to 8 double column pages. - Work-in-Progress: limited to 4 double column pages. -------------------------------------------------------------------- AUTHOR'S SCHEDULE: Long papers Deadline for submission of long papers: February 4, 2007 Notification of acceptance for long papers: March 18, 2007 Final manuscripts due for long papers: April 22, 2007 Work-in-Progress and Industry Practice Deadline for submission of WIP & IP papers: April 1, 2007 Notification of acceptance of WIP and IP papers: April 22, 2007 Final manuscripts due for WIP & IP papers: May 6, 2007 -------------------------------------------------------------------- SPECIAL SESSION ORGANIZATION : To enhance the technical program and focus on specific topics and areas, the SIES'2007 Symposium will include special sessions, in addition to regular ones. Special sessions can cover subjects or cross-subjects belonging to the topics of interest, or novel topics related with the ones identified within the topics of interest. Special sessions can also have the drive from specific R&D projects or clusters of projects, namely EU-sponsored R&D projects. -------------------------------------------------------------------- COMMITTEES -------------------------------------------------------------------- SIES'2007 General Co-Chairs: Luis Gomes, Univ. Nova Lisboa, Portugal Eric Dekneuvel, I3S/UNSA, France SIES'2007 Program Co-Chairs: Josi Barata, Univ. Nova Lisboa, Portugal Nicolas Navet, Loria, France Tei-Wei Kuo, National Taiwan University, Taiwan SIES'2007 Work in Progress Co-Chairs: Lucia Lo Bello, University of Catania, Italy Marcian Cirstea, Anglia Ruskin University, UK SIES'2007 Industry Liaison Committee Andrea Andenna, ABB Corporate Research, Switzerland Armando Walter Colombo, Schneider Electric, Germany Joao Miguel Fernandes (chair), Univ. Minho, Portugal Vladimir Oplustil, UNIS, Czech Replublic Jianli Xu, Nokia, Finland SIES'2007 International Advisory Committee Charles Andre, I3S/UNSA, France Giuseppe Buja, University of Padova, Italy Carlo Cecati, University of L'Aquila, Italy Carlos Couto, University of Minho, Portugal Paul Drews, APS - European Centre for Mechatronics, Germany Leopoldo Franquelo, Universidad de Sevilla, Spain A. Steiger Gargco, Univ. Nova de Lisboa, Portugal J. David Irwin, Auburn University, USA Karel Jezernik, Uni. Maribor, Slovenia Hermann Kopetz, Vienna University of Technology, Austria Ian Phillips, ARM, UK Juan Pimentel, Kettering University, USA Francoise Simonot-Lion, LORIA, France P. S. Thiagarajan, National University of Singapore, Singapore Bogdan Wilamosvski, Auburn University, USA Alex Yakovlev, Univ. Newcastle, UK Jing Bing Zhang, SIMTech, Singapore Richard Zurawski (Chair), ISA Group., USA SIES'2007 Publicity Committee Luis Almeida, Univ. Aveiro, Portugal Ricardo Machado, Univ. Minho, Portugal Josi Carlos Metrolho, I.P.Castelo Branco, Portugal Christer Norstrom, Mdlardalen University, Sweden SIES Series Steering Committee Eric Dekneuvel, I3S/UNSA , France Luis Gomes, Univ. Nova Lisboa, Portugal (chair) James C. Hung, Univ. of Tennessee, USA Richard Zurawski, ISA Group., USA SIES'2007 Publication Chair Joco Paulo Barros, ESTIG/UNL/UNINOVA, Portugal SIES'2007 Local Organizing Committee: Aniks Costa, UNL/UNINOVA, Portugal Regina Frei, Univ. Nova Lisboa, Portugal Luis Gomes, UNL/UNINOVA, Portugal Rodolfo Oliveira, UNL/UNINOVA, Portugal Rui Pais, ESTIG/UNL/UNINOVA, Portugal Rui Tavares, UNL/UNINOVA, Portugal ============================================================================== Upcoming funding opportunities ------------------------------- ASEE Office of Naval Research (ONR) Summer Faculty Research Program Deadline: December 1, 2006 http://www.asee.org/fellowships/summer/index.cfm DOD High Density Optical Memory Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Quantum Electronic Solids Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Distributed Intelligence Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Young Faculty Award Deadline: December 5, 2006 http://www.grants.gov/search/search.do?oppId=10908&mode=VIEW Experimental and Theoretical Development of Quantum Information Science Deadline: December 11, 2006 http://www.arl.army.mil/main/Main/DownloadedInternetPages/CurrentPages/DoingBusinesswithARL/research/QC06Final6Jul06.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF Computer Systems Research (CSR) (NSF 07-504) Deadline: January 17, 2007 http://www.nsf.gov/pubs/2007/nsf07504/nsf07504.htm Strategic Technologies for Cyberinfrastructure (STCI) Deadline: February 8, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=500066&org=NSF&sel_org=NSF&from=fund Software Development for Cyberinfrastructure (SDCI) (NSF 07-503) Deadline: January 22, 2007 http://www.nsf.gov/pubs/2007/nsf07503/nsf07503.htm Cyber Trust (CT) (NSF 07-500) Deadline: January 8, 2007 http://www.nsf.gov/pubs/2007/nsf07500/nsf07500.htm NSF-SIA/NRI Graduate Student and Postdoctoral Fellow Supplements to NSF Centers in Nanoelectronics (NSF 06-051) Deadline: November 17, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=501009&org=CISE&from=home Information and Intelligent Systems: Advancing Human-Centered Computing, Information Integration and Informatics, and Robust Intelligence (NSF 06-572) Deadline: October 19, 2006 for Large Projects November 02, 2006 for Medium Projects December 06, 2006 for Small Projects http://www.nsf.gov/pubs/2006/nsf06572/nsf06572.htm Active Nanostructures and Nanosystems (ANN) (NSF 06-595) Deadline: November 15, 2006 http://www.nsf.gov/pubs/2006/nsf06595/nsf06595.htm Advanced Learning Technologies (ALT) (NSF 06-535) Deadline: April 25, 2007 http://www.nsf.gov/pubs/2006/nsf06535/nsf06535.htm DARPA Cognitive Information Processing Technology (BAA02-21) Deadline: June 5, 2007 http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm NASA Applied Information Systems Research Deadline: January 30, 2007 http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId={0B64DB41-8F7D-C949-44CD-9D04A484B653}&path=open ============================================================================== CALL FOR WORKSHOP PROPOSALS ------------------------------- COMPSAC is a major international forum for researchers, practitioners, managers, and policy makers interested in computer software and applications. Starting with 2006, COMPSAC is designated as the IEEE Computer Society Signature Conference on Software Technology and Applications. Based on this designation COMPSAC organizers are able to work with other key functions of the Computer Society to create more values for the conference volunteers and participants. Proposals for workshops are solicited for consideration of affiliation with COMPSAC 2007. Affiliated workshops will be held in conjunction and co-located with the conference and other affiliated workshops. The purpose of these workshops is to provide a platform for presenting novel ideas in a less formal and possibly more focused way than the conference itself. As such, they also offer a good opportunity for young researchers to present their work and to obtain feedback from an interested community. Workshop organizers are responsible for establishing a program committee, collecting and evaluating submissions, notifying authors of acceptance or rejection in due time, and ensuring a transparent and fair selection process, organizing selected papers into sessions, and assigning session chairs. Researchers and practitioners are invited to submit a one-page concept paper proposing a workshop to the 31st COMPSAC Workshop Chair, Atilla Elci (atilla.elci@emu.edu.tr), by Dec. 8, 2006. Submission may be made by e-mail with "COMPSAC Preliminary Workshop Proposal" in the subject header and supplying data on the Preliminary Workshop Proposal Format. Feedback will be provided to the workshop proposers by Dec. 15, 2006. An accepted proposal will then be detailed using the Final Workshop Proposal Format by its organizers. Other important due dates are mentioned below. The selection of the workshops to be included in the final COMPSAC program will be based upon several factors, including the scientific / technical interest of the topics, the quality of the proposal, balance and distinctness of workshop topics, and the capacity of the conference workshop program. Workshops use the same paper submission system with COMPSAC 2007. Proceedings of the COMPSAC Workshops will be printed as a separate volume by IEEE Computer Society Press to be made available to all conference registrants on site. All workshop papers will as well be electronically available through IEEE Xplore Digital Database. Any further information needed for preparing a workshop proposal can be obtained by contacting the COMPSAC Workshop Chair. 31st COMPSAC web site, too, (http://www.compsac.org/) is a source of first hand information. 31st COMPSAC Preliminary Workshop Proposal Format (Limited to 1-page, typed double space in 11 pt Times New Roman) Workshop title: ... Primary organizers, their affiliation, and contact details: ... Proposed duration (select one: 1 / 2 / 3 / 4 sessions; 1 session=90 minutes): ... A statement of goals for the workshop: ... Workshop theme: ... Likely participants: ... 31st COMPSAC Final Workshop Proposal Format (Limited to 3-pages, typed double space in 11 pt Times New Roman) Workshop title: ... Primary organizers, their affiliation, and contact details: ... Proposed duration (select one: 1 / 2 / 3 / 4 sessions; 1 session=90 minutes): ... A statement of goals for the workshop: ... Workshop theme: ... Likely participants: ... Description of the workshop: suggested items are as follows: expected achievements, importance, program committee, format (paper presentations, discussion sessions, etc.), plans for call for papers / participation, plans for publicity,... 31st COMPSAC important dates for workshops Dec. 08, 2006: Preliminary Workshop Proposal submission Dec. 15, 2006: Feedback provided to the workshop proposers Dec. 31, 2006: Final workshop proposal submission Feb. 23, 2007: Full paper and short paper due Mar. 15, 2007: Decision notification (electronic) Apr. 15, 2007: Camera-ready copy and author registration due Note: The 31st COMPSAC Steering Committee will allocate sessions to each workshop within the constraints of space availability and the likely interest of the attendees in the workshop. Please be advised to organize your workshop early and request for adequate space as soon as your effort turns out to be fruitful. The COMPSAC Workshop Chair will work closely with the primary organizers to ensure a successful workshop. Issue Date: Oct. 16, 2006. ============================================================================== Conference Proceedings Added to the ACM Digital Library --------------------------------------------------------- Proceedings of the following conferences are now available in the ACM Digital Library. http://portal.acm.org/dl.cfm GECCO 2006 ICCAD 2005 FPGA 2005 DATE 2005 DAC 2005 GLSVLSI 2005 ISLPED 2005 ============================================================================== Table of Contents - the Lastest Issue of ACM Trans. on Design Automation ------------------------------------------------------------------------ Introduction to special issue: Novel paradigms in system-level design Massoud Pedram Pages: 535 - 536 http://delivery.acm.org/10.1145/1150000/1142981/p535-introduction.pdf?key1=1142981&key2=0056121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 System level design paradigms: Platform-based design and communication synthesis Alessandro Pinto, Alvise Bonivento, Allberto L. Sangiovanni-Vincentelli, Roberto Passerone, Marco Sgroi Pages: 537 - 563 http://delivery.acm.org/10.1145/1150000/1142982/p537-pinto.pdf?key1=1142982&key2=6256121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Computation and communication refinement for multiprocessor SoC design: A system-level perspective Radu Marculescu, Umit Y. Ogras, Nicholas H. Zamora Pages: 564 - 592 http://delivery.acm.org/10.1145/1150000/1142983/p564-marculescu.pdf?key1=1142983&key2=9356121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Analysis and optimization of distributed real-time embedded systems Paul Pop, Petru Eles, Zebo Peng, Traian Pop Pages: 593 - 625 http://delivery.acm.org/10.1145/1150000/1142984/p593-pop.pdf?key1=1142984&key2=1656121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs Prabhat Mishra, Aviral Shrivastava, Nikil Dutt Pages: 626 - 658 http://delivery.acm.org/10.1145/1150000/1142985/p626-mishra.pdf?key1=1142985&key2=0856121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Warp Processors Roman Lysecky, Greg Stitt, Frank Vahid Pages: 659 - 681 http://delivery.acm.org/10.1145/1150000/1142986/p659-lysecky.pdf?key1=1142986&key2=6956121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Module placement for fault-tolerant microfluidics-based biochips Fei Su, Krishnendu Chakrabarty Pages: 682 - 710 http://delivery.acm.org/10.1145/1150000/1142987/p682-su.pdf?key1=1142987&key2=2166121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing Narender Hanchate, Nagarajan Ranganathan Pages: 711 - 739 http://delivery.acm.org/10.1145/1150000/1142988/p711-hanchate.pdf?key1=1142988&key2=1366121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Simultaneous placement with clustering and duplication Gang Chen, Jason Cong Pages: 740 - 772 http://delivery.acm.org/10.1145/1150000/1142989/p740-chen.pdf?key1=1142989&key2=0566121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan Pages: 773 - 796 http://delivery.acm.org/10.1145/1150000/1142990/p773-bhanja.pdf?key1=1142990&key2=4666121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. 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