=============================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org =============================================================================== 1 November 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 21 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What are Carbon Nanotubes? Contributing author: Kaustav Banerjee University of California-Santa Barbara Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Final Call For Papers - GLSVLSI 2007 Hai Zhou (6) Call For Workshop Proposals - COMPSAC 2007 Atilla Elçi (7) Upcoming Funding Opportunities Qinru Qiu (8) Conference Proceedings Added to the ACM Digital Library (9) Table of Contents - the Lastest Issue of ACM Trans. on Design Automation =============================================================================== Dear ACM/SIGDA members, This issue includes the new "What are Carbon Nanotubes?" column and a fresh batch of SIGDA news. We updated the lists of upcoming deadlines and events, as well as the funding opportunities. The final call for papers of GLSVLSI and the call for workshop proposals of COMPSAC are also included. We have also reprinted the table of contents for recent conference proceedigns and the table of contents for the lastest issue of TODAES. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "Pentagon Urges 'Relevant' R&D" http://www.eetimes.com/showArticle.jhtml?articleID=193400997 The U.S. military will need contractors to concentrate more on relevant technology that troops will be able to use while battling insurgents in places such as Iraq and Afghanistan. In the immediate future, high-risk and high-payoff research will be less of a focus. Fiscal 2006 was a record-setting year for spending on military R&D, but technology spending has reached a plateau and is likely to fall in the years to come, says Boeing's Cecil Black, who oversaw the DOD spending forecast that the Government Electronics and Information Technology Association (GEIA) released last week. The military has a budget of $435.6 billion for fiscal 2007, and much of the spending will go toward developing missile defenses and a U.S. space force, in addition to "transformational technologies" that connect commanders to troops in the streets. "44th Design Automation Conference Adds New 'Wild and Crazy Ideas' Track and Automotive Electronics Theme" http://home.businesswire.com/portal/site/google/index.jsp?ndmViewId=news_view&newsId=20061018005326&newsLang=en The 44th Design Automation Conference (DAC) has added a new "Wild and Crazy Ideas" (WACI) track and a special Automotive Electronics theme to make the electronic design automation (EDA) industry's premier event even more valuable for the more than 11,000 developers, designers, researchers, managers and engineers from leading electronics companies and universities around the world who attend. Papers are invited for the WACI track to provide an opportunity for the electronic design community to share new, forward-looking technical ideas that have yet to be fully developed and proven. Unlike traditional DAC technical paper submissions, which explore specific technology issues and outline a complete solution, WACI papers allow presenters to share novel ideas in their early stages. "Benefits of FPGA Coprocessing" http://neasia.nikkeibp.com/neasia/005541 High-performance DSP platforms, traditionally based on general-purpose DSP processors running algorithms developed in C, have been migrating towards the use of an FPGA pre-processor or coprocessor. Doing so can provide significant performance, power, and cost advantages. Even with these considerable advantages, design teams accustomed to working on processor-based systems may avoid using FPGAs because they lack the hardware skills necessary to use one as a coprocessor. Unfamiliarity with traditional hardware design methodologies such as VHDL and Verilog limits or prevents the use of an FPGA, often resulting in more expensive and power-hungry designs. A new group of emerging design tools called ESL (electronic system level) promises to address this methodology issue, allowing processor-based developers to accelerate their designs with programmable logic while maintaining a common design methodology for hardware and software. "Ion Trap Marks A Step Toward Practical Quantum Computing" http://www.elecdesign.com/Articles/Index.cfm?AD=1&ArticleID=13827 A quantum computer would be nothing less than a marvel. Unlike conventional two-state computers, it would encode information as quantum bits, or qubits. A qubit can be a 1 or a 0, simultaneously both 1 and 0, or some point in between. Quantum computing works on an atomic scale, exploiting the unusual behavior of the smallest particles of matter and light. A key stumbling block to building a functional machine is finding a way to build one using real-world fabrication processes. A research team at the National Institute of Standards and Technology (NIST) believes it can surmount this barrier with an easily manufacturable trap that harnesses electrically charged atoms-ions-for use as qubits. "Yale to Create Nanodevices for Drug Delivery" http://www.azonano.com/news.asp?newsID=3272 A team of Yale biomedical engineers and cell biologists received a $1-million award from the National Science Foundation to develop "smart nanoparticles" for the delivery of vaccines. "Professional Ethics on The ICCAD Agenda" http://www.eetimes.com/news/design/showArticle.jhtml?articleID=193501179 The Council on Electronic Design Automation (CEDA) is IEEE's focal point for multiple EDA disciplines. Its goal is to bring increased value to IEEE members by coordinating EDA activities, enabling new initiatives, fostering interdisciplinary research and recruiting young talent to EDA. CEDA will sponsor a discussion on professional ethics during the International Conference on Computer-Aided Design (ICCAD) Tuesday, November 7, from 1-1:45 p.m. in the Sierra/Cascade Ballroom at the Doubletree Hotel in San Jose, Calif. "Nanotechnology Size Scale - The Relative Size Of Nanotechnology Activities Compared To Atoms, Viruses, Bacteria And Human Hair" http://www.azonano.com/Details.asp?ArticleID=1780 One of the most difficult things to understand about nanotechnology is to get a solid grip of exactly how small nanoparticles are. This article seeks to better explain this by comparing nano sized objects with common things. "Transaction-Level Modeling is Critical for an Effective Functional Verification Methodology" http://www.chipdesignmag.com/print.php?articleId=655?issueId=0 Complexity drives greater degrees of abstraction, driving the shift in focus from the register transfer level to the transaction level. Consequently, the most successful advanced verification methodology will be one which is based upon transaction-level modeling (TLM). "PSoC Microcontroller and LVDT Measure Position" http://www.edn.com/contents/images/6382647.pdf Connecting an LVDT (linear-variable-differential transformer) to a microcontroller can prove challenging because an LVDT requires ac-input excitation and measurement of ac outputs to determine its movable core's position. "DSP Video Processing Via Open-Source APIs" http://www.embedded.com/shared/printableArticle.jhtml?articleID=193500221 Digital signal processors offer outstanding multimedia performance. Typically, they require just 40 percent to 50 percent as many cycles as a general-purpose processor (GPP) core to run a codec (encoders/decoders). They also offer far greater flexibility and reconfigurability than ASICs. Yet until now, programmers have had to learn proprietary languages to take advantage of the benefits of DSPs in digital video applications. "Embedded FPGA to Reach 65-nm in 2007" http://www.eetimes.com/showArticle.jhtml?articleID=193500527 A French company (M2000 SA) is claiming to be already delivering the densest embedded FPGA (eFPGA) at the 90-nanometer manufacturing node, and is in the process of preparing FPGA intellectual property targeting 65-nanometer designs. The first 65-nm tapeout is expected during the first half of 2007, the company said. Embedded FPGA block cover a large range of applications, from pin-swapping at one end of the spectrum to ASIC function prototyping at the other end, and including all possible forms of co-processing. With pin-swapping applications, reprogrammable macros are embedded into low-end ASICs using a few I/O pins. The reprogrammable logic area is small as it is only needed for pin multiplexing or for creating temporary test I/Os. However, for ASIC "platform silicon" large FPGA blocks are needed to sit next to standard processor and peripheral cores, and are used for application prototyping, to save simulation and first silicon costs. "Configurable Processors on the Rise" http://www.eetimes.com/showArticle.jhtml?articleID=193500460 Configurable processor cores are on a rapid growth curve and have "great opportunities" in many embedded applications, said analyst Jim Feldhan, keynote speaker at the ConfigCon Silicon Valley 2006 conference. Feldhan said that configurable cores should do well in applications such as wireless networks, multimedia, streaming video, image processing, HDTV, and old and new portables. He said that configurable cores provide product differentiation, address multiple standards, support multicore designs, and protect designers' IP. "Cadence Rivals Unimpressed with Power Standards Offer" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=193501406 Cadence Design Systems may be hoping to head off a power standards war by donating its Common Power Format (CPF) to the Silicon Integration Initiative (Si2) next year, but the offer still falls short of what is needed today, according to Cadence's primary competitors. "Design Analysis: The Importance of EDA Post Processing" http://dataweek.co.za/news.aspx?pklNewsId=22786&pklIssueId=596&pklCategoryID=38 EDA software tools include simulation, post processing, and physical design. With the exception of the physical design software, the post-processor is the tool designers use the most. The post-processing capability of an EDA software package is crucial for enabling designers to analyse their simulation results, make design decisions, and create documentation. This article covers the characteristics of a post-processor that are present in a world-class EDA software package, and includes many examples. "International Computing Prize Goes to Cell Biologist" http://www.earthtimes.org/articles/show/news_press_release,15044.shtml A computational cell biologist from the University of Cambridge has won one of the largest international prizes in science, the Royal Society andAcademie des Sciences Microsoft European Science award, it was announced today. Dr Dennis Bray has won the 250,000 euro award(1), funded by MicrosoftCorp, for his research using innovative computer simulations of biological systems. His work focuses on the molecular systems that enable bacteria todetect and respond to chemical changes in their surroundings - swimming, for example, towards food and away from poisons - a process known as chemotaxis. ============================================================================== What are Carbon Nanotubes? ------------------------------ Kaustav Banerjee University of California-Santa Barbara Carbon materials are found in a variety of forms (known as isomers) due to the various distinct types of valence bonds that a carbon atom can form. While the diamond and graphite forms and their applications have been widely known, carbon nanotubes (CNTs) came into the limelight only in 1991 when they were experimentally observed using transmission electron microscopy by Sumio Iijima at NEC in Japan [1]. Since then, a flurry of research activities ranging from basic science to highly applied concepts related to CNTs have been reported in the literature. From a purely physics perspective, the one-dimensional nature of carbon nanotubes allows a whole new range of theoretical and experimental analysis that is not feasible with two- and three-dimensional materials. On the other hand, the outstanding properties of CNTs have made them prime candidates for future nanoelectronic devices and interconnects. CNTs exhibit extraordinary strength and unique electrical properties, and are efficient conductors of heat. In this article, I will focus on the prospects of carbon nanotubes in VLSI. As we know, VLSI is essentially CMOS (silicon) based and face several fundamental challenges-both in terms of device and interconnect (copper) scaling [2]. Metallic and Semiconducting Nanotubes A carbon nanotube is a one-atom thick sheet of graphite (called graphene) rolled up into a seamless cylinder with diameter of the order of a nanometer [3]. This results in an essentially one-dimensional nanostructure (i.e., length to diameter ratio exceeds 10,000). There are two main types of carbon nanotubes: single-walled nanotubes (SWCNTs) and multi-walled nanotubes (MWCNTs). In SWCNTs the cylindrical structure consists of a single layer of graphene with typically observed diameters < 2 nm. MWCNTs consist of multiple concentric cylinders or the graphene sheet is simply rolled in around itself resembling a scroll of parchment. Most experimentally observed CNTs are multi-walled structures with outer most shell diameters exceeding 10 nm. Since current conduction in a MWCNT is known to be mostly confined to the outermost single-walled nanotube and since band gap of a SWCNT varies inversely with its diameter, MWCNTs are metallic in nature. SWCNTs can be either metallic or semiconducting depending on the way the roll-up of the graphene sheet occurs---an aspect termed as Chirality, and if all the roll-up types are realized with equal probability, 1/3 of the SWCNTs end up being metallic and 2/3 semiconducting. Thus, when CNTs are fabricated either by arc growth, laser ablation or chemical vapor deposition (CVD), a mixture of metallic and semi-conducting nanotubes is formed. Carbon Nanotube Interconnects Metallic CNTs have aroused a lot of research interest in their applicability as VLSI interconnects of the future because of their extremely desirable properties of high mechanical and thermal stability, high thermal conductivity and large current carrying capacity [4, 5]. An isolated CNT can carry current densities in excess of 1000 MA/sq-cm without any signs of damage even at an elevated temperature of 250 degree C, thereby eliminating electromigration reliability concerns that plague Cu interconnects. Recent modeling work comparing the performance, power dissipation and thermal/reliability aspects of CNT interconnect to scaled copper interconnects have shown that CNT bundle interconnects can potentially offer significant advantages over copper [6, 7]. Additionally, the concept of hybrid CNT/Cu interconnects-employing CNT vias in tandem with copper interconnects has been shown to offer remarkable advantages from a reliability/thermal-management perspective [7]. More information on state-of-the-art of CNT interconnects (including their fabrication) can be found in [8, 9]. Carbon Nanotube Transistors Semiconducting CNTs have been used to fabricate field effect transistors (CNTFETs), which show tremendous promise due to their superior electrical characteristics over silicon based MOSFETs [10, 11]. Since electron mean free path in SWCNTs can exceed 1 micrometer, CNTFETs exhibit near-ballistic transport characteristics resulting in very high speed devices. In fact, CNT devices are projected to be operational in the frequency range of hundreds of GHz [12]. Recent work detailing the advantages and disadvantages of various forms of CNTFETs have also shown that the tunneling based CNTFET offers significantly better characteristics compared to other CNTFET structures [13]. This device has been found to be superior in terms of subthreshold slope--a very important property for low power applications. Design and Design Automation Challenges Although CNT devices and interconnects have been separately shown to be promising in their own respects, there have been few efforts to successfully combine them in a realistic circuit. Most CNTFET structures employ the silicon substrate as a back gate. Applying different back gate voltages might become a concern when designing large circuits out of these devices. Several top-gated structures have also been demonstrated, which can alleviate this concern [14, 15]. Recently, a fully integrated logic circuit built on a single nanotube has been reported [16]. However, this circuit also employs a back-gate. Additionally, there are still several process related challenges that need to be addressed before CNT-based devices and interconnects can enter mainstream VLSI process. This makes it an exciting and open field for research. Problems like purification, separation of carbon nanotubes, control over nanotube length, chirality and desired alignment, low thermal budget as well as high contact resistance are yet to be fully resolved. Although these are serious technological challenges, innovative ideas have been proposed to build practical transistors out of nano-networks [17]. Since lack of control on chirality produces a mix of metallic as well as semiconducting CNTs from any fabrication process and it is difficult to control the growth direction of the CNTs, random arrays of SWCNTs (that are easily produced) have been proposed to build thin film transistors [17]. This idea can be further exploited to build practical CNT based transistors and circuits without the need for precise growth and assembly. Finally, while it is important to have physical implementations of large CNT circuits, it is also imperative to develop the ability to perform detailed modeling, analysis and simulation of such circuits. Not only will this require a correct understanding of the physics of these individual devices and interconnects, but will also present significant challenges in terms of novel design automation techniques that can comprehend effects such as uncertainties and variations in design parameters (due to lack of control) as well as probabilistic designs (such as in nano-networks). Moreover, the outstanding thermal conductivity of CNTs and their mesoscopic properties can be exploited to address a variety of key technological issues including chip-level thermal management as well as design of ultra high-density passive circuit elements (such as capacitors and inductors) that are widely employed in high-frequency mixed-signal and radio-frequency ICs. The CNT interconnect structures also offer exciting prospects for system level architectural innovations including design of ultra high-bandwidth networks-on-chip, very low-latency memory addressing, and robust power distribution networks. References: [1] S. Iijima, "Helical Microtubules of Graphitic Carbon," Nature, Vol. 354, pp. 56-58, 1991. [2] ITRS, "International Technology Roadmap for Semiconductors-2005 edition," SIA, Available online: http://www.itrs.net 2005. [3] M.S. Dresselhaus, G. Dresselhaus and Ph. Avouris, Editors, Carbon Nanotubes: Synthesis, Structure, Properties and Applications, Springer-Verlag, 2000. [4] F. Kreupl, et al., "Carbon Nanotubes in Interconnect Applications," Microelectronic Engineering, 64, pp. 399-408, 2002. [5] J. Li, et al., "Bottom-up Approach for Carbon Nanotube Interconnects," Applied Physics Letters, Vol. 82, No. 15, pp. 2491-2493, April 2003. [6] N. Srivastava and K. Banerjee, "Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications," ICCAD, 2005, pp. 383-390. [7] N. Srivastava, R.V. Joshi and K. Banerjee, "Carbon Nanotube Interconnects: Implications for Performance, Power Dissipation and Thermal Management," IEDM, 2005, pp. 257-260. [8] K. Banerjee and N. Srivastava, "Are Carbon Nanotubes the future of VLSI Interconnections?", ACM Design Automation Conference, 2006, pp. 809-814. [9] K. Banerjee, S. Im and N. Srivastava, "Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?" IEEE Nano Networks Conference, 2006. [10] P. Avouris, et al., "Carbon Nanotube Electronics," Proc. IEEE, Vol. 91, pp. 1772-1784, 2003. [11] S. Wind, J. Appenzeller, and P. Avouris, "Lateral scaling in CN fieldeffect transistors," Phys. Rev. Lett., Vol. 91, pp. 058 301-1-058 301-4, 2003. [12] S. Hasan, S. Salahuddin, M. Vaidyanathan and M. A. Alam, "High-Frequency Performance Projections for Ballistic Carbon-Nanotube Transistors," IEEE Transactions on Nanotechnology, Vol. 5, No. 1, pp. 14-22, 2006. [13] J. Appenzeller, et al., "Comparing Carbon Nanotube Transistors - The Ideal Choice: A Novel Tunneling Device Design," IEEE TED, Vol. 52, No. 12, pp. 2568-2576, 2005. [14] S. J. Wind, J. Appenzeller, R. Martel, V. Derycke and Ph. Avouris, "Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes," Applied Physics Letters, Vol. 80, No. 20, 3817 - 3819, 2002. [15] D. V. Singh, K. A. Jenkins, J. Appenzeller, D. Neumayer, A. Grill and H.-S. P. Wong, "Frequency Response of Top-Gated Carbon Nanotube Field-Effect Transistors," IEEE Transactions on Nanotechnology, Vol. 3, No. 3, pp. 383-387, 2004. [16] Z. Chen, J. Appenzeller, Y.-M. Lin, J. Sippel-Oakley, A. G. Rinzler, J. Tang, S. J. Wind, P. M. Solomon and Ph. Avouris, "An Integrated Logic Circuit Assembled on a Single Carbon Nanotube," Science, Vol. 311, p. 1735, 2006. [17] E. S. Snow, J. P. Novak, P. M. Campbell, and D. Park "Random networks of carbon nanotubes as an electronic material," Applied Physics Letters, Vol. 82, No. 13, pp. 2145 - 2147, 2003. ============================================================================== Submission deadlines: --------------------- GLSVLSI'07 - Great Lakes Symposium on VLSI Stresa-Largo Maggiore, Italy Mar 11-13, 2007 Deadline: Nov 10, 2006 http://www.glsvlsi.org/ LATW'07 - Latin-American Test Workshop Peru Mar 11-14, 2007 Deadline: Nov 12, 2006 http://www.latw.net/ DAC'07 - Design Automation Conference San Diego, CA Jun 4-8, 2007 Deadline: Nov. 20, 2006 http://www.dac.com/ SLIP'07 - System Level Interconnect Prediction Workshop Austin, TX Mar 17-18, 2007 Deadline: Nov 24, 2006 http://www.sliponline.org/ TAU'07 - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Austin, TX Feb 26-27, 2007 Deadline: Nov 27, 2006 http://www.tauworkshop.com/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 Deadline: Dec 1, 2006 http://www.nocsymposium.org/ ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 Deadline: Dec 15, 2006 http://www.inf.ufrgs.br/isvlsi2007/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 Deadline: Dec 20, 2006 http://www.iess.org/ MSE'07 - Int'l Conference on Microelectronic Systems Education San Diego, CA Jun 3-4, 2007 Deadline: Jan 15, 2007 http://www.mseconference.org/ ============================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- ICCAD'06 - Int'l Conference on Computer-Aided Design San Jose, CA Nov 5-9, 2006 http://www.iccad.com/ PDCS'06 - Int'l Conference on Parallel and Distributed Computing and Systems Dallas, TX Nov 13-15, 2006 http://www.iasted.org/conferences/2006/Dallas/pdcs.htm CSS'06 - Conference on Circuits, Signals and Systems San Francisco, CA Nov 20-22, 2006 http://www.iasted.org/newsletter/2006/css2.htm IP-SOC'06 - IP Based SoC Design Grenoble, France Dec 6-7, 2006 http://www.us.design-reuse.com/ipsoc2006/ ThETA'07 - Int'l Conference on Thermal Issues in Emerging Technologies: Theory and Applications Cairo, Egypt Jan 3-6, 2007 http://www.thetaconf.org VLSI'07 - Int'l Conference on VLSI Design Bangalore, India Jan 6-10, 2007 http://www.vlsiconference.com/2007/ ASPDAC'07 - Asia and South Pacific Design Automation Conference Yokohama, Japan Jan 23-26, 2007 http://www.aspdac.com/aspdac2007/ FPGA'07 -Int'l Symposium on Field-Programmable Gate Arrays Monterey, CA Feb 18-20, 2007 http://conferences.ece.ubc.ca/isfpga2007/ TAU'07 - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Austin, TX Feb 26-27, 2007 http://www.tauworkshop.com/ SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 http://www.splconf.org/ GLSVLSI'07 - Great Lakes Symposium on VLSI Stresa-Largo Maggiore, Italy Mar 11-13, 2007 http://www.glsvlsi.org/ LATW'07 - Latin-American Test Workshop Peru Mar 11-14, 2007 http://www.latw.net/ ASYNC'07: Int'l Symposium on Asynchronous Circuits and Systems Berkeley, CA Mar 12-14, 2007 http://conferences.computer.org/async2007/ SLIP'07 - System Level Interconnect Prediction Workshop Austin, TX Mar 17-18, 2007 http://www.sliponline.org/ ISPD'07 - Int'l Symposium on Physical Design Austin, TX Mar 18-21, 2007 http://www.ispd.cc/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 http://www.nocsymposium.org/ ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 http://www.inf.ufrgs.br/isvlsi2007/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 http://www.iess.org/ MSE'07 - Int'l Conference on Microelectronic Systems Education San Diego, CA Jun 3-4, 2007 http://www.mseconference.org/ DAC'07 - Design Automation Conference San Diego, CA Jun 4-8, 2007 http://www.dac.com/ ============================================================================== GLSVLSI 2007 (Great Lakes Symposium on VLSI) Final Call For Papers ------------------------------------------------------------------- Stresa-Lago Maggiore, Italy March 11-13, 2007 http://www.glsvlsi.org/ Sponsored by ACM SIGDA, with the Technical Support of IEEE CASS The 17th edition of Great Lakes Symposium on VLSI (GLSVLSI) will be held in Stresa-Lago Maggiore, Italy, the first time in Europe. Original, unpublished papers, describing research in the general area of VLSI are solicited. Both theoretical and experimental research results are welcome. Proceedings will be published by the ACM and will be included inthe SIGDA compendium CD-ROM. Important deadlines: Paper submission: November 10, 2006 Acceptance notification: December 22, 2006 Camera-ready paper due:January 8, 2007 Program Tracks: * VLSI Design: design of ASICs, microprocessors and micro-architectures, embedded processors, analog/digital/mixed-signal systems, multi-chip modules, FPGAs. * VLSI Circuits: analog/digital/mixed-signal circuits, RF and communication circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits. * Computer-Aided Design (CAD): hardware/software co-design, logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction), algorithms and complexity analysis. * Low Power and Power Aware Design: circuits, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools. * Testing, Reliability, Fault-Tolerance: digital/analog/mixed-signal testing, design for testability and reliability, online testing techniques, static and dynamic defect-and fault-recoverability, and variation-aware design. * Emerging Technologies: nanotechnology, molecular electronics, quantum devices, biologically-inspired computing, single electron transistors, resonant tunneling devices, VLSI aspects of sensor and sensor network, and CAD tools for emerging technology devices and circuits. General Chairs Hai Zhou, Northwestern University Enrico Macii, Politecnico di Torino Program Chairs Zhiyuan Yan, Lehigh University Yehia Massoud, Rice University Publicity Chairs Vassilis Paliouras , University of Patras Lin Yuan , Synopsys Inc. Program Track Chairs VLSI Design: Massoud Pedram, University of Southern California VLSI Circuits: Jamil Kawa, Synopsys Computer-Aided Design (CAD): Martin Wong, University of Illinois at Urbana-Champaign Low Power and Power-Aware Design: Gang Qu, University of Maryland Testing, Reliability, Fault-Tolerance: Jacob Abraham, University of Texas, Austin Emerging Technologies: Mircea Stan, University of Virginia Paper Submission: Authors are invited to submit full-length (6 pages maximum), original, unpublished papers along with an abstract of at most 200 words. To enable blind review, the author list should be omitted from the main document. Previously published papers or papers currently under review for other conferences/journals should not be submitted and will not be considered. Electronic submission in PDF format to the http://www.glsvlsi.org website is required. Author and contact information must be entered during the submission process. Paper Format: To allow reduced turn-around time for accepted papers, GLSVLSI 2007 submissions should be in camera-ready two-column format, following the ACM proceedings specifications located at: http://www.acm.org/sigs/pubs/proceed/template.html and the classification system detailed at: http://www.acm.org/class/1998/ Paper Publication and Presenter Registration: Papers will be accepted for regular or poster presentation at the symposium. Every accepted paper MUST have at least one author registered to the symposium by the time the camera-ready paper is submitted; the author is also expected to attend the symposium and present the paper. Journal Special Issue: Authors of the best papers published at the symposium will be invited to submit extended versions of their manuscripts for possible publication in a special issue of some international journal. Best Student Paper Award: A Best Student Paper Award, sponsored by Intel Corp., will be assigned by the technical program committee. Only papers with a student as first author will be eligible for receiving the award. ============================================================================== CALL FOR WORKSHOP PROPOSALS ------------------------------- COMPSAC is a major international forum for researchers, practitioners, managers, and policy makers interested in computer software and applications. Starting with 2006, COMPSAC is designated as the IEEE Computer Society Signature Conference on Software Technology and Applications. Based on this designation COMPSAC organizers are able to work with other key functions of the Computer Society to create more values for the conference volunteers and participants. Proposals for workshops are solicited for consideration of affiliation with COMPSAC 2007. Affiliated workshops will be held in conjunction and co-located with the conference and other affiliated workshops. The purpose of these workshops is to provide a platform for presenting novel ideas in a less formal and possibly more focused way than the conference itself. As such, they also offer a good opportunity for young researchers to present their work and to obtain feedback from an interested community. Workshop organizers are responsible for establishing a program committee, collecting and evaluating submissions, notifying authors of acceptance or rejection in due time, and ensuring a transparent and fair selection process, organizing selected papers into sessions, and assigning session chairs. Researchers and practitioners are invited to submit a one-page concept paper proposing a workshop to the 31st COMPSAC Workshop Chair, Atilla Elci (atilla.elci@emu.edu.tr), by Dec. 8, 2006. Submission may be made by e-mail with "COMPSAC Preliminary Workshop Proposal" in the subject header and supplying data on the Preliminary Workshop Proposal Format. Feedback will be provided to the workshop proposers by Dec. 15, 2006. An accepted proposal will then be detailed using the Final Workshop Proposal Format by its organizers. Other important due dates are mentioned below. The selection of the workshops to be included in the final COMPSAC program will be based upon several factors, including the scientific / technical interest of the topics, the quality of the proposal, balance and distinctness of workshop topics, and the capacity of the conference workshop program. Workshops use the same paper submission system with COMPSAC 2007. Proceedings of the COMPSAC Workshops will be printed as a separate volume by IEEE Computer Society Press to be made available to all conference registrants on site. All workshop papers will as well be electronically available through IEEE Xplore Digital Database. Any further information needed for preparing a workshop proposal can be obtained by contacting the COMPSAC Workshop Chair. 31st COMPSAC web site, too, (http://www.compsac.org/) is a source of first hand information. 31st COMPSAC Preliminary Workshop Proposal Format (Limited to 1-page, typed double space in 11 pt Times New Roman) Workshop title: ... Primary organizers, their affiliation, and contact details: ... Proposed duration (select one: 1 / 2 / 3 / 4 sessions; 1 session=90 minutes): ... A statement of goals for the workshop: ... Workshop theme: ... Likely participants: ... 31st COMPSAC Final Workshop Proposal Format (Limited to 3-pages, typed double space in 11 pt Times New Roman) Workshop title: ... Primary organizers, their affiliation, and contact details: ... Proposed duration (select one: 1 / 2 / 3 / 4 sessions; 1 session=90 minutes): ... A statement of goals for the workshop: ... Workshop theme: ... Likely participants: ... Description of the workshop: suggested items are as follows: expected achievements, importance, program committee, format (paper presentations, discussion sessions, etc.), plans for call for papers / participation, plans for publicity,... 31st COMPSAC important dates for workshops Dec. 08, 2006: Preliminary Workshop Proposal submission Dec. 15, 2006: Feedback provided to the workshop proposers Dec. 31, 2006: Final workshop proposal submission Feb. 23, 2007: Full paper and short paper due Mar. 15, 2007: Decision notification (electronic) Apr. 15, 2007: Camera-ready copy and author registration due Note: The 31st COMPSAC Steering Committee will allocate sessions to each workshop within the constraints of space availability and the likely interest of the attendees in the workshop. Please be advised to organize your workshop early and request for adequate space as soon as your effort turns out to be fruitful. The COMPSAC Workshop Chair will work closely with the primary organizers to ensure a successful workshop. Issue Date: Oct. 16, 2006. ============================================================================== Upcoming funding opportunities ------------------------------- ASEE Office of Naval Research (ONR) Summer Faculty Research Program Deadline: December 1, 2006 http://www.asee.org/fellowships/summer/index.cfm DOD High Density Optical Memory Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Quantum Electronic Solids Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Distributed Intelligence Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Young Faculty Award Deadline: December 5, 2006 http://www.grants.gov/search/search.do?oppId=10908&mode=VIEW Experimental and Theoretical Development of Quantum Information Science Deadline: December 11, 2006 http://www.arl.army.mil/main/Main/DownloadedInternetPages/CurrentPages/DoingBusinesswithARL/research/QC06Final6Jul06.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF Computer Systems Research (CSR) (NSF 07-504) Deadline: January 17, 2007 http://www.nsf.gov/pubs/2007/nsf07504/nsf07504.htm Strategic Technologies for Cyberinfrastructure (STCI) Deadline: February 8, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=500066&org=NSF&sel_org=NSF&from=fund Software Development for Cyberinfrastructure (SDCI) (NSF 07-503) Deadline: January 22, 2007 http://www.nsf.gov/pubs/2007/nsf07503/nsf07503.htm Cyber Trust (CT) (NSF 07-500) Deadline: January 8, 2007 http://www.nsf.gov/pubs/2007/nsf07500/nsf07500.htm NSF-SIA/NRI Graduate Student and Postdoctoral Fellow Supplements to NSF Centers in Nanoelectronics (NSF 06-051) Deadline: November 17, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=501009&org=CISE&from=home Information and Intelligent Systems: Advancing Human-Centered Computing, Information Integration and Informatics, and Robust Intelligence (NSF 06-572) Deadline: October 19, 2006 for Large Projects November 02, 2006 for Medium Projects December 06, 2006 for Small Projects http://www.nsf.gov/pubs/2006/nsf06572/nsf06572.htm Active Nanostructures and Nanosystems (ANN) (NSF 06-595) Deadline: November 15, 2006 http://www.nsf.gov/pubs/2006/nsf06595/nsf06595.htm Advanced Learning Technologies (ALT) (NSF 06-535) Deadline: April 25, 2007 http://www.nsf.gov/pubs/2006/nsf06535/nsf06535.htm DARPA Cognitive Information Processing Technology (BAA02-21) Deadline: June 5, 2007 http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm NASA Applied Information Systems Research Deadline: January 30, 2007 http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId={0B64DB41-8F7D-C949-44CD-9D04A484B653}&path=open ============================================================================== Conference Proceedings Added to the ACM Digital Library --------------------------------------------------------- Proceedings of the following conferences are now available in the ACM Digital Library. http://portal.acm.org/dl.cfm GECCO 2006 ICCAD 2005 FPGA 2005 DATE 2005 DAC 2005 GLSVLSI 2005 ISLPED 2005 ============================================================================== Table of Contents - the Lastest Issue of ACM Trans. on Design Automation ------------------------------------------------------------------------ Introduction to special issue: Novel paradigms in system-level design Massoud Pedram Pages: 535 - 536 http://delivery.acm.org/10.1145/1150000/1142981/p535-introduction.pdf?key1=1142981&key2=0056121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 System level design paradigms: Platform-based design and communication synthesis Alessandro Pinto, Alvise Bonivento, Allberto L. Sangiovanni-Vincentelli, Roberto Passerone, Marco Sgroi Pages: 537 - 563 http://delivery.acm.org/10.1145/1150000/1142982/p537-pinto.pdf?key1=1142982&key2=6256121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Computation and communication refinement for multiprocessor SoC design: A system-level perspective Radu Marculescu, Umit Y. Ogras, Nicholas H. Zamora Pages: 564 - 592 http://delivery.acm.org/10.1145/1150000/1142983/p564-marculescu.pdf?key1=1142983&key2=9356121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Analysis and optimization of distributed real-time embedded systems Paul Pop, Petru Eles, Zebo Peng, Traian Pop Pages: 593 - 625 http://delivery.acm.org/10.1145/1150000/1142984/p593-pop.pdf?key1=1142984&key2=1656121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs Prabhat Mishra, Aviral Shrivastava, Nikil Dutt Pages: 626 - 658 http://delivery.acm.org/10.1145/1150000/1142985/p626-mishra.pdf?key1=1142985&key2=0856121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Warp Processors Roman Lysecky, Greg Stitt, Frank Vahid Pages: 659 - 681 http://delivery.acm.org/10.1145/1150000/1142986/p659-lysecky.pdf?key1=1142986&key2=6956121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Module placement for fault-tolerant microfluidics-based biochips Fei Su, Krishnendu Chakrabarty Pages: 682 - 710 http://delivery.acm.org/10.1145/1150000/1142987/p682-su.pdf?key1=1142987&key2=2166121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing Narender Hanchate, Nagarajan Ranganathan Pages: 711 - 739 http://delivery.acm.org/10.1145/1150000/1142988/p711-hanchate.pdf?key1=1142988&key2=1366121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Simultaneous placement with clustering and duplication Gang Chen, Jason Cong Pages: 740 - 772 http://delivery.acm.org/10.1145/1150000/1142989/p740-chen.pdf?key1=1142989&key2=0566121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan Pages: 773 - 796 http://delivery.acm.org/10.1145/1150000/1142990/p773-bhanja.pdf?key1=1142990&key2=4666121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. 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