=============================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org =============================================================================== 15 October 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 20 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What Is OpenAccess Gear? (Reprinted from October 1 issue) Contributing author: Philip Chong, Cadence Berkeley Laboratories Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Call For Papers - GLSVLSI 2007 Hai Zhou (6) Conference Proceedings Added to the ACM Digital Library (7) Table of Contents - the Lastest Issue of ACM Trans. on Design Automation (8) Upcoming Funding Opportunities Qinru Qiu (9) Call For Papers - ARC 2007 2007 International Workshop on Applied Reconfigurable Computing Fernanda G. L. Kastensmid =============================================================================== Dear ACM/SIGDA members, This issue includes the announcement on the conference proceedings added to the ACM Digital Library and the table of contents for the lastest issue of TODAES. It also has the 2nd call for papers for GLSVLSI'07. In addition to a fresh batch of SIGDA news, we updated the lists of upcoming deadlines and events, as well as the funding opportunities. We reprint the "What is" column from the last issue. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "EU Set to Decide on European Institute of Technology" http://www.eetimes.com/showArticle.jhtml?articleID=193300050 The European Commission has had to scale down plans for a flagship project that was proposed as a way to compete with the U.S. in leading research projects and as a centre of excellence in innovation and education because of lack of interest from industry. The European Institute of Technology (EIT), which proponents see as a European rival to the Massachusetts Institute of Technology, has been strongly backed by European Commission president, José Manuel Barroso, but industry across the member states has been lukewarm about the project, as have academics and several national governments. Discussions within the EU executive have also seen divisions emerge between key commissioners over the EIT's institutional form and role. "ARM's Fault-Tolerant Chip to Cut Cost of Car Development" http://www.arm.com/iqonline/news/ARMnews/14948.html ARM has rolled out the Cortex-R4F processor, which it said will accelerate next-generation automotive design with floating-point support for faster processing. The Cortex-R4F processor will enable ARM Partners to meet the stringent error-free safety standards and high performance requirements of automotive applications including next-generation Anti-lock Braking (ABS) and vehicle stability systems, the company said. "'DNA computer' is Unbeatable at Tic-tac-toe" http://www.newscientisttech.com/article/dn10310-dna-computer-is-unbeatable-at-tictactoe.html A computer that uses strands of DNA to perform calculations has mastered the game tic-tac-toe. MAYA-II, developed by researchers at Columbia University and the University of New Mexico in the US, uses a system of DNA logic gates to calculate its moves. A DNA logic gate consists of a strand of DNA that binds to another specific input sequence. This binding causes a region of the strand to work as an enzyme, modifying yet another short DNA sequence into an output string. "Quantum Computing Gets Boost From 'Entanglement' Of Atom Pairs" Technical paper published in the Nature journal http://www.sciencedaily.com/releases/2006/10/061018150842.htm Physicists at the Commerce Department's National Institute of Standards and Technology (NIST) have taken a significant step toward transforming entanglement--an atomic-scale phenomenon described by Albert Einstein as "spooky action at a distance"--into a practical tool. They demonstrated a method for refining entangled atom pairs (a process called purification) so they can be more useful in quantum computers and communications systems, emerging technologies that exploit the unusual rules of quantum physics for pioneering applications such as "unbreakable" data encryption. This process has only been demonstrated with photons before, and with much lower levels of purification. The same NIST group previously has demonstrated at a rudimentary level all the basic building blocks for a quantum computer, including key processes such as error correction and, most recently, a mass-producible ion trap. Ions are among the most promising of a dozen or so candidates for quantum bits (qubits) to store, manipulate, and transport quantum information. "IBM Announces Dual-core Power6 Running at 4-5GHz" http://www.eetimes.com/showArticle.jhtml?articleID=193105767 IBM's next-generation dual-core Power6 processors will ship in mid-2007. They will run at 4-5GHz with a total of 8Mbytes L2 cache and a 75Gbyte/second link to external memory. The big news for IBM is how it can double frequency while holding the line on power consumption and pipeline depth. New circuit designs and process technology improvements plow the way for the advances. The processor is built in a 65-nm process using IBM's silicon-on-insulator (SOI) and strained silicon technolog. IBM applied new techniques in variable gate lengths and variable threshold voltages to squeeze maximum performance per Watt at the transistor level, as well as new latch circuits and improved static gates. The chip can be fully operated at as little as 0.8V. "AMD Unveils Details of the Barcelona Quad-Core Opteron Processor" http://www.extremetech.com/article2/0,1697,2027650,00.asp It's probably fair to suggest that Barcelona is to the current Opterons as Intel's Core 2 is to the Pentium M-designed from the ground up, on a base of the old with a lot of new stuff rolled in. In addition to several improvements in floating-point performance, Barcelona will include advanced branch prediction, 32-byte instruction fetch, sideband stack optimizer, out-of-order load execution. On-die independent memory controllers feature greater bandwidth, support for 1GB memory pages in addition to smaller sizes, and 48-bit hardware addressing. On-chip cache architecture includes per-core L1 and L2 cashes, as well as L3 cache. Advanced power-reduction features will allow Barcelona to run in the 95W envelope. Desktop variants aren't scheduled to ship until the second half of 2007 "EDA Software Aids in the Development of SoCs" http://news.thomasnet.com/fullstory/493994/2585 Synopsys, Inc. (NASDAQ:SNPS), a world leader in semiconductor design software, today announced that it has expanded its portfolio of DesignWare(R) Library intellectual property (IP) with the release of verification IP for the Open Core Protocol (OCP) interface. OCP is a common standard IP core interface, or socket, that facilitates "plug and play" system-on-chip (SoC) design. Synopsys has developed verification IP for the OCP interface in response to customer demand for using the DesignWare Library and VCS(R) Verification Library to verify systems and cores that utilize OCP. "Magma Gets High Marks in EDA Market Study" http://www.eetimes.com/news/design/showArticle.jhtml?articleID=193105402 EDA users give high marks to Magma Design Automation Inc. and remain undeterred by company's high-profile patent infringement disputes with heavyweight Synopsys, according to the results of an unscientific EDA design implementation market study conducted by a prominent EDA analyst. "Accellera Issues Revised VHDL Standard" http://www.reed-electronics.com/tmworld/article/CA6380373.html A new revision to Accellera's VHDL standard integrates the Property Specification Language (PSL), adds intellectual property (IP) protection methods, and offers improvements that increase designer productivity, including the implementation of a hierarchical signal reference to allow test benches to drive and read signals deep in a design. "Introducing The New InsideChips.com - The Premier Internet Channel For Semiconductor Executives, Entrepreneurs, and Investors" http://home.businesswire.com/portal/site/google/index.jsp?ndmViewId=news_view&newsId=20061011005358&newsLang=en A richly enhanced version of the semiconductor industry's premier web site, InsideChips, has launched at http://www.insidechips.com. The web site serves the business information and resource needs of entrepreneurs, executives, investors, and others in the global semiconductor industry. InsideChips.com supports and promotes entrepreneurship and new ventures in the semiconductor industry, and provides timely coverage of new and established and new companies plus industry trends and events, financial data, new products, and more. Site members and visitors hail from industry organizations worldwide including semiconductor manufacturers, fabless semiconductor companies, integrated device manufacturers, IP providers, design houses, and electronic design automation (EDA) companies. It is a major news and information source for angel investment groups, venture capitalists, and investment banking firms. InsideChips is a service of HTE Research, Inc. and features both monthly and annual subscriptions that provide access to the entire site's content, services, and tools. "Synopsys Unveils New MinChip Technology" http://www.antara.co.id/en/seenws/?id=21397 Synopsys JupiterXT and IC Compiler Tools Enable Die Size Optimization Synopsys, Inc., a world leader in semiconductor design software, today introduced newMinChip technology that analyzes physical design complexity and identifies the smallest routable size for semiconductor designs. "Linux Copyright Wars: IBM Catalogs SCO's Failures" http://www.ip-wars.net/story/2006/10/14/233634/06 The discovery phase of SCO v. IBM is now complete, and as per the court's schedule the time to raise Summary Judgment issues is now. And IBM has indeed raised them making it likely that all of SCO's claims against IBM could wind up dismissed piecemeal in those motions. IBM's redacted memo in support of CC10 includes 102 pages detailing five independent but overlapping, direct and powerfully detailed reasons why SCO's claims of Linux infringement against its code should be dismissed. "Korean-U.S. Partners Develop Deep UV LEDs" http://www.eetimes.com/showArticle.jhtml?articleID=193300181 Seoul Optodevice Co and U.S. partner Sensor Electronic Technology Inc. said they have completed joint development of a new line of deep ultraviolet LEDs that double output power and lifetime than existing devices. Maximum output power of the 280-nm LED reached 1.5 mW at 20 mA. The new LEDs could represent a non-toxic, solid-state replacement for mercury lamps. The new LEDs could be used in home appliances, sterilization of hygienic products, biomedical analysis, bioagent detection and detecting counterfeit currency, SOC added. ============================================================================== What Is OpenAccess Gear? ------------------------- Philip Chong, Cadence Berkeley Laboratories The complex design flows prevalent in the EDA industry today present a challenge for academic researchers. Many experiments of potential interest revolve around the interaction between a variety of EDA components. For example, a researcher interested in developing and studying a physically-aware synthesis flow must be able to combine physical and logical information in a design database, and co-ordinate placement, synthesis, and timing analysis tools. This can be a daunting task in an academic setting, where developing these components from scratch can be prohibitively time-consuming, and purchasing these components can be too costly. The OpenAccess Gear (OA Gear) project was originally started by Cadence Berkeley Labs to facilitate academic research and development of complex EDA flows and tools. OA Gear is a toolkit of utilities written in C++ [1] and built on the industry-standard OpenAccess EDA database [2]. Among the OA Gear packages are a static timing analysis tool, an interface to the Capo placement tool developed at UCLA and University of Michigan, and an extension to OpenAccess for logical/functional representation. Such components can be combined to form the foundation of the aforementioned physically-aware synthesis flow, or other interesting research tools can be written to take advantage of these packages. OA Gear is freely available in source code form, making it easy to integrate into research projects. As a concrete example of how OA Gear can facilitate academic research, the work presented by Zhong Xiu and Rob Rutenbar at the 2005 Design Automation Conference ("Timing-Driven Placement by Grid-Warping") used the OA Gear timing analysis tool to provide timing-driven capabilities for their novel placement technique [3]. In a related paper published at the 2005 International Symposium on Physical Design, the authors indicate that OA Gear saved them several months of implementation and coding effort [4] Another recent example of the use of OA Gear in academic research was the programming challenge held in conjunction with the 2006 International Workshop on Logic And Synthesis [5]. For the challenge, students were tasked to develop a synthesis tool of their choice using the OA Gear logical/functional representation layer; winners were determined by a panel of judges, who also dispensed small cash prizes and stipends for travel to the workshop. There were two winning entries chosen, one a fast simulation and equivalence checking tool written by Kai-hui Chang and David Papa from University of Michigan [6], the other a tool using a novel SAT sweeping algorithm written by Nathan Kitchen and Qi Zhu from UC Berkeley [7]. (The latter work also won a best paper award at the 2006 Design Automation Conference.) Both winning entries have been contributed by their authors to OA Gear and are now part of the toolkit. For more information about OA Gear and to download the toolkit, see the OA Gear web site at http://openedatools.si2.org/oagear/ . Links to obtain information about OpenAccess itself can be found on the OA Gear web site as well. References [1] Open Access http://www.si2.org/?page=69 [2] OA Gear http://openedatools.si2.org/oagear/ [3] Z. Xiu, R. A. Rutenbar, "Timing-driven placement by grid-warping," DAC 2005, pp. 585-591. [4] Z. Xiu et al, "Early research experience with OpenAccess gear: an open source development environment for physical design," ISPD 2005, pp. 94 - 100. [5] R. Goering, "Synthesis contest winners offer new algorithms", http://www.eetimes.com/showArticle.jhtml?articleID=188702906 EE Times, June 2006. [6] K.-H. Chang, D. A. Papa, I. L. Markov and V. Bertacco, "Fast Simulation and Equivalence Checking Using OAGear," IWLS 2006, pp. 270-271. [7] Q. Zhu, N. Kitchen, A. Kuehlmann, A. Sangiovanni-Vincentelli, "SAT sweeping with local observability don't-cares," DAC 2006, pp. 229-234. ============================================================================== Submission deadlines: --------------------- SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 Deadline: Oct 23, 2006 http://www.splconf.org/ GLSVLSI'07 - Great Lakes Symposium on VLSI Stresa-Largo Maggiore, Italy Mar 11-13, 2007 Deadline: Nov 10, 2006 http://www.glsvlsi.org/ LATW'07 - Latin-American Test Workshop Peru Mar 11-14, 2007 Deadline: Nov 12, 2006 http://www.latw.net/ DAC'07 - Design Automation Conference San Diego, CA Jun 4-8, 2007 Deadline: Nov. 20, 2006 http://www.dac.com/ SLIP'07 - System Level Interconnect Prediction Workshop Austin, TX Mar 17-18, 2007 Deadline: Nov 24, 2006 http://www.sliponline.org/ TAU'07 - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Austin, TX Feb 26-27, 2007 Deadline: Nov 27, 2006 http://www.tauworkshop.com/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 Deadline: Dec 1, 2006 http://www.nocsymposium.org/ ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 Deadline: Dec 15, 2006 http://www.inf.ufrgs.br/isvlsi2007/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 Deadline: Dec 20, 2006 http://www.iess.org/ MSE'07 - Int'l Conference on Microelectronic Systems Education San Diego, CA Jun 3-4, 2007 Deadline: Jan 15, 2007 http://www.mseconference.org/ ============================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- ISOCC'06 - Int'l SoC Design Conference Seoul, Korea Oct 26-27, 2006 http://www.isocc.org/ ICCAD'06 - Int'l Conference on Computer-Aided Design San Jose, CA Nov 5-9, 2006 http://www.iccad.com/ PDCS'06 - Int'l Conference on Parallel and Distributed Computing and Systems Dallas, TX Nov 13-15, 2006 http://www.iasted.org/conferences/2006/Dallas/pdcs.htm CSS'06 - Conference on Circuits, Signals and Systems San Francisco, CA Nov 20-22, 2006 http://www.iasted.org/newsletter/2006/css2.htm IP-SOC'06 - IP Based SoC Design Grenoble, France Dec 6-7, 2006 http://www.us.design-reuse.com/ipsoc2006/ ThETA'07 - Int'l Conference on Thermal Issues in Emerging Technologies: Theory and Applications Cairo, Egypt Jan 3-6, 2007 http://www.thetaconf.org VLSI'07 - Int'l Conference on VLSI Design Bangalore, India Jan 6-10, 2007 http://www.vlsiconference.com/2007/ ASPDAC'07 - Asia and South Pacific Design Automation Conference Yokohama, Japan Jan 23-26, 2007 http://www.aspdac.com/aspdac2007/ FPGA'07 -Int'l Symposium on Field-Programmable Gate Arrays Monterey, CA Feb 18-20, 2007 http://conferences.ece.ubc.ca/isfpga2007/ TAU'07 - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Austin, TX Feb 26-27, 2007 http://www.tauworkshop.com/ SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 http://www.splconf.org/ GLSVLSI'07 - Great Lakes Symposium on VLSI Stresa-Largo Maggiore, Italy Mar 11-13, 2007 http://www.glsvlsi.org/ LATW'07 - Latin-American Test Workshop Peru Mar 11-14, 2007 http://www.latw.net/ ASYNC'07: Int'l Symposium on Asynchronous Circuits and Systems Berkeley, CA Mar 12-14, 2007 http://conferences.computer.org/async2007/ SLIP'07 - System Level Interconnect Prediction Workshop Austin, TX Mar 17-18, 2007 http://www.sliponline.org/ ISPD'07 - Int'l Symposium on Physical Design Austin, TX Mar 18-21, 2007 http://www.ispd.cc/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 http://www.nocsymposium.org/ ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 http://www.inf.ufrgs.br/isvlsi2007/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 http://www.iess.org/ MSE'07 - Int'l Conference on Microelectronic Systems Education San Diego, CA Jun 3-4, 2007 http://www.mseconference.org/ DAC'07 - Design Automation Conference San Diego, CA Jun 4-8, 2007 http://www.dac.com/ ============================================================================== Call For Papers --------------------- ACM GLSVLSI 2007 2nd Call For Papers http://www.glsvlsi.org/ The 17th edition of GLSVLSI will be held March 11-13, 2007, in Stresa - Lago Maggiore, Italy, the first time in Europe. Original, unpublished papers, describing research in the general area of VLSI are solicited. Both theoretical and experimental research results are welcome. Proceedings will be published by the ACM and will be included in the SIGDA compendium CD-ROM. Program Tracks * VLSI Design (Chair: Massoud Pedram, University of Southern California): design of ASICs, microprocessors and micro-architectures, embedded processors, analog/digital/mixed-signal systems, multi-chip modules, FPGAs. * VLSI Circuits (Chair: Jamil Kawa, Synopsys): analog/digital/mixed-signal circuits, RF and communication circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits. * Computer-Aided Design (Chair: Martin Wong, UI at Urbana-Champaign): hardware/software co-design, logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction), algorithms and complexity analysis. * Low Power and Power Aware Design (Chair: Gang Qu, University of Maryland): circuits, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools. * Testing, Reliability, Fault-Tolerance (Chair: Jacob Abraham, UT Austin): digital/analog/mixed-signal testing, design for testability and reliability, online testing techniques, static and dynamic defect- and fault-recoverability, and variation-aware design. * Emerging Technologies (Chair: Mircea Stan, University of Virginia): nanotechnology, molecular electronics, quantum devices, biologically-inspired computing, single electron transistors, resonant tunneling devices, VLSI aspects of sensor and sensor network, and CAD tools for emerging technology devices and circuits. Best Student Paper Award A "Best Student Paper Award" will be voted on by the technical program committee. Only papers with a student as first author will be eligible. A laptop, generously donated by Intel, will be awarded to the winner at the symposium. Schedule * Paper Submission Deadline: November 10th, 2006 * Acceptance Notification: December 22nd, 2006 * Camera-Ready Paper Due: January 8th, 2007 ============================================================================== Conference Proceedings Added to the ACM Digital Library --------------------------------------------------------- Proceedings of the following conferences are now available in the ACM Digital Library. http://portal.acm.org/dl.cfm GECCO 2006 ICCAD 2005 FPGA 2005 DATE 2005 DAC 2005 GLSVLSI 2005 ISLPED 2005 ============================================================================== Table of Contents - the Lastest Issue of ACM Trans. on Design Automation ------------------------------------------------------------------------ Introduction to special issue: Novel paradigms in system-level design Massoud Pedram Pages: 535 - 536 http://delivery.acm.org/10.1145/1150000/1142981/p535-introduction.pdf?key1=1142981&key2=0056121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 System level design paradigms: Platform-based design and communication synthesis Alessandro Pinto, Alvise Bonivento, Allberto L. Sangiovanni-Vincentelli, Roberto Passerone, Marco Sgroi Pages: 537 - 563 http://delivery.acm.org/10.1145/1150000/1142982/p537-pinto.pdf?key1=1142982&key2=6256121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Computation and communication refinement for multiprocessor SoC design: A system-level perspective Radu Marculescu, Umit Y. Ogras, Nicholas H. Zamora Pages: 564 - 592 http://delivery.acm.org/10.1145/1150000/1142983/p564-marculescu.pdf?key1=1142983&key2=9356121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Analysis and optimization of distributed real-time embedded systems Paul Pop, Petru Eles, Zebo Peng, Traian Pop Pages: 593 - 625 http://delivery.acm.org/10.1145/1150000/1142984/p593-pop.pdf?key1=1142984&key2=1656121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs Prabhat Mishra, Aviral Shrivastava, Nikil Dutt Pages: 626 - 658 http://delivery.acm.org/10.1145/1150000/1142985/p626-mishra.pdf?key1=1142985&key2=0856121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Warp Processors Roman Lysecky, Greg Stitt, Frank Vahid Pages: 659 - 681 http://delivery.acm.org/10.1145/1150000/1142986/p659-lysecky.pdf?key1=1142986&key2=6956121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Module placement for fault-tolerant microfluidics-based biochips Fei Su, Krishnendu Chakrabarty Pages: 682 - 710 http://delivery.acm.org/10.1145/1150000/1142987/p682-su.pdf?key1=1142987&key2=2166121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing Narender Hanchate, Nagarajan Ranganathan Pages: 711 - 739 http://delivery.acm.org/10.1145/1150000/1142988/p711-hanchate.pdf?key1=1142988&key2=1366121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Simultaneous placement with clustering and duplication Gang Chen, Jason Cong Pages: 740 - 772 http://delivery.acm.org/10.1145/1150000/1142989/p740-chen.pdf?key1=1142989&key2=0566121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan Pages: 773 - 796 http://delivery.acm.org/10.1145/1150000/1142990/p773-bhanja.pdf?key1=1142990&key2=4666121611&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 ============================================================================== Upcoming funding opportunities ------------------------------- ASEE Office of Naval Research (ONR) Summer Faculty Research Program Deadline: December 1, 2006 http://www.asee.org/fellowships/summer/index.cfm DOD Young Faculty Award Deadline: December 5, 2006 http://www.grants.gov/search/search.do?oppId=10908&mode=VIEW Experimental and Theoretical Development of Quantum Information Science Deadline: December 11, 2006 http://www.arl.army.mil/main/Main/DownloadedInternetPages/CurrentPages/DoingBusinesswithARL/research/QC06Final6Jul06.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF NSF-SIA/NRI Graduate Student and Postdoctoral Fellow Supplements to NSF Centers in Nanoelectronics (NSF 06-051) Deadline: November 17, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=501009&org=CISE&from=home Computer Systems Research (CSR) (NSF 05-629) Deadline: Second Friday in November http://www.nsf.gov/pubs/2005/nsf05629/nsf05629.htm Information and Intelligent Systems: Advancing Human-Centered Computing, Information Integration and Informatics, and Robust Intelligence (NSF 06-572) Deadline: October 19, 2006 for Large Projects November 02, 2006 for Medium Projects December 06, 2006 for Small Projects http://www.nsf.gov/pubs/2006/nsf06572/nsf06572.htm Cyber Trust (CT) (NSF 06-517) Deadline: First Monday in February http://www.nsf.gov/pubs/2006/nsf06517/nsf06517.htm Active Nanostructures and Nanosystems (ANN) (NSF 06-595) Deadline: November 15, 2006 http://www.nsf.gov/pubs/2006/nsf06595/nsf06595.htm Power, Controls and Adaptive Networks (PCAN) Deadline: September 7, 2006 - October 7, 2006 http://nsf.gov/funding/pgm_summ.jsp?pims_id=13380 Advanced Learning Technologies (ALT) (NSF 06-535) Deadline: April 25, 2007 http://www.nsf.gov/pubs/2006/nsf06535/nsf06535.htm DARPA Cognitive Information Processing Technology (BAA02-21) Deadline: June 5, 2007 http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm NASA Applied Information Systems Research Deadline: January 30, 2007 http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId={0B64DB41-8F7D-C949-44CD-9D04A484B653}&path=open Others Microsoft Research New Faculty Fellowship Program Deadline: October 30, 2006 http://research.microsoft.com/nff/eligibility.aspx ============================================================================== Call For Papers ------------------ ARC2007 International Workshop on Applied Reconfigurable Computing Mangaratiba, Rio de Janeiro, Brazil March 27-29, 2007 http://www.arc-workshop.org/arc2007 e-mail: arc2007@icmc.usp.br Important Dates: Submission deadline: 20 November, 2006 Notification to authors: 22 December, 2006 Camera-Ready Submission: 08 January, 2007 Registration: begins 29 December, 2006 **************************************************************** The best papers of ARC will be invited to submit to a special issue of the *International Journal of Electronics* (Taylor & Francis Group) dedicated to ARC2007. **************************************************************** APPLIED RECONFIGURABLE COMPUTING Reconfigurable computing technologies offer the promise of substantial performance gains over traditional architectures viathe customizing, even at runtime, the topology of the underlyingarchitecture to match the specific needs of a given application.Contemporary configurable architectures allow for the definition of architectures with functional and storage units that match in function, bit-width and control structures the specific needs of a given computation. The flexibility enabled by reconfiguration is also seen as a basic technique for overcoming transient failures in emerging device structures. ARC aims at bringing together researchers and practitioners of reconfigurable computing with an emphasis on practical applications of this promising technology. This year's workshop will have a series of international invited speakers that will express their view on the future of reconfigurable technology. MEETING VENUE The workshop will be held at the Portobello Hotel in Mangaratiba, Rio de Janeiro, Brazil, on March 27-29, 2007. Mangaratiba is located approximately 90 Km (56 miles) from downtown rio de Janeiro (please check the ARC 2007 website for information regarding local transportation options to and from Rio's international airport). The event is organized by the Instituto de Ciências Matemáticas e de Computação (ICMC), Universidade de São Paulo, Brazil. WORKSHOP THEMES Topics of InterestSubmissions are solicited on a wide variety of topics related to applied reconfigurable computing, including but not limited to: * Methods and Tools (High-Level Compilers, Simulation,Estimation, Design space exploration, Languages to programreconfigurable systems, etc.) * Architectures (Fine-grained, coarse-grained, and mixed--grained, Multi-processor-based reconfigurable platforms,Microprocessors with tightly-coupled reconfigurable hardware,etc.) * Applications (High-Performance Systems, use of reconfigurable computing in embedded systems, robotics, digital signal processing, etc.) * Teaching reconfigurable computing * Surveys and Future Trends * Benchmarks (papers presenting benchmarks publicly available to be used by the reconfigurable computing community are especiallywelcome) SUBMISSION INFORMATION Authors are invited to submit original contributions in English including, but not limited to, the areas of interest mentioned above. Papers should be submitted electronically in PDF formatfollowing the LNCS formating guidelines.See: http://www.springer.de/comp/lncs/authors.html Submissions must identify the format of the contribution aseither, long papers, 12 pages maximum and which should includemainly accomplished results, or as short papers (6 pages maximumto be composed of work in progress or report recent developments. The paper submission site is located:http://conferenceserver.rnl.ist.utl.pt/conftool which can also be accessed via the ARC 2007 website indicatedabove. Each paper will be reviewed by at least three programcommittee members. In order to maintain a blind review information about authors should not be included in thesubmission. ORGANIZING COMMITTEE General Chairs Eduardo Marques, University of São Paulo, Brazil Koen Bertels, Delft University of Technology, The Netherlands Program Chair Pedro C. Diniz, IST/INESC-ID, Portugal Steering Committee George Constantinides, Imperial College, UK João M. P. Cardoso, IST/INESC-ID, Portugal Koen Bertels, Delft Univ. of Technology, The Netherlands Mladen Berekovic, IMEC, Leuven, Belgium Pedro C. Diniz, IST/INESC-ID, Portugal Stamatis Vassiliadis, Delft Univ. of Technology, The Netherlands Walid Najjar, University of California Riverside, USA Proceedings Chair Marcio M. Fernandes, Unimep, Brazil Special Journal Edition Chairs George Constantinides, Imperial College, UK João M. P. Cardoso, IST/INESC-ID, Portugal Publicity Chair Fernanda G. L. Kastensmid, UFRGS, Brazil Sponsorship Chair Denis F. Wolf, University of São Paulo, Brazil Finance Chair Jorge L. Silva, University of São Paulo, Brazil Local Arrangements Chairs Marcos Santana, University of São Paulo, Brazil Regina C. Santana, University of São Paulo, Brazil Ricardo Menotti, UTFPR, Brazil Vanderlei Bonato, University of São Paulo, Brazil Web Chair Carlos Almeida Jr., University of São Paulo, Brazil Secretariat Marilia Marino, University of São Paulo, Brazil PROGRAM COMMITTEE Andreas Koch, TU Darmstadt, Germany Andy Pimentel, University of Amsterdam, The Netherlands António Ferrari, University of Aveiro, Portugal Bernard Pottier, University of West Brittany (UBO), France Carl Ebeling, University of Washington, USA Eduardo Marques, University of São Paulo, Brazil George Constantinides, Imperial College, UK Hideharu Amano, Keio University, Japan Horácio Neto, INESC-ID/IST, Portugal Jeff Arnold, Strech Inc., USA Joachim Pistorius, Altera Corp., USA João M. P. Cardoso, IST/INESC-ID, Portugal Joon-seok Park, Inha University, Seoul, South Korea José Nelson Amaral, University of Alberta, Canada José Sousa, IST/INESC-ID, Portugal Juan Carlos de Martin, Politecnico de Torino, Italy Jürgen Becker, Universität Karlsruhe (TH), Germany Koen Bertels, Delft Univ. of Technology, The Netherlands Laura Pozzi, University of Lugano (USI), Switzerland Marco Platzner, University of Paderborn, Germany Markus Weinhardt, PACT Informationstechnologie AG, Germany Maria-Cristina Marinescu, IBM T. J. W. Research Center, USA Mihai Budiu, Microsoft Research, USA Mladen Berekovic, IMEC vzw, Leuven, Belgium Nader Bagherzadeh, University of California, Irvine, USA Oliver Diessel, University of New South Wales, Australia Paul Chow, University of Toronto, Canada Pedro C. Diniz, IST/INESC-ID, Portugal Pedro Trancoso, University of Cyprus, Cyprus Peter Cheung, Imperial College, UK Phil James-Roxby, Xilinx Corp., USA Philip Leong, The Chinese University of Hong Kong, China Ranga Vemuri, University of Cincinnati, USA Reiner Hartenstein, University of Kaiserslautern, Germany Roger Woods, The Queen's University of Belfast, UK Roman Hermida, Universidad Complutense, Madrid, Spain Russell Tessier, University of Massachusetts, USA Ryan Kastner, University of California, Santa Barbara, USA Seda Ö. Memik, Northwestern University, USA Stamatis Vassiliadis, Delft Univ. of Technology, The Netherlands Stephan Wong, Delft University of Technology, The Netherlands Tarek El-Ghazawi, The George Washington University, USA Tim Callahan, Carnegie Mellon University, USA Tsutomu Sasao, Kyushu Institute of Technology, Japan Walid Najjar, University of California Riverside, USA Wayne Luk, Imperial College, UK ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. 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