=============================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org =============================================================================== 1 October 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 19 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What Is OpenAccess Gear? Contributing author: Philip Chong, Cadence Berkeley Laboratories Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Call For Papers - ARC 2007 2007 International Workshop on Applied Reconfigurable Computing Fernanda G. L. Kastensmid (6) Upcoming Funding Opportunities Qinru Qiu (7) Call For Papers - ISPD 2007 2007 ACM International Symposium on Physical Design Prashant Saxena (8) Call For Papers - TAU 2007 2007 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Michael Orshansky =============================================================================== Dear ACM/SIGDA members, This issue includes the new "What Is OpenAccess Gear?" column. It also has new call for papers for ARC'07. In addition to a fresh batch of SIGDA news, we updated the lists of upcoming deadlines and events, as well as the funding opportunities. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "Intel Manufactures 80-core TeraFlop Processor" http://www.reghardware.co.uk/2006/09/26/intel_teraflop_processor/ Intel has produced an 80-core chip with teraflop performance capabilities. The proof-of-concept chip is not x86-compatible. Each core is designed at 3.1GHz and is mounted with 20MB of SRAM stacked up on top of the die. Connecting memory this way provides an aggregate bandwidth of a trillion bytes per second. "A Breakthrough in Quantum Communication: Sending Entangled Qubits" http://viterbi.usc.edu/news/news/2006/entanglement-unties-a.htm A new approach by three theorists working at the USC Viterbi School of Engineering dramatically changes the rules of the game. They report in Science that adding entangled photons as part of the message stream opens the door to using the entire error coding playbook. "This method allows the use of highly efficient turbo codes, operating close to the theoretical limits of efficiency, something never before possible," says Todd Brun, an associate professor in the Viterbi School's department of electrical engineering, who is lead author on the study. "Experimental Breakthrough in Teleportation" http://www.cnn.com/2006/TECH/science/10/04/teleportation.reut/index.html?section=cnn_topstories Physicists in Denmark have teleported information from light to matter. Until now scientists have teleported similar objects such as light (photons) or single atoms over short distances from one spot to another in a split second. But Professor Eugene Polzik and his team at the Niels Bohr Institute at Copenhagen University in Denmark have made a breakthrough by using both light and matter. "It is one step further because for the first time it involves teleportation between light and matter, two different objects. One is the carrier of information and the other one is the storage medium," Polzik explained in an interview on Wednesday. The experiment involved for the first time a macroscopic atomic object containing thousands of billions of atoms. They also teleported the information a distance of half a meter but believe it can be extended further. "Teleportation between two single atoms had been done two years ago by two teams but this was done at a distance of a fraction of a millimeter," Polzik, of the Danish National Research Foundation Center for Quantum Optics, explained. "Our method allows teleportation to be taken over longer distances because it involves light as the carrier of entanglement," he added. "Google Launches Search Service for Computer Code" http://www.washingtonpost.com/wp-dyn/content/article/2006/10/05/AR2006100500053.html Similar to how a consumer might type a few words into a standard Google search box to find an answer, programmers can seek out relevant lines of code at http://google.com/codesearch and find a range of search results that link them to answers. "NSF Awards Texas Advanced Computing Ctr $59 Million for High-Perf Computing" http://www.utexas.edu/opa/news/2006/09/research28.html The University of Texas at Austin's Texas Advanced Computing Center (TACC) and its partners at Cornell University and Arizona State University have won a five-year, $59 million grant from the National Science Foundation (NSF) to purchase, operate, and maintain a high-performance computing (HPC) system with the aim of providing scientists and engineers throughout the United States with unprecedented computing power. TACC has teamed up with Sun Microsystems to implement a supercomputer that will by its final configuration perform more than 420 teraflops, and boast more than 100 terabytes of memory and 1.7 petabytes of disk storage. "Scientists Discuss New Frontiers In Single-molecule Research" http://www.sciencedaily.com/releases/2006/09/060915203506.htm Not long ago, the idea of conducting an experiment on a single strand of DNA seemed far beyond the realm of science. But thanks to rapid advances in microscopy in the last decade, researchers can now watch a single gene being transcribed from DNA-one atom at a time- or observe the activity of a protein molecule as it moves inside a living cell. "Intel, UCSB Tout Scalable On-chip Silicon Laser" http://www.eetimes.com/showArticle.jhtml?articleID=193001495 Researchers at Intel and the University of California, Santa Barbara have made what they say is a major breakthrough in making hybrid silicon lasers that they suggest could have a huge impact on chip-to chip communication and on optical communications networks. The researchers caution that commercializing the laser chip could take till the end of the decade, but suggest being able to place hundreds or thousands of data-carrying light beams on standard industry chips will have the potential "to reshape the data center, could improve the way fiber is delivered to the home and potentially trigger the next paradigm shift since the introduction of fiber." Such devices could handle data rates of between 20Gbit/s to 40Gbit/s, up from today's 10Gbit/s. "New Features in VIM 7.0" http://linuxhelp.blogspot.com/2006/09/visual-walk-through-of-couple-of-new.html VIM and GVIM are the latest reincarnations of the popular Unix editor VI, and provide an astronomic number of functionalities that can be used with visual or keyboard-only interfaces. VIM and GVIM have been included with all major Linux distributions for many years. New features in VIM 7.0 include on-the-fly spell-checking, bracket highlighting, omni-completion, browser-like tabs, multiple branches of undo, and time-driven undo. "Startup Defines Next-generation FPGA" http://www.eetimes.com/showArticle.jhtml?articleID=193000884 Velogix Inc. is developing a high-performance programmable-logic platform to run the billions of operations each second needed by applications like video and imaging, test and measurement, and communications. The platform is planned for unveiling by year's end. "E-beams Falling Behind Moore's Law" http://www.eetimes.com/showArticle.jhtml?articleID=193004187 Despite a trend towards flat photomask costs, electron-beam reticle writers are falling behind and are not keeping up with Moore's Law, warned a mask maker at Intel Corp. There is a 25 percent increase in mask write times for every technology node. In fact, the average write times for a critical layer in a photomask has jumped to 24 hours, up from 5-to-6 hours in recent times, Sowers said. "SIA Warns of Declining U.S. Production Capacity" http://www.eetimes.com/showArticle.jhtml?articleID=193003931 The U.S. share of advanced semiconductor production capacity is in steep decline, according to the Semiconductor Industry Association (SIA), plummeting from 35 percent of global capacity five years ago to an estimated 11 percent in 2006. Nevertheless, the industry is thriving. The SIA reported that global sales of semiconductors totaled $20.1 billion in July, up over 11.5 percent from July 2005. It said capital spending in 2006 is expected to total approximately 22 percent of semiconductor sales. The only way to reverse the decline in the US share is to boost investment in new fabs, SIA said. "Synopsys Claims Tripling of TetraMAX ATPG Tool Performance" http://www.eetimes.com/showArticle.jhtml?articleID=193006149 Synopsys Inc. said the latest version of its TetraMAX automatic test pattern generation (ATPG) product achieves a typical speed-up of at least 3x from previous version, across all design styles. This includes ATPG runtime for both stuck-at and transition delay testing. TetraMAX does not require partitioning of a large SoCs and can generate patterns for the entire design at once. Previous revision of TetraMAX offered a 4x speed-up. "IBM, Chartered, Infineon and Samsung Discuss 32nm Technologies" http://www.eetimes.com/showArticle.jhtml?articleID=193100380 At a press event in Santa Clara on Thursday (Sept. 28), IBM's "fab club" or process-development partners - Chartered, Infineon and Samsung - provided a glimpse of possible candidates for the "common platform" at the 32nm node. The target date for the group's 32-nm process ramp is late-2009 or early-2010, or approximately two years after its 45-nm ramp, keeping up with Moore's Law. For the 32-nm node, the "fab club" is looking at high-k dielectric materials, metal gates, ultra low-k films and silicon germanium. 193-nm immersion lithography with double-patterning techniques may be used at that node, but Extreme Ultra-Violet (EUV) lithography is unlikely. To this end, ASML has quietly inserted 193-nm immersion with double-patterning techniques on its roadmap, claiming that the technology is the "only" lithographic solution for the 2008 and 2009 timeframe. "Sematech, SEMI to Assess 450-mm Efforts" http://www.eetimes.com/showArticle.jhtml?articleID=193006341 Chip-making consortium International Sematech has joined forces with the Semiconductor Equipment and Materials International (SEMI) trade group to develop and assess capabilities for the possible transition from 300- to 450-mm wafer fabs. Squeezed between rising manufacturing costs and penny-pinching end markets, semiconductor fab productivity has become an industry mantra, inspiring a new Sematech program called 300 mm Prime. The program, announced in January, aims to boost productivity in 300-mm fabs and ease the transition to tomorrow's pizza-sized 450-mm silicon wafers. As part of the effort, Sematech (Austin, Texas) and SEMI, based here, have established two engineering groups to engage suppliers and chip makers. The groups are called the Manufacturing Technology Forum (MTF) and the Joint Productivity Working Group (JPWG). Inputs from both groups will help Sematech to develop a 300 Prime capability assessment - with details on potential benefits and cost reductions - through 2006 and beyond. "IBM 'Fab Club' Narrows Options For 32-nm" http://www.eetimes.com/showArticle.jhtml?articleID=193100380 IBM's "fab club" or process-development partners - Chartered, Infineon and Samsung - did not disclose the exact details about its 32-nm technology, but it did provide a glimpse of possible candidates for the "common platform" at that node. The group's 32-nm schedule is approximately two years after its 45-nm ramp, which keeps the group on par with Moore's Law. "There is a business requirement to stay on the two-year cycle," Lu said in an interview at the event. For the 32-nm node, the "fab club" is looking at several obvious technology candidates: high-k dielectric materials, metal gates, ultra low-k films and silicon germanium, she said. However, it's unlikely that extreme ultraviolet (EUV) lithography will be ready in time for the 32-nm "half-pitch" node, according to observers. "I think EUV has a lot of challenges," she said. The strategy somewhat reflects its key lithography vendor: ASML Holding NV. Recently, ASML quietly inserted 193-nm immersion with double-patterning techniques on its roadmap, claiming that the technology is the "only" lithographic solution for the 2008 and 2009 timeframe. "Start-up Offers Free Layout-verification and DRC-repair Tools" http://www.eetimes.com/showArticle.jhtml?articleID=193100951 Startup CAD Science Inc. offers the fastest GDSII viewing and full-chip design rule-checking (DRC) tools. The single-processor 32-bit version is available for free, and the company plans to market the 64-bit version. Also available are DRC repair, technology migration and rules-based OPC modifications. The tool doesn't have all the detailed features of commercial DRC programs, but is the fastest program for single CPUs. The tools feature an innovaitve compact geometry representation that bears resemblence to the Oasis datamodel, but improves on it. It includes a fast geometry search engine a fast DRC engine and "innovative" hierarchical operations for layout modification "EDA Consortium Reports 15% Revenue Growth in Second Quarter 2006" http://biz.yahoo.com/prnews/061002/sfm022.html?.v=62 The EDA Consortium's Market Statistics Service (MSS) today announced that the electronic design automation (EDA) industry revenue for Q2 of 2006 grew 15% to $1,256 million, versus $1,091 million in Q2 2005, due in part to new company participation. Total product revenues, without services, was up 15% to $1,180 million in Q2 of 2006 vs. $1,028 million in the same quarter of 2005. "Panel Will Spotlight ''What Fabless Companies Really Want'' at 2006 FSA Suppliers Expo and Conference" http://home.businesswire.com/portal/site/google/index.jsp?ndmViewId=news_view&newsId=20060926005275&newsLang=en FSA, the voice of the global fabless business model, announces a 2006 FSA Suppliers Expo and Conference panel focusing on design for manufacturing (DFM) and the development of a standard form of interface. The panel will take place Wednesday, October 11 from 4:30-5:30 p.m. PT, at the San Jose McEnery Convention Center in San Jose, Calif./Electronic News "FPGAs Ride Tools Into ASIC Territory" http://www.elecdesign.com/Articles/Index.cfm?AD=1&ArticleID=13477 When pondering your next-generation system design, you may ask yourself whether the spiraling mask costs have priced you out of the ASIC game. You'll perform the requisite analyses of performance requirements (high) versus cost (much higher) and begin wondering whether another implementation path might serve the end product in a more costeffective fashion. And you'll consider the notion of using FPGAs, at least for prototyping if not for production. FPGAs? Can they have the horsepower to make that nextgeneration design sing? With major FPGA vendors now at the 90-nm process node, it's quite likely they do. "Cadence, SMIC Create 90nm Low-Power Reference Flow" http://www.edn.com/index.asp?layout=article&articleid=CA6369778&ref=nbednnenews&industryid=2813 To address the increasing needs of designers developing ICs for the computing, consumer, networking and wireless markets, electronic design market leader Cadence Design Systems Inc. and Shanghai, China-based foundry Semiconductor Manufacturing International Corp. (SMIC) said today they have jointly developed a low-power digital reference flow to support SMIC's 90nm process technology. "The Mentor model: Q&A with Walden Rhines, chairman and CEO, Mentor Graphics" http://www.digitimes.com/news/a20060908VL201.html Mentor Graphics is routinely assessed as the third of the "big three" in EDA, but in practice, this pigeon-holing is simply a comparative reference to revenues. The truth is that in a period of little to no growth in the EDA industry, Mentor has grown at over twice the industry average. At a recent EDA Tech Forum in Hsinchu, Taiwan, DigiTimes.com had an opportunity to talk with Walden Rhines, chairman and CEO of Mentor Graphics, about the company's strategy and business model, how the company is differentiated, what drives growth in the EDA industry, and what lies ahead in EDA-driven semiconductor design. "New Class of Formal Software Verification Engines Reaching Maturity" http://home.businesswire.com/portal/site/google/index.jsp?ndmViewId=news_view&newsId=20060926005502&newsLang=en SRI International's "Yices" technology won a competition of formal verification engines at the Conference on Automated Verification (CAV) held in Seattle, Washington, on August 20, 2006. The competition highlighted the arrival of a new class of engines that can address satisfiability modulo theories (SMT). The best of these verifiers now have wide capabilities and very impressive performance. Formal verification is used to prove the properties of a system or to prove that it does not have a certain defect. Formal verification goes beyond software testing and is particularly important in systems such as those used for drive-by-wire, fly-by-wire and other safety critical systems. ============================================================================== What Is OpenAccess Gear? ------------------------- Philip Chong, Cadence Berkeley Laboratories The complex design flows prevalent in the EDA industry today present a challenge for academic researchers. Many experiments of potential interest revolve around the interaction between a variety of EDA components. For example, a researcher interested in developing and studying a physically-aware synthesis flow must be able to combine physical and logical information in a design database, and co-ordinate placement, synthesis, and timing analysis tools. This can be a daunting task in an academic setting, where developing these components from scratch can be prohibitively time-consuming, and purchasing these components can be too costly. The OpenAccess Gear (OA Gear) project was originally started by Cadence Berkeley Labs to facilitate academic research and development of complex EDA flows and tools. OA Gear is a toolkit of utilities written in C++ [1] and built on the industry-standard OpenAccess EDA database [2]. Among the OA Gear packages are a static timing analysis tool, an interface to the Capo placement tool developed at UCLA and University of Michigan, and an extension to OpenAccess for logical/functional representation. Such components can be combined to form the foundation of the aforementioned physically-aware synthesis flow, or other interesting research tools can be written to take advantage of these packages. OA Gear is freely available in source code form, making it easy to integrate into research projects. As a concrete example of how OA Gear can facilitate academic research, the work presented by Zhong Xiu and Rob Rutenbar at the 2005 Design Automation Conference ("Timing-Driven Placement by Grid-Warping") used the OA Gear timing analysis tool to provide timing-driven capabilities for their novel placement technique [3]. In a related paper published at the 2005 International Symposium on Physical Design, the authors indicate that OA Gear saved them several months of implementation and coding effort [4] Another recent example of the use of OA Gear in academic research was the programming challenge held in conjunction with the 2006 International Workshop on Logic And Synthesis [5]. For the challenge, students were tasked to develop a synthesis tool of their choice using the OA Gear logical/functional representation layer; winners were determined by a panel of judges, who also dispensed small cash prizes and stipends for travel to the workshop. There were two winning entries chosen, one a fast simulation and equivalence checking tool written by Kai-hui Chang and David Papa from University of Michigan [6], the other a tool using a novel SAT sweeping algorithm written by Nathan Kitchen and Qi Zhu from UC Berkeley [7]. (The latter work also won a best paper award at the 2006 Design Automation Conference.) Both winning entries have been contributed by their authors to OA Gear and are now part of the toolkit. For more information about OA Gear and to download the toolkit, see the OA Gear web site at http://openedatools.si2.org/oagear/ . Links to obtain information about OpenAccess itself can be found on the OA Gear web site as well. References [1] Open Access http://www.si2.org/?page=69 [2] OA Gear http://openedatools.si2.org/oagear/ [3] Z. Xiu, R. A. Rutenbar, "Timing-driven placement by grid-warping," DAC 2005, pp. 585-591. [4] Z. Xiu et al, "Early research experience with OpenAccess gear: an open source development environment for physical design," ISPD 2005, pp. 94 - 100. [5] R. Goering, "Synthesis contest winners offer new algorithms", http://www.eetimes.com/showArticle.jhtml?articleID=188702906 EE Times, June 2006. [6] K.-H. Chang, D. A. Papa, I. L. Markov and V. Bertacco, "Fast Simulation and Equivalence Checking Using OAGear," IWLS 2006, pp. 270-271. [7] Q. Zhu, N. Kitchen, A. Kuehlmann, A. Sangiovanni-Vincentelli, "SAT sweeping with local observability don't-cares," DAC 2006, pp. 229-234. ============================================================================== Submission deadlines: --------------------- ISCAS'07 - Int'l Symposium on Circuits and Systems New Orleans, LA May 27-30, 2007 Deadline: Oct 13, 2006 http://www.iscas2007.org/ ISPD'07 - Int'l Symposium on Physical Design Austin, TX Mar 18-21, 2007 Deadline: Oct 12, 2006 http://www.ispd.cc/ SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 Deadline: Oct 23, 2006 http://www.splconf.org/ GLSVLSI'07 - Great Lakes Symposium on VLSI Stresa-Largo Maggiore, Italy Mar 11-13, 2007 Deadline: Nov 10, 2006 http://www.glsvlsi.org/ LATW'07 - Latin-American Test Workshop Peru Mar 11-14, 2007 Deadline: Nov 12, 2006 http://www.latw.net/ DAC'07 - Design Automation Conference San Diego, CA Jun 4-8, 2007 Deadline: Nov. 20, 2006 http://www.dac.com/ SLIP'07 - System Level Interconnect Prediction Workshop Austin, TX Mar 17-18, 2007 Deadline: Nov 24, 2006 http://www.sliponline.org/ TAU'07 - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Austin, TX Feb 26-27, 2007 Deadline: Nov 27, 2006 http://www.tauworkshop.com/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 Deadline: Dec 1, 2006 http://www.nocsymposium.org/ ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 Deadline: Dec 15, 2006 http://www.inf.ufrgs.br/isvlsi2007/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 Deadline: Dec 20, 2006 http://www.iess.org/ ============================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- ISOCC'06 - Int'l SoC Design Conference Seoul, Korea Oct 26-27, 2006 http://www.isocc.org/ ICCAD'06 - Int'l Conference on Computer-Aided Design San Jose, CA Nov 5-9, 2006 http://www.iccad.com/ PDCS'06 - Int'l Conference on Parallel and Distributed Computing and Systems Dallas, TX Nov 13-15, 2006 http://www.iasted.org/conferences/2006/Dallas/pdcs.htm CSS'06 - Conference on Circuits, Signals and Systems San Francisco, CA Nov 20-22, 2006 http://www.iasted.org/newsletter/2006/css2.htm IP-SOC'06 - IP Based SoC Design Grenoble, France Dec 6-7, 2006 http://www.us.design-reuse.com/ipsoc2006/ ThETA'07 - Int'l Conference on Thermal Issues in Emerging Technologies: Theory and Applications Cairo, Egypt Jan 3-6, 2007 http://www.thetaconf.org VLSI'07 - Int'l Conference on VLSI Design Bangalore, India Jan 6-10, 2007 http://www.vlsiconference.com/2007/ ASPDAC'07 - Asia and South Pacific Design Automation Conference Yokohama, Japan Jan 23-26, 2007 http://www.aspdac.com/aspdac2007/ FPGA'07 -Int'l Symposium on Field-Programmable Gate Arrays Monterey, CA Feb 18-20, 2007 http://conferences.ece.ubc.ca/isfpga2007/ TAU'07 - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Austin, TX Feb 26-27, 2007 http://www.tauworkshop.com/ SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 http://www.splconf.org/ GLSVLSI'07 - Great Lakes Symposium on VLSI Stresa-Largo Maggiore, Italy Mar 11-13, 2007 http://www.glsvlsi.org/ LATW'07 - Latin-American Test Workshop Peru Mar 11-14, 2007 http://www.latw.net/ ASYNC'07: Int'l Symposium on Asynchronous Circuits and Systems Berkeley, CA Mar 12-14, 2007 http://conferences.computer.org/async2007/ SLIP'07 - System Level Interconnect Prediction Workshop Austin, TX Mar 17-18, 2007 http://www.sliponline.org/ ISPD'07 - Int'l Symposium on Physical Design Austin, TX Mar 18-21, 2007 http://www.ispd.cc/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 http://www.nocsymposium.org/ ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 http://www.inf.ufrgs.br/isvlsi2007/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 http://www.iess.org/ DAC'07 - Design Automation Conference San Diego, CA Jun 4-8, 2007 http://www.dac.com/ ============================================================================== Call For Papers ------------------ ARC2007 International Workshop on Applied Reconfigurable Computing Mangaratiba, Rio de Janeiro, Brazil March 27-29, 2007 http://www.arc-workshop.org/arc2007 e-mail: arc2007@icmc.usp.br Important Dates: Submission deadline: 20 November, 2006 Notification to authors: 22 December, 2006 Camera-Ready Submission: 08 January, 2007 Registration: begins 29 December, 2006 **************************************************************** The best papers of ARC will be invited to submit to a special issue of the *International Journal of Electronics* (Taylor & Francis Group) dedicated to ARC2007. **************************************************************** APPLIED RECONFIGURABLE COMPUTING Reconfigurable computing technologies offer the promise of substantial performance gains over traditional architectures viathe customizing, even at runtime, the topology of the underlyingarchitecture to match the specific needs of a given application.Contemporary configurable architectures allow for the definition of architectures with functional and storage units that match in function, bit-width and control structures the specific needs of a given computation. The flexibility enabled by reconfiguration is also seen as a basic technique for overcoming transient failures in emerging device structures. ARC aims at bringing together researchers and practitioners of reconfigurable computing with an emphasis on practical applications of this promising technology. This year's workshop will have a series of international invited speakers that will express their view on the future of reconfigurable technology. MEETING VENUE The workshop will be held at the Portobello Hotel in Mangaratiba, Rio de Janeiro, Brazil, on March 27-29, 2007. Mangaratiba is located approximately 90 Km (56 miles) from downtown rio de Janeiro (please check the ARC 2007 website for information regarding local transportation options to and from Rio's international airport). The event is organized by the Instituto de Ciências Matemáticas e de Computação (ICMC), Universidade de São Paulo, Brazil. WORKSHOP THEMES Topics of InterestSubmissions are solicited on a wide variety of topics related to applied reconfigurable computing, including but not limited to: * Methods and Tools (High-Level Compilers, Simulation,Estimation, Design space exploration, Languages to programreconfigurable systems, etc.) * Architectures (Fine-grained, coarse-grained, and mixed--grained, Multi-processor-based reconfigurable platforms,Microprocessors with tightly-coupled reconfigurable hardware,etc.) * Applications (High-Performance Systems, use of reconfigurable computing in embedded systems, robotics, digital signal processing, etc.) * Teaching reconfigurable computing * Surveys and Future Trends * Benchmarks (papers presenting benchmarks publicly available to be used by the reconfigurable computing community are especiallywelcome) SUBMISSION INFORMATION Authors are invited to submit original contributions in English including, but not limited to, the areas of interest mentioned above. Papers should be submitted electronically in PDF formatfollowing the LNCS formating guidelines.See: http://www.springer.de/comp/lncs/authors.html Submissions must identify the format of the contribution aseither, long papers, 12 pages maximum and which should includemainly accomplished results, or as short papers (6 pages maximumto be composed of work in progress or report recent developments. The paper submission site is located:http://conferenceserver.rnl.ist.utl.pt/conftool which can also be accessed via the ARC 2007 website indicatedabove. Each paper will be reviewed by at least three programcommittee members. In order to maintain a blind review information about authors should not be included in thesubmission. ORGANIZING COMMITTEE General Chairs Eduardo Marques, University of São Paulo, Brazil Koen Bertels, Delft University of Technology, The Netherlands Program Chair Pedro C. Diniz, IST/INESC-ID, Portugal Steering Committee George Constantinides, Imperial College, UK João M. P. Cardoso, IST/INESC-ID, Portugal Koen Bertels, Delft Univ. of Technology, The Netherlands Mladen Berekovic, IMEC, Leuven, Belgium Pedro C. Diniz, IST/INESC-ID, Portugal Stamatis Vassiliadis, Delft Univ. of Technology, The Netherlands Walid Najjar, University of California Riverside, USA Proceedings Chair Marcio M. Fernandes, Unimep, Brazil Special Journal Edition Chairs George Constantinides, Imperial College, UK João M. P. Cardoso, IST/INESC-ID, Portugal Publicity Chair Fernanda G. L. Kastensmid, UFRGS, Brazil Sponsorship Chair Denis F. Wolf, University of São Paulo, Brazil Finance Chair Jorge L. Silva, University of São Paulo, Brazil Local Arrangements Chairs Marcos Santana, University of São Paulo, Brazil Regina C. Santana, University of São Paulo, Brazil Ricardo Menotti, UTFPR, Brazil Vanderlei Bonato, University of São Paulo, Brazil Web Chair Carlos Almeida Jr., University of São Paulo, Brazil Secretariat Marilia Marino, University of São Paulo, Brazil PROGRAM COMMITTEE Andreas Koch, TU Darmstadt, Germany Andy Pimentel, University of Amsterdam, The Netherlands António Ferrari, University of Aveiro, Portugal Bernard Pottier, University of West Brittany (UBO), France Carl Ebeling, University of Washington, USA Eduardo Marques, University of São Paulo, Brazil George Constantinides, Imperial College, UK Hideharu Amano, Keio University, Japan Horácio Neto, INESC-ID/IST, Portugal Jeff Arnold, Strech Inc., USA Joachim Pistorius, Altera Corp., USA João M. P. Cardoso, IST/INESC-ID, Portugal Joon-seok Park, Inha University, Seoul, South Korea José Nelson Amaral, University of Alberta, Canada José Sousa, IST/INESC-ID, Portugal Juan Carlos de Martin, Politecnico de Torino, Italy Jürgen Becker, Universität Karlsruhe (TH), Germany Koen Bertels, Delft Univ. of Technology, The Netherlands Laura Pozzi, University of Lugano (USI), Switzerland Marco Platzner, University of Paderborn, Germany Markus Weinhardt, PACT Informationstechnologie AG, Germany Maria-Cristina Marinescu, IBM T. J. W. Research Center, USA Mihai Budiu, Microsoft Research, USA Mladen Berekovic, IMEC vzw, Leuven, Belgium Nader Bagherzadeh, University of California, Irvine, USA Oliver Diessel, University of New South Wales, Australia Paul Chow, University of Toronto, Canada Pedro C. Diniz, IST/INESC-ID, Portugal Pedro Trancoso, University of Cyprus, Cyprus Peter Cheung, Imperial College, UK Phil James-Roxby, Xilinx Corp., USA Philip Leong, The Chinese University of Hong Kong, China Ranga Vemuri, University of Cincinnati, USA Reiner Hartenstein, University of Kaiserslautern, Germany Roger Woods, The Queen's University of Belfast, UK Roman Hermida, Universidad Complutense, Madrid, Spain Russell Tessier, University of Massachusetts, USA Ryan Kastner, University of California, Santa Barbara, USA Seda Ö. Memik, Northwestern University, USA Stamatis Vassiliadis, Delft Univ. of Technology, The Netherlands Stephan Wong, Delft University of Technology, The Netherlands Tarek El-Ghazawi, The George Washington University, USA Tim Callahan, Carnegie Mellon University, USA Tsutomu Sasao, Kyushu Institute of Technology, Japan Walid Najjar, University of California Riverside, USA Wayne Luk, Imperial College, UK ============================================================================== Upcoming funding opportunities ------------------------------- ASEE Office of Naval Research (ONR) Summer Faculty Research Program Deadline: December 1, 2006 http://www.asee.org/fellowships/summer/index.cfm DOD Young Faculty Award Deadline: December 5, 2006 http://www.grants.gov/search/search.do?oppId=10908&mode=VIEW Experimental and Theoretical Development of Quantum Information Science Deadline: December 11, 2006 http://www.arl.army.mil/main/Main/DownloadedInternetPages/CurrentPages/DoingBusinesswithARL/research/QC06Final6Jul06.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF NSF-SIA/NRI Graduate Student and Postdoctoral Fellow Supplements to NSF Centers in Nanoelectronics (NSF 06-051) Deadline: November 17, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=501009&org=CISE&from=home Computer Systems Research (CSR) (NSF 05-629) Deadline: Second Friday in November http://www.nsf.gov/pubs/2005/nsf05629/nsf05629.htm Information and Intelligent Systems: Advancing Human-Centered Computing, Information Integration and Informatics, and Robust Intelligence (NSF 06-572) Deadline: October 19, 2006 for Large Projects November 02, 2006 for Medium Projects December 06, 2006 for Small Projects http://www.nsf.gov/pubs/2006/nsf06572/nsf06572.htm Cyber Trust (CT) (NSF 06-517) Deadline: First Monday in February http://www.nsf.gov/pubs/2006/nsf06517/nsf06517.htm Active Nanostructures and Nanosystems (ANN) (NSF 06-595) Deadline: November 15, 2006 http://www.nsf.gov/pubs/2006/nsf06595/nsf06595.htm Power, Controls and Adaptive Networks (PCAN) Deadline: September 7, 2006 - October 7, 2006 http://nsf.gov/funding/pgm_summ.jsp?pims_id=13380 Advanced Learning Technologies (ALT) (NSF 06-535) Deadline: April 25, 2007 http://www.nsf.gov/pubs/2006/nsf06535/nsf06535.htm DARPA Cognitive Information Processing Technology (BAA02-21) Deadline: June 5, 2007 http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm NASA Applied Information Systems Research Deadline: January 30, 2007 http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId={0B64DB41-8F7D-C949-44CD-9D04A484B653}&path=open Others Microsoft Research New Faculty Fellowship Program Deadline: October 30, 2006 http://research.microsoft.com/nff/eligibility.aspx ============================================================================== CALL FOR PAPERS - ISPD 2007 -------------------------------- ACM International Symposium on Physical Design http://www.ispd.cc March 18-21, 2007 Dolce Lakeway Resort and Spa Austin, TX (Sponsored by ACM SIGDA with Technical Co-sponsorship from IEEE CAS) The International Symposium on Physical Design provides a forum to exchange ideas and promote research on critical areas related to the physical design of VLSI systems. All aspects of physical design (including interactions with architecture, behavioral- and logic-level synthesis, and back-end performance analysis and verification) are within the scope of the Symposium. Target domains include semi-custom and full-custom IC, MCM and FPGA based systems. Applications of classical physical design techniques to emerging technologies such as MEMs and microfluidics are also encouraged. Following its fourteen predecessors, the 2007 symposium will highlight key new directions and leading-edge theoretical and experimental contributions to the field. The ACM Press will publish accepted papers in the Symposium proceedings. Topics of interest include but are not limited to: Floorplanning and interconnect planning Partitioning, placement and routing Estimation and modeling Physical design for manufacturability and yield Special structures for clocking and power networks Interactions with architecture, behavioral- and logic synthesis Management of design data, constraints and hierarchies Analysis and management of power dissipation Timing and crosstalk issues in physical design Design for large and/or high-performance systems Circuit performance measurements in a PD context New physical design methodologies and paradigms Physical design of analog, RF and mixed systems Applications of PD to emerging technologies such as MEMs and microfluidics Physical design in parallel / distributed / Web environments IMPORTANT DATES Submission deadline October 12, 2006 Acceptance notification November 18, 2006 Camera-ready paper due January 31, 2007 SUBMISSION OF PAPERS All papers must be submitted electronically. Details will be posted on the web site http://www.ispd.cc. Potential authors will be required to submit full-length, original, unpublished papers (a maximum of 8 pages in ACM conference format) along with an abstract of at most 200 words and contact author information (name, street/mailing address, telephone/fax, e-mail). Previously published papers or papers submitted for publication to other conferences/journals will not be considered. Failure to disclose such relationships will result in automatic rejection. If one or more related papers have been previously submitted elsewhere for publication, the authors should clearly state the differences between these papers and the current submission. ISPD will recognize excellent contributions through Best Paper and Best Presentation Awards. SYMPOSIUM ORGANIZATION General Chair Patrick Madden (SUNY, Binghamton) [pmadden@acm.org] Past Chair Lou Scheffer (Cadence) [lou@cadence.com] Steering Committee Chair Patrick Groeneveld (Eindhoven University) [patrick@ics.ele.tue.nl] Technical Program Chair David Z. Pan (University of Texas, Austin) [dpan@ece.utexas.edu] Publications Chair Gi-Joon Nam (IBM) [gnam@us.ibm.com] Publicity Chair Prashant Saxena (Synopsys) [saxena@synopsys.com] ============================================================================== CALL FOR PAPERS - TAU 2007 --------------------------------- ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems http://www.tauworkshop.com February 26-27, 2007 Renaissance Hotel, Austin, Texas Sponsored by ACM/SIGDA and IEEE/CAS The TAU series of workshops provide an informal forum for practitioners and researchers working on temporal aspects of digital systems to disseminate early work and engage in a free discussion of ideas. The fourteenth in the TAU series, the TAU 2007 workshop invites submissions from all areas related to the timing properties of digital electronic systems, including but not limited to: Analysis and verification Custom design analysis Integrated functional-temporal analysis Timing-driven synthesis / re-synthesis Circuit-level timing Formal theories and methods Statistical analysis techniques Transistor-level timing Timing issues in low power design Delay models and metrics Adjacent line switching and coupling Incremental analysis Clocking, synchronization, and skew Process variations Asynchronous systems Sensitivity analysis Special circuit families System-level timing Novel clocking schemes Clock domains, static/dynamic logic Layout impact on timing Uncertainty-based analysis Process variation models Power-delay tradeoffs Reliability impact on performance Incorporation of RETs in timing Circuit optimization Timing-driven layout optimization IMPORTANT DATES Submission deadline November 27, 2006 Acceptance notification January 15, 2007 Camera-ready paper due February 12, 2007 SUBMISSION OF PAPERS All papers must be submitted electronically. Details will be posted on the web site http://www.tauworkshop.com. Submissions are limited to 6 pages in the double column proceedings format. TAU is a workshop aimed at fostering a high level of professional interaction, not a conference. Copies of papers will be provided to the attendees, but the proceedings will not be published by the ACM or the IEEE. Therefore, accepted papers can still be submitted to other conferences and journals. The intent of the workshop is to encourage the vigorous and unfettered discussion of the latest ideas in the field. WORKSHOP ORGANIZATION (see the web site for more details): General Chair: Michael Orshansky, University of Texas at Austin (orshansky@mail.utexas.edu) Program Chair: Noel Menezes, Intel Corporation (noel.menezes@intel.com) ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ============================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To manage your subscription, go to "Subscriber's corner" on http://listserv.acm.org/ - you need to login using the email address where this newsletter is delivered. First time users will be required to choose a password.) ==============================================================================