======================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org ======================================================================== 1 August 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 15 Online archive: http://www.sigda.org/newsletter ======================================================================== Contents of this E-NEWSLETTER: (1) Important Notice For 2006 ACM Outstanding Ph.D. Dissertation Award in EDA 2006 SIGDA Outstanding New Faculty Award Radu Marculescu Martin D.F. Wong (2) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Upcoming Funding Opportunities Qinru Qiu (6) Call For Participation HOT Chips 18: A Symposium on High-Performance Chips Alan Smith ======================================================================== Dear ACM/SIGDA members, As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; ======================================================================== Important Notice ------------------- Starting this year, the ACM Outstanding Ph.D. Dissertation Award and SIGDA Outstanding New Faculty Award will be regularly presented at the Design Automation Conference (instead of ICCAD). The new deadlines for submitting the application package are (corresponding webpages have been already updated): ***Sept. 15, 2006*** for ACM Outstanding Ph.D. Dissertation in Design Automation Award ***Nov. 1, 2006*** for SIGDA Outstanding New Faculty Award ======================================================================== SIGDA News ----------------------- "AMD to Acquire ATI" http://www.nytimes.com/2006/07/24/technology/24semi.htm AMD has agreed to buy ATI Technologies for $5.4 billion in cash and stock, entering the graphics chipsets business. The deal puts AMD on equal footing with Intel, which produces such chipsets for laptops. It could help improve AMD's overall gross profit margins and also gives it strength in the the cellphone and handheld markets. "Costello: VCs See EDA As 'Dead Space'" http://www.eetimes.com/news/design/showArticle.jhtml?articleID=191001215 Joe Costello, chairman of Orb Networks and former CEO of Cadence Design Systems Inc., came back to this year's Design Automation Conference (DAC) and said in his keynote speech Monday (July 24), "VC investors are not interested in EDA. They see it as a dead space." "Vertically Oriented Nanoelectronics" http://www.azonano.com/news.asp?newsID=2757 Engineers at Purdue University have developed a technique to grow individual carbon nanotubes vertically on top of a silicon wafer, a step toward making advanced electronics, wireless devices and sensors using nanotubes by stacking circuits and components in layers. "Second Code Found in DNA" http://www.nytimes.com/2006/07/25/science/25dna.html Unlike the genetic code that specifies all of cell's proteins, the second code, superimposed on the first, sets the placement of miniature protein spools around which the DNA is looped (nucleosomes). The spools protect and regulate access to the DNA. "Thermal Effects Not An Immediate Concern, Says TI Exec" http://www.eetimes.com/showArticle.jhtml?articleID=191200780 Contrary to popular belief, the impact of high temperature on a chip design is not among the most immediate concerns for advanced IC design, according to Robert Pitts, senior member of the technical staff and 45-nanometer platform manager at Texas Instruments Inc. Participating in a panel discussion on IC thermal issues here at the Design Automation Conference Tuesday (July 25), Pitts acknowledged that he is concerned about thermal impact at the "mid-45- and 32-nm" nodes, but that it is currently "not our No. 1 problem." Right now, "thermal is a second-order priority," Pitts said. Dynamic IR drop, he said, is chief among more immediate concerns. But thermal gradient does remain a long-term concern. "Several trends are going in the wrong direction," Pitts said. "They have been going in the wrong direction for several technology nodes." Among these trends are increasing chip power density and feature integration, Pitts said, as well as packaging options that further increase power density, such as stacked die and system-in-package modules. "Top 500 Supercomputers" http://www.top500.org/news/2006/06/28 The Summer 2006 edition of the TOP500 supercomputers list is again lead by the BlueGene/L System (IBM) installed at the DOE's Lawrence Livermore National Laboratory in Livermore, CA and commissioned for nuclear weapons simulations. It has reached a Linpack benchmark performance of 280.6 TFlop/s and is the only supercomputer on the list to exceed 100 TFlop/s. BlueGene/L topped the last 3 editions of the list, and is expected to remain in the lead for the next few editions. Even as processor frequencies seem to stall, the performance improvements of full systems is ahead of Moore's Law. There were 298 US entries, 93 entries from Asia (with Japan and China in the lead) and 83 from Europe (with UK leading Germany). IBM remains the dominant vendor of supercomputers with 49% of the list, while HP is the unchallenged second with 31%; Sun is trailing behind but supplied TSUBAME, the top entry for Asia (7th overall). Supercomputers most typically use Intel processors (301/500), IBM Power processors (84 systems) and AMD Opterons (81). "Quantum Wires and Spin Control" http://www.eetimes.com/showArticle.jhtml?articleID=191204807 At the Conf. on the Physics of Semiconductors in Vienna, Austria, researchers from Australia reported producing, for the first time, hole-based quantum wires in semiconductors. Other researchers discussed controlling spin in quantum dots, nanotube transport of holes with quantum spin, ballistic transport in quantum wires, and optical control of spin polarization. "Japan's New Petaflop Computer" http://www.newsfactor.com/story.xhtml?story_id=1220059R0ADY Japan is about to take back the world speed record for computing it held earlier in the decade. The MDGrape-3 at Riken (aka the Institute of Physical & Chemical Research) in Yokohama achieved the speed of 1 PetaFlop/s. After nearly four years in development and $9 million spent, the Riken machine is the first ever to accomplish the feat. It's nearly three times swifter than BlueGene/L, the official No. 1. However, it may not be eligible for the TOP500 supercomputer list because of its specialization to molecular dynamics and protein folding, whereas TOP500 measures performance using the LINPACK benchmark. The most impressive aspect of MDGrape-3 is its cost-efficiency --- $15 per gigaflop, compared to BlueGene/L's is $140 and the Earth Simulator's $8,000. Indeed, it uses only 4,808 chips compared 130,000 in BlueGene/L. "Variability Fingered as Next Design Pothole" http://www.eetimes.com/showArticle.jhtml?articleID=191600059 The effects of process variations loomed large at last week's Design Automation Conference here, as leading-edge chip designers spelled out the challenges they face at 65 nanometers and beyond. But many offered differing views and approaches for dealing with the problem. One quandary facing chip makers is whether to try to model everything using design-for-manufacturability (DFM) tools, or to employ restricted design rules (RDRs) that will result in more regular fabrics. Discussions last week showed that designers are hoping for a balanced approach that involves some restrictions, but leaves enough area and performance on the table so there's still some point in going to lower process nodes. Another issue that's unresolved is whether and when to use statistical timing analysis. Some designers are clearly skeptical, believing that it's effective for random variations only. In any case, there seems to be support for separating out systematic variations "EDA Players Detail Involvement in TSMC Reference Flow" http://www.reed-electronics.com/electronicnews/article/CA6354332.html Following TSMC.s announcement Monday regarding its Reference Flow 7.0 , EDA vendors are fleshing out their respective pieces and support of the world's leading foundry's recommended flow. "FPGA Users Rank Challenges, Tasks" http://www.eetimes.com/news/design/showArticle.jhtml?articleID=191600017 FPGA complexity and speed are rapidly increasing, and as a result, FPGA designers are confronting many of the same issues--and adopting some of the same tools--as their counterparts in ASIC and IC design. That's the picture that emerged from the FPGA portion of the "EE Times 2006 EDA Users Survey," which was released at last week's Design Automation Conference. "Software Environment Turbocharges IC-Logic Simulation" http://www.edn.com/index.asp?layout=article&articleid=CA6353725&spacedesc=newProducts With ICs becoming ever more complex and larger in gate counts, an ongoing demand exists for faster and higher capacity verification tools. EDA start-up Liga Systems claims it addresses that need with its new NitroSim hardware-accelerated simulation environment. The company claims that the tool improves simulation performance from 10 to 100 times over single-CPU simulation and can handle designs with as many as 300 million gates. "Harnessing Parallelism From Video-Processing DSPs" http://www.embedded.com/shared/printableArticle.jhtml?articleID=191601549 In part one of this article, we show how video applications present opportunities for multiple forms of parallelism. We then review the hardware and software approaches for exploiting these opportunities, and explain how memory systems impact performance. We also introduce the DSP architectures commonly used in video applications. "Digital Power Management: Changing The Value Ecosystem" http://www.powermanagementdesignline.com/howto/showArticle.jhtml?articleID=191600998 Here's some guidance to help you decide whether you should consider digital or analog power management in your next design. It's not as simple as you may think. "The TV Quality On Your Mobile Handsets Must Meet Or Exceed Consumer Expectations" http://www.mobilehandsetdesignline.com/showArticle.jhtml?articleID=190400003 Coming handsets will have TV capability as a checklist item. Make sure that when you design it in, it produces a high-quality experience. By Phillip Spruce, Microtune Inc. "Pure Java Platform Powers Smart Phone" http://www.elecdesign.com/Articles/ArticleID/13091/13091.html Java continues to dominate as the development platform for smart phones. Now SavaJe Technologies takes it to the extreme by delivering an exclusively Java platform. The SavaJe Mobile Platform exposes a multitasking Java virtual machine (JVM) and nothing more. There's no native operating system, nor are there any application programming interfaces (APIs). "Your Efficient Power Designs Have Tremendous Global Impact" http://www.elecdesign.com/Articles/ArticleID/13092/13092.html Summertime, and the livin' is... pricey. This issue's cover story on energy-efficiency standards seems well timed. I'm in a state of shock over the seasonal rates, pushing my monthly electric bill to more than $400. I'm thinking fondly of my years in Seattle, where the typical home doesn't even have an air conditioner. ======================================================================== Submission deadlines: --------------------- CSS'06 - Conference on Circuits, Signals and Systems San Francisco, CA Nov 20-22, 2006 Deadline: Aug 7, 2006 http://www.iasted.org/newsletter/2006/css2.htm DATE'07 - Design Automation and Test in Europe Nice, France Apr 16-20, 2007 Deadline: Sep 10, 2006 http://www.date-conference.com/ FPGA'07 -Int'l Symposium on Field-Programmable Gate Arrays Monterey, CA Feb 18-20, 2007 Deadline: Sep 15, 2006 http://conferences.ece.ubc.ca/isfpga2007/ IP-SOC'06 - IP Based SoC Design Grenoble, France Dec 6-7, 2006 Deadline: Sep 25, 2006 http://www.us.design-reuse.com/ipsoc2006/ ASYNC'07: Int'l Symposium on Asynchronous Circuits and Systems Berkeley, CA Mar 12-14, 2007 Deadline: Sep 25, 2006 http://conferences.computer.org/async2007/ ISQED'07 - Int'l Symposium & Exhibits on Quality Electronic Design San Jose, CA Mar 26-28, 2007 Deadline: Sep 30, 2006 http://www.isqed.org/ ISCAS'07 - Int'l Symposium on Circuits and Systems New Orleans, LA May 27-30, 2007 Deadline: Oct 6, 2006 http://www.iscas2007.org/ ISPD'07 - Int'l Symposium on Physical Design Austin, TX Mar 18-21, 2007 Deadline: Oct 12, 2006 http://www.ispd.cc/ SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 Deadline: Oct 23, 2006 http://www.splconf.org/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 Deadline: Dec 1, 2006 http://www.nocsymposium.org/ ======================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- EUC'06 - Int'l Conference on Embedded And Ubiquitous Computing Seoul, Korea Aug 1-4, 2006 http://euc06.euc-conference.org/ MWSCAS'06 - Int'l Midwest Symposium on Circuits and Systems San Juan, Puerto Rico Aug 6-9, 2006 http://mwscas06.ece.uprm.edu/ EC'06 - Int'l Workshop on Embedded Computing Columbus, OH August 14, 2006 http://juliet.stfx.ca/~lyang/icpp06-ec/ ASAP'06 - Int'l Conference on Application-specific Systems, Architectures and Processors Steamboat Springs, CO Sep 11-13, 2006 http://asap2006.grm.polymtl.ca/ ISOCC'06 - Int'l SoC Design Conference Seoul, Korea Oct 26-27, 2006 http://www.isocc.org/ ICCAD'06 - Int'l Conference on Computer-Aided Design San Jose, CA Nov 5-9, 2006 http://www.iccad.com/ PDCS'06 - Int'l Conference on Parallel and Distributed Computing and Systems Dallas, TX Nov 13-15, 2006 http://www.iasted.org/conferences/2006/Dallas/pdcs.htm CSS'06 - Conference on Circuits, Signals and Systems San Francisco, CA Nov 20-22, 2006 http://www.iasted.org/newsletter/2006/css2.htm IP-SOC'06 - IP Based SoC Design Grenoble, France Dec 6-7, 2006 http://www.us.design-reuse.com/ipsoc2006/ ThETA'07 - Int'l Conference on Thermal Issues in Emerging Technologies: Theory and Applications Cairo, Egypt Jan 3-6, 2007 http://www.thetaconf.org VLSI'07 - Int'l Conference on VLSI Design Bangalore, India Jan 6-10, 2007 http://www.vlsiconference.com/2007/ ASPDAC'07 - Asia and South Pacific Design Automation Conference Yokohama, Japan Jan 23-26, 2007 http://www.aspdac.com/aspdac2007/ FPGA'07 -Int'l Symposium on Field-Programmable Gate Arrays Monterey, CA Feb 18-20, 2007 http://conferences.ece.ubc.ca/isfpga2007/ SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 http://www.splconf.org/ ASYNC'07: Int'l Symposium on Asynchronous Circuits and Systems Berkeley, CA Mar 12-14, 2007 http://conferences.computer.org/async2007/ ISPD'07 - Int'l Symposium on Physical Design Austin, TX Mar 18-21, 2007 http://www.ispd.cc/ ======================================================================== Upcoming funding opportunities ------------------------------- SRC Integrated Circuit and Systems Sciences (ICSS) - Circuit Design Deadline: August 18, 2006 http://www.src.org/fr/current_calls.asp?bhcp=1 Integrated Circuit and Systems Sciences (ICSS) - Integrated Systems Design Deadline: August 18, 2006 http://www.src.org/fr/current_calls.asp?bhcp=1 DOD Experimental and Theoretical Development of Quantum Information Science Deadline: December 11, 2006 http://www.arl.army.mil/main/Main/DownloadedInternetPages/CurrentPages/DoingBusinesswithARL/research/QC06Final6Jul06.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 Optoelectronics: Components and Information Processing Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/optoelectronics.htm Software and Systems Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/software_and_systems.htm Information Fusion and Artificial Intelligence Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/information_fusion.htm Computational Mathematics Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/computational_mathematics.htm Electronics Design for Cold Environments (CRREL-66) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf Sensors, Sensor Systems, Data Acquisition, Processing, and Transmission Systems (ITL-6) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf High Performance Computing (HPC) and Networking (ITL-4) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf NSF Power, Controls and Adaptive Networks (PCAN) Deadline: September 7, 2006 - October 7, 2006 http://nsf.gov/funding/pgm_summ.jsp?pims_id=13380 Advanced Learning Technologies (ALT) (NSF 06-535) Deadline: April 25, 2007 http://www.nsf.gov/pubs/2006/nsf06535/nsf06535.htm Foundations of computing processes and Artifacts (NSF 06-585) Deadline: October 10, 2006 http://www.nsf.gov/pubs/2006/nsf06585/nsf06585.htm Instrument Development for Biological Research (IDBR) (NSF 06-570) Deadline: August 25, 2006 http://www.nsf.gov/pubs/2006/nsf06570/nsf06570.htm Operations Research (OR) Deadline: September 1, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13341&org=NSF&from=fund Information and Intelligent Systems: Advancing Human-Centered Computing, Information Integration and Informatics, and Robust Intelligence (NSF 06-572) Full Proposal Deadline(s): October 19, 2006 for Large Projects November 02, 2006 for Medium Projects December 06, 2006 for Small Projects http://www.nsf.gov/pubs/2006/nsf06572/nsf06572.htm DARPA TRUST for Integrated Circuits (BAA06-40) Original Response Date: Aug 11, 2006 http://www.darpa.mil/baa/baa06-40.html Cognitive Information Processing Technology (BAA02-21) Deadline: June 5, 2007 http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm Advanced Soldier Sensor Information System and Technology Deadline: August 04, 2006 http://fedbizopps.cos.com/cgi-bin/eps/spg/ODA/DARPA/CMO/BAA04-38/listing.html?notice=MOD NASA Applied Information Systems Research Deadline: January 30, 2007 http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId={0B64DB41-8F7D-C949-44CD-9D04A484B653}&path=open DOE Solid-State Lighting Core Technologies Deadline: June 27, 2006 https://e-center.doe.gov/iips/faopor.nsf/3b3cff0a4a1f243485256ec100490e1a/3d84c25df7cf18428525716c006d1004?OpenDocument Fellowship Sloan Research Fellowships Deadline: September 15, 2006 http://www.sloan.org/programs/scitech_fellowships.shtml ======================================================================== Call For Participation ----------------------------- HOT Chips 18 ADVANCE PROGRAM A Symposium on High-Performance Chips August 20-22, 2006, Memorial Auditorium, Stanford University, Palo Alto, California http://www.hotchips.org HOT Chips brings together designers and architects of high-performance chips, software, and systems. Presentations focus on up-to-the-minute real developments. This symposium is the primary forum for engineers and researchers to highlight their leading-edge designs. Three full days of tutorials and technical sessions will keep you on top of the industry. See http://www.hotchips.org for registration information, local arrangements, location, etc. ------------------------- Sunday, August 20, 2006 ------------------------- Morning Tutorial: Multicore Programming: From Threads to Transactional Memory Yuan Lin (Sun Microsystems) Christos Kozyrakis (Stanford) Ali-Reza Adl-Tabatabai (Intel) Bratin Saha (Intel) Afternoon Tutorial Wireless in the home - Challenges and Opportunities Jan Rabaey (UC Berkeley) ------------------------- Monday, August 21, 2006 ------------------------- Video Processing (Phillips Semiconductors) * Highly Integrated Nexperia PNX8535 Hybrid TV Processor * Heterogeneous Multiprocessing for Multi-Std HD Video Decoding * Home Entertainment-Quality on the Move: Nexperia PNX4103 Keynote I: Justin Rattner, Intel Sr. Fellow, Chief Technology Officer * Cool Codes for Hot Chips Microprocessors I * The Low-Power High-Perf. Arch. of the PWRficient Processor Family (P.A. Semi) * The Opteron CMP NorthBridge Architecture, Now and in the Future (AMD) Memory and Storage * Z-RAM Ultra-dense memory for 90nm and below (Innovative Silicon) * The Ultra Small HDD for the Mobile Applications (Toshiba) Reconfigurable Computing * Virtex5, the Next Generation 65nm FPGA (Xilinx) * RAMP: Research Accelerator for Multiple Processors UC Berkeley, CMU, Intel, MIT, UT Austin, Stanford, U. Wash.) * A Dynamically Reconfigurable HW Accelerator (Toshiba) Parallel Processing * TeraOPS: A Massively-Parallel, MIMD Computing Fabric IC (Ambric) * CA1024: Programmable SOC for HDTV Media Processing (Connex Tech.) * AsAP: An Asynchronous Array of Simple Processors (UC Davis) Panel: Who owns the living room? Moderator: Jan-Willem van de Waerdt (Philips Semiconductors) James Akiyama (Intel) Bob Brummer (Microsoft) Bill Curtis (Dell) Eugene Shteyn (Philips CE) Alan Messer (Samsung) Glen Stone (Sony) Prof. Yamada (Kyushu Institute of Technology) ------------------------- Monday, August 21, 2006 ------------------------- Embedded Processors * ARM996HS: First Licensable, Clockless 32-bit Processor Core (Handshake Solutions) * MIPS32(r) 34K(tm) Cores: Ultimate Flexibility for Embedded Apps (MIPS) * A Reusable 1GHz Super-scalar ARM Processor (ARM) * Towards Optimal Custom Instruction Processors (Imperial College) Keynote II: Bernard Meyerson, IBM Fellow; VP Strategic Alliances and Chief Technologist * Collaborative Innovation: A New Lever in Information Technology Development Novel Silicon Applications * In Silico Vox: Toward Speech Recognition in Silicon (Carnegie Mellon) * Processor Architecture for High-Performance Stream Processing (IBM Zurich) * Micro Manipulator Array for the Nano-bioelectronics Era (Toshiba) Communications * FocalPoint: A Low-Latency, High-Bandwidth Ethernet Switch (Fulcrum Micro.) * SH-MobileG1: A Single-Chip Application & Dual-Mode Baseband (Renesas) * APP300 Access Network Processor (Agere Systems) Microprocessors II * TULSA: A Dual P4 Core Large Shared Cache Intel(r) Xeon(tm) Processor (Intel) * Niagara2: A Highly-Threaded Server-on-A-Chip (Sun Micro) * Blackford: A Dual Processor Chipset for Servers & Workstations (Intel) * Inside the Core(tm) Microarchitecture (Intel) This is a preliminary program; changes may occur. For the most up-to-the-minute details on presentations and schedules, and for registration information, please visit our web site where you can also check out HOT Interconnects (another HOT Symposium being held following HOT Chips): Web: http://www.hotchips.org Email: info2006@hotchips.org Organizing Committee General Chair: Yusuf Abdulghani Apple Vice Chair: John Sell Microsoft Finance: Lily Jow HP Publicity: Donna Wilson Donna Wilson & Assoc. Gail Sachs Telairity Advertising: Don Draper Rambus Sponsorship: Amr Zaky Broadcom Publications: Gordon Garb GHI Registration: Ravi Rajamani Sun Sujata Ramasubramanian Intel Local Arrangments: Lance Hammond Apple Allen Baum Intel Charlie Neuhauser Neuhauser Assoc. Webmaster: Alexis Cordova Steering: Don Alpert Camelback Arch. Lily Jow HP John Mashey Techviser Howard Sachs Telairity Alan Jay Smith UC Berkeley At Large: Slava Mach Bob Stewart SRE Program Committee Co-Chairs: John Kubiatowicz UC Berkeley Howard Sachs Telairity Program Committee: Rajeevan Amirtharajah UC Davis Forrest Baskett NEA Bill Dally Stanford Pradeep Dubey Intel David Kirk nVIDIA Christos Kozyrakis Stanford Chuck Moore AMD Mitso Saito Toshiba Alan Jay Smith UC Berkeley Marc Tremblay Sun Micro. Jan-Willem van de Waerdt Philips Semiconductors John Wawrzynek UC Berkeley A Symposium of the Technical Committee on Microprocessors and Microcomputers of the IEEE Computer Society ======================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ======================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To manage your subscription, go to "Subscriber's corner" on http://listserv.acm.org/ - you need to login using the email address where this newsletter is delivered. First time users will be required to choose a password.) ========================================================================