======================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org ======================================================================== 15 May 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 10 Online archive: http://www.sigda.org/newsletter ======================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What is Electromigration? Contributing author: Jens Lienig Dresden University of Technology, Germany Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Upcoming Funding Opportunities Qinru Qiu ======================================================================== Dear ACM/SIGDA members, As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; ======================================================================== SIGDA News ----------------------- "EDA vendors line up to support Virtex-5" http://www.eetimes.com/showArticle.jhtml?articleID=187203331 Mentor, Magma and Synplicity have announced tool support for the new Virtex-5 FPGA from Xilinx. Synplicity particularly emphasized optimizations for the new ExpressFabric technology with the look-up table structure with six independent inputs to reduce levels of logic. A Synopsys spokesperson said that the company has no plans to support Virtex-5. Technical details of the new architecture with 12 layers of metal interconnect @65nm and significant I/O improvements are discussed at http://www.eetimes.com/showArticle.jhtml?articleID=187202400 "Dell To Sell Servers with AMD Microprocessors" http://www.eetimes.com/showArticle.jhtml?articleID=188100228 Dell Computer Corp. that previously exclusively relied on Intel processors announced that it would ship servers based on 64-bit AMD Opteron processors. AMD's CEO Hector Ruiz announced this move in an email to AMD employees with subject "Dell Makes a Smarter Choice". Dell has recently been losing market share, especially on the server market. It's competitors have increased market share by developing Opteron-based systems, according to analysts. Apparently Dell.s own sales force has been urging the company to adopt AMD.s Opteron chips in an effort to regain lost share. However, Dell plans to continue using Intel processors in a majority of their PC lines. "TSMC DFM format empowers fabless design" http://www.eetimes.com/showArticle.jhtml?articleID=187202879 TSMC this week will roll out a 65-nanometer design for manufacturability (DFM) "ecosystem" and a unified data format that will bring process model information to fabless semiconductor makers. The announcement may help close the gap between fabless designers and IDM designers, who can obtain process information from their own fabs. At a TSMC Technology Symposium the company will announce its 65-nm Compliant Design Support Ecosystem. Its centerpiece is the DFM Unified Format (DUF), which claims to provide all the information needed for lithography process checks, critical area analysis, and chemical mechanical polishing (CMP) analysis. It will be available for both 90- and 65-nm processes in July. To use the format, EDA tools must undergo a rigorous qualification that includes tests for accuracy, usability and run times. Vendors who have qualified tools include Anchor Semiconductor, Cadence Design Systems, Clear Shape Technologies, Magma Design Automation, Mentor Graphics, Ponte Solutions, Predictions Software, and Synopsys. "DFM tool targets parametric yield" http://www.eetimes.com/showArticle.jhtml?articleID=187202881 Claiming to open a new chapter in IC design-for-manufacturability, startup Blaze DFM Inc. this week will roll out Blaze MO, said to be the first "electrical" DFM solution. The company maintains that its offering improves leakage and timing by optimizing and annotating design data for the optical proximity correction (OPC) process. Blaze DFM is one of many startups in its area, but the company believes its electrical DFM approach is unique. That method, the company says, turns design requirements into manufacturing directives, and improves parametric yield through better control over leakage, timing and variability. In contrast, tools with a "geometric" focus are more concerned about issues like wire spreading, lithography simulation and critical-area analysis. "Power integrity tool takes aim at leakage" http://www.eetimes.com/showArticle.jhtml?articleID=187202896 Physical power integrity EDA provider Apache Design Solutions introduced RedHawk-LP, described as a dynamic power integrity solution for analysis and optimization of low power and leakage control designs. According to Apache, RedHawk-LP provides the most accurate and complete power solutions for designs utilizing various low power and leakage management techniques, including power-gating with full-chip ramp-up analysis and switch optimization, and multiple-Vdd/Vss cells with multiple voltage domains. Leakage power has become a huge at 90-nanometer and below, and Apache believes it has begun to dominate overall power. Engineers are employing techniques such as power-gating or multi-threshold-CMOS switches to control the amount of leakage in designs. RedHawk-LP's Spice-accurate multi-threshold-CMOS switch modeling, full-chip capacity and performance, as well as true-transient simulation engine enable designers to accurately analyze the chip's non-linear behavior during ramp-up, including how the current surge during ramp-up impacts the timing of surrounding logic, according to Apache. "Chip makers and lighting specialists get switched on to new possibilities" http://compoundsemiconductor.net/articles/magazine/12/4/9/1 The manufacturers of high-brightness LEDs and their customers in the general lighting industry now seem to be on the same wavelength, discovers Michael Hatcher. "AMD seeks desktop business with efficient chips" http://www.computerworld.com/action/article.do?command=viewArticleBasic&articleId=9000492 Advanced Micro Devices Inc. is hoping to take a bite out of Intel Corp.'s market share by selling energy-efficient versions of its desktop processors. This month, the company will release energy-efficient versions of three chip designs: the Athlon 64 X2 dual core and the Athlon 64 and Sempron single cores. "Microcontroller simplifies battery-state-of-charge measurement" http://www.edn.com/article/CA6325591.html?spacedesc=designIdeas&industryid=44217 A system that receives its power from a renewable-energy source, such as a photovoltaic panel or a wind-driven generator, typically accumulates power in a rechargeable battery and delivers it to a load. Often, both processes occur simultaneously. This article describes how to monitor battery status for renewable energy systems. "0.35 um CMOS process allows voltages from 3.3V to 120V" http://www.eetasia.com/ART_8800417940_480200_43bf6cba_no.HTM Austriamicrosystems' Full Service Foundry business unit announced its 0.35 um high-voltage CMOS technology H35 with an additional set of 120V NMOS and PMOS devices. The new extension is said to allow the integration of 3.3V, 5V, 20V, 50V and 120V devices on a single chip without any process changes. "Embedded experts: Fix code bugs or cost lives" http://www.eetasia.com/ART_8800417922_499495_4be71a05_no.HTM The Therac 25 was supposed to save lives by zapping tumors with targeted blasts of radiation. Instead, the device delivered massive overdoses that killed three patients and injured several others because of software glitches by a lone programmer whose code was never properly inspected and tested. "Startup moves binaries into FPGAs" http://www.eetasia.com/ART_8800417918_499485_57e0ae12_no.HTM Reducing embedded-system development times from months to hours sounds like a pretty good deal. And that's what startup Binachip Inc. promised when it recently unveiled plans to offer tools that convert embedded-software binary code into FPGA hardware implementations. "UC Riverside Studies New Designs for Ultra Fast Nano-Oscillators" http://www.azonano.com/news.asp?newsID=2298 Even the smallest devices, assembled at the molecular level, need motors and oscillators. UC Riverside Mechanical Engineering Professor Qing Jiang thinks bundling groups of carbon nanotubes together could make an ultra-efficient and accurate nano-oscillator. "Sun To Opensource Java" http://www.eetimes.com/showArticle.jhtml?articleID=187203700 At the annual JavaOne conference in San Francisco, Sun Microsystems Inc. announced a push for Linux on Sparc processors. The company is expected to formally announce within a week support for at least one Linux distribution on its new Niagara-based Sparc computers. It also made a commitment to opensource the Java language, but acknowledged the challenge of preserving compatibility. ""No one wants to see us destroy the Java platform," said Rich Green, Sun's executive vice president of software. "Benchmarking Quantum Control Methods on a 12-Qubit System" C. Negrevergne et al, Physical Review Letters 96,170501 (2006) A controllable 12-qubit system has been reported by a group of researchers from Waterloo, ON (Institute for Quantum Computing and Perimeter Institute for Theoretical Physics) and MIT (Department of Nuclear Engineering). This quantum information processor, the largest reported so far, is based on single molecules of l-histidine that have 14 spin-1/2 nuclei: five 1H, six 13C, and three 15N. The main effort in this work focused on designing pulse sequences to control nuclear spins. "Big Blue works out what Junk DNA does" http://www.theinquirer.net/?article=31479 BIG BLUE boffins have been using a computer technique which is designed to analyse business data to work out what all that junk does in human DNA. Ajay Royyuru, head of the Computational Biology Center at IBM Research applied pattern discovery techniques to sift through the approximately six billion letters in the non-coding regions of the human genome and look for repeating sequence fragments, or motifs. "ARM launches next-generation chip for deeply embedded systems; targets 1 billion units" http://www.siliconfenbusiness.com/index.php?articleid=138 Cambridge-headquartered chip designer ARM Holdings (ARM.L) today announced the new Cortex-R4 processor for the next generation of mobile phones, hard-disk drives, printers and automotive designs, targeting more than one billion units in the embedded market, at the Spring Processor Forum, in San Jose, California. "Guest Opinion: Will the real ESL please stand up?" http://www.edn.com/article/CA6326108.html?industryid=2813 The industry is still waiting for a truly disruptive technology to become the universally acknowledged design methodology. "IBM Sets Record in Magnetic Tape Data Density" http://www.reed-electronics.com/electronicnews/article/CA6335180.html?ref=nbednn IBM researchers claimed a world record in data density on linear magnetic tape today, packing data onto a test tape at a density of 6.67 billion bits per square inch -- more than 15 times the data density of current industry standard magnetic tape products. "Electronic Design Processes Workshop: Good engineers are worriers" http://www.edn.com/article/CA6326107.html?ref=nbsa Just an hour before the start of the 13th Electronic Design Processes Workshop -held April 13 and 14 in Monterey, CA-National Public Radio's /Morning Edition/ ran a segment by science correspondent David Kestenbaum about the ongoing repair of the New Orleans levees. The report ended with the statement, "Good engineers are worriers. That apt description applies to the Monterey workshop participants as well. Presenter after presenter described ways to solve the problems with existing EDA design flows caused by the advent of nanometer silicon and the incessant advance of Moore's Law. "FDA Asked to Better Regulate Nanotechnology" http://www.washingtonpost.com/wp-dyn/content/article/2006/05/16/AR2006051601537.html Citing research suggesting that some invisibly small engineered nanoparticles might pose health risks, a coalition of consumer and environmental groups petitioned the Food and Drug Administration yesterday to beef up its regulation of nanoparticle-containing sunscreens and cosmetics and recall some products. ======================================================================== What is Electromigration? --------------------------------- Jens Lienig Dresden University of Technology, Germany The term "electromigration" refers to the gradual displacement of metal atoms (ions) from a conductor as a result of excessive current density within this conductor. Current flow produces two forces to which the individual metal ions in the conductor are exposed. The first is an electrostatic force (F_field) caused by the electric field strength in the metallic interconnect. Since the positive metal ions are to some extent shielded by the negative electrons in the conductor, this force can be ignored in most cases. The second force (F_wind) is generated by the momentum transfer between conduction electrons (which move according to the applied electric field) and metal ions in the crystal lattice. This "wind force" works in the direction of the current flow and is the main cause of electromigration. In a homogeneous crystalline structure, because of the uniform lattice structure of the metal ions, there is hardly any momentum transfer between the conduction electrons and the metal ions. However, this symmetry does not exist at the grain boundaries and material interfaces, and so here momentum is transferred much more vigorously. Since the metal ions in these regions are bonded more weakly than in a regular crystal lattice, once the electron wind has reached a certain strength, atoms become separated from the grain boundaries and are transported in the direction of the current. This direction is also influenced by the grain boundary itself, because atoms tend to move along grain boundaries. If the current direction of an excessive current is kept constant over an extended period of time, voids (depletion of atoms) and hillocks (accumulation of atoms) appear in the wire. For this reason, analog circuits or power supply lines in digital circuits are particularly susceptible to the effects of electromigration. When the current direction varies, for example in digital circuits with their alternating capacitive charging and discharging in conductors, there is a limited amount of compensation due to a material flow back (self-healing effect). Furthermore, the susceptibility of wires to electromigration depends on grain size and thus on the distribution of grain sizes. Smaller grains encourage material transport, because there are more transport channels than in coarse-grained material. The result of this is that voids tend to show at the points of transition from coarse to fine grains, while hillocks are often generated where the structure turns from fine grains to coarse. These variations in grain size appear in interconnects at every contact hole or via which makes contacts and vias particularly susceptible to electromigration. Diffusion processes caused by electromigration can be divided into grain boundary diffusion, bulk diffusion and surface diffusion. In general, grain boundary diffusion is the major electromigration process in aluminum wires [1], whereas surface diffusion is dominant in copper interconnects [2]. It is obvious that a wider wire results in smaller current density and, hence, less likelihood of electromigration. However, if you reduce wire width to below the average grain size of the wire material, the resistance to electromigration increases, despite an increase in current density. This apparent contradiction is caused by the position of the grain boundaries, which in such narrow wires as in a bamboo structure lie perpendicular to the width of the whole wire. Because the grain boundaries in these so-called "bamboo structures" are at right angles to the current flow, the boundary diffusion factor is excluded, and material transport is correspondingly reduced. There is also a lower limit for the length of the interconnect that will allow electromigration to occur. It is known as "Blech length", and any wire that has a length below this limit (typically in the order of 10-100 microns) will not fail by electromigration [3]. Here, a mechanical stress buildup causes a reversed migration process which reduces or even compensates the effective material flow towards the anode. The Blech length must be considered when designing test structures for electromigration. At the end of the 1960s the physicist J. R. Black developed an empirical model to estimate the MTTF (mean time to failure) of a wire, taking electromigration into consideration [4]: MTTF = A (J^-n) e^(E_a / (k T)). Here A is a constant based on the cross-sectional area of the interconnect, J is the current density, E_a is the activation energy (e.g. 0.7 eV for grain boundary diffusion in aluminum), k is the Boltzmann constant, T is the temperature and n a scaling factor (usually set to 2 according to Black [4]). It is clear that current density J and (less so) the temperature T are deciding factors in the design process that affect electromigration. Due to its time delay, electromigration is very difficult to detect in its early stages. Thus, the best solution to electromigration problems is to prevent them from taking place by taking electromigration- and current-density- related parameters into account during the design process of an electronic circuit. For example, it is crucial to limit current densities in the interconnect, vias and terminal connections by keeping their cross-sectional area sufficiently large [5][6]. Various technology solutions to the electromigration problem can be applied as well, such as generating a bamboo structure, replacing aluminum with copper wires and depositing a passivation over the metal interconnect. Ongoing research in this area includes developing better passivation methods of copper wires in order to suppress surface diffusion (and so to fully exploit their much better electromigration robustness in comparison to aluminum), using nano tubes as vias (which are extremely electromigration robust) and improving IC soldering contacts to avoid electromigration-related failures of those. With regard to physical design, present research is focused on reliable current prediction methods (i.e., simulation-based current characterization) and time efficient current density verification methodologies during various layout stages. A comprehensive overview of electromigration-related aspects of physical design can be found in [7] (also available at http://www.ifte.de/mitarbeiter/lienig/ispd06_emPaper_lienig.pdf). References: [1] A. Scorzoni, C. Caprile and F. Fantini, "Electromigration in Thin-film Inter-connection Lines: Models, Methods and Results". Material Science Reports, New York: Elsevier, vol. 7, 1991, pp. 143-219. [2] Ch. S. Hau-Riege, "An Introduction to Cu Electromigration". Microel. Reliab., vol. 44, 2004, pp. 195-205. [3] I. A. Blech, "Electromigration in Thin Aluminum Films on Titanium Nitride". J. Appl. Phys., vol. 47, 1976, pp. 1203-1208. [4] J. R. Black, "Electromigration - A Brief Survey and Some Recent Results". IEEE Transactions on Electronic Devices, April 1969, pp. 338-347. [5] J. Lienig, G. Jerke, "Current-driven Wire Planning for Electromigration Avoidance in Analog Circuits". Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), 2003, pp. 783-788. [6] G. Jerke, J. Lienig, "Hierarchical Current-density Verification in Arbitrarily Shaped Metallization Patterns of Analog Circuits". IEEE Trans. on CAD, vol. 23(1), Jan. 2004, pp. 80-90. [7] J. Lienig, "Introduction to Electromigration-aware Physical Design". Proc. of the International Symposium on Physical Design (ISPD) 2006, pp. 39-46. ======================================================================== Submission deadlines: --------------------- HiPEAC'07: Int'l Conference on High Performance Embedded Architectures & Compilers Ghent, Belgium Jan 29-30, 2007 Deadline: Jun 9, 2006 http://www.hipeac.net/hipeac2007/ SMACD'06 - Int'l Workshop on Symbolic Methods and Applications to Circuit Design Florence, Italy Oct 12-13, 2006 Deadline: Jun 11, 2006 http://www.smacd06.unifi.it/ ICFPT'06 - Int'l Conference on Field-Programmable Technology Bangkok, Thailand Dec 13-15, 2006 Deadline: Jun 12, 2006 http://www.icfpt2006.org/ ISRA'06 - Int'l Symposium on Robotics and Automation San Miguel Regla, Hidalgo, Mexico Aug 25-28, 2006 Deadline: Jun 12, 2006 http://www.uaeh.edu.mx/isra2006/Html/ ProRISC'06 - Workshop on Signal Processing, Integrated Systems and Circuits Koningshof Veldhoven, Nederland Nov 23-24, 2006 Deadline: Jun 30, 2006 http://www.stw.nl/programmas/prorisc/ BIOCAS'06 - Biomedical Circuits and Systems Conference London, UK Nov 29-Dec 1, 2006 Deadline: Jul 3, 2006 http://www.ieeebiocas.org/ ISLPED'06 - Int'l Low Power Design Contest Tegernsee, Germany Oct 4 - 6, 2006 Deadline: Jul 31, 2006 http://www.islped.org/contest.html DATE'07 - Design Automation and Test in Europe Nice, France Apr 16-20, 2007 Deadline: Sep 10, 2006 http://www.date-conference.com/ IP-SOC'06 - IP Based SoC Design Grenoble, France Dec 6-7, 2006 Deadline: Sep 25, 2006 http://www.us.design-reuse.com/ipsoc2006/ NOCS'06 - IEEE International Symposium on Networks-on-Chips (NoCS) Princeton, New Jersey May 7-9, 2007 Deadline: December 1, 2006 ======================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- ISCAS'06 - Int'l Symposium on Circuits and Systems Island of Kos, Greece May 21-24, 2006 http://www.iscas06.org/ ETS'06 - European Test Symposium Southampton, UK May 21-25, 2006 http://www.ecs.soton.ac.uk/~mz/ETS06/ ICSE'06 - Int'l Conference on Software Engineering Shanghai, China May 20-28, 2006 http://www.icse-conferences.org/2006/ ICICDT'06 - Int'l Conference on Integrated Circuit Design & Technology Padova, Italy May 24-26, 2006 http://www.icicdt.org/ AHS'06 - Conference on Adaptive Hardware and Systems Istanbul, Turkey Jun 16-18, 2006 http://ehw.jpl.nasa.gov/events/ahs2006/ ISCA'06 - Int'l Symposium on Computer Architecture Boston, MA Jun 17-21, 2006 http://www.ece.neu.edu/conf/isca2006/ DAC'06 - Design Automation Conference San Francisco, CA Jul 24-28, 2006 http://www.dac.com/ DAC'06 - SIGDA Ph.D. Forum at DAC San Francisco, CA Jul 25, 2006 http://www.sigda.org/daforum/ EUC'06 - Int'l Conference on Embedded And Ubiquitous Computing Seoul, Korea Aug 1-4, 2006 http://euc06.euc-conference.org/ MWSCAS'06 - Int'l Midwest Symposium on Circuits and Systems San Juan, Puerto Rico Aug 6-9, 2006 http://mwscas06.ece.uprm.edu/ EC'06 - Int'l Workshop on Embedded Computing Columbus, OH August 14, 2006 http://juliet.stfx.ca/~lyang/icpp06-ec/ ASAP'06 - Int'l Conference on Application-specific Systems, Architectures and Processors Steamboat Springs, CO Sep 11-13, 2006 http://asap2006.grm.polymtl.ca/ ICCAD'06 - Int'l Conference on Computer-Aided Design San Jose, CA Nov 5-9, 2006 http://www.iccad.com/ ======================================================================== Upcoming funding opportunities ------------------------------- DOD Wireless Adaptable Network Node (WANN) (BAA06-26) Deadline: May 24, 2006 http://www.federal-business-daily.com/search.php?record=200604:11256 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 Optoelectronics: Components and Information Processing Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/optoelectronics.htm Software and Systems Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/software_and_systems.htm Information Fusion and Artificial Intelligence Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/information_fusion.htm Computational Mathematics Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/computational_mathematics.htm Electronics Design for Cold Environments (CRREL-66) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf Sensors, Sensor Systems, Data Acquisition, Processing, and Transmission Systems (ITL-6) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf High Performance Computing (HPC) and Networking (ITL-4) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf NSF Partnerships for Innovation (NSF 06-550) Letter of Intent Deadline Date: June 28, 2006 Full Proposal Deadline Date: August 30, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=5261&org=CISE&from=home Computing Community Consortium (CCC): Defining the Large-Scale Infrastructure Needs of the Computing Research Community - NSF 06-551 Deadline: June 10, 2006 http://www.nsf.gov/pubs/2006/nsf06551/nsf06551.htm Theoretical Foundations 2006 (TF06) - NSF 06-542 Deadline: May 25, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13679&org=CISE&from=home DARPA Advanced Soldier Sensor Information System and Technology Deadline: August 04, 2006 http://fedbizopps.cos.com/cgi-bin/eps/spg/ODA/DARPA/CMO/BAA04-38/listing.html?notice=MOD Fellowship Sloan Research Fellowships Deadline: September 15, 2006 http://www.sloan.org/programs/scitech_fellowships.shtml ======================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. 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