======================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org ======================================================================== 15 April 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 8 Online archive: http://www.sigda.org/newsletter ======================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What is Network-on-Chip? Contributing author: Avinoam Kolodny, Technion Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Upcoming Funding Opportunities Qinru Qiu ======================================================================== Dear ACM/SIGDA members, As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; ======================================================================== SIGDA News ----------------------- Quantum Computers Are Closer than You Think http://www.newscientist.com/article/mg18925441.500.html While practical quantum computers remain in the distant future, several quantum architectures hold promise to reduce adoption time and circumvent engineering problems that have plagued laboratory experiments so far. One-way computing, proposed five years ago by scientists at Germany's Ludwig Maximilian University, arranges qubits so that all entanglements needed for the calculation are established at the outset and the detrimental effects of decoherense are reduced. University of Oxford physicist David Deutsch, credited with the first quantum algorithm, has recently revised his timetable for the development of a practical quantum computer from 20 years to 10, based on progress achieved in one-way computing. IC CAD points way to brain research http://www.eetimes.com/news/design/showArticle.jhtml?articleID=185300515 What can IC physical design techniques tell us about the wiring of the brain? Plenty, according to biologist Dmitri Chklovskii, associate professor at Cold Spring Harbor Laboratory (New York). Chklovskii gave an invited talk entitled "Placement and routing optimization in the brain" at the International Symposium on Physical Design (ISPD) Tuesday (April 11). Using the concept of wiring optimization with respect to constraints and cost factors, he showed how researchers predicted the neuronal layout of the relatively simple brain of C. elegans, a small worm with 279 neurons. Langberg: Building up a `bump' in the new flat world http://www.mercurynews.com/mld/mercurynews/news/columnists/14332661.htm The San Francisco Bay Area thrives, and remains the world's leading technology center, because it has two strong research universities that often work together in building the regional economy. A. Richard Newton, engineering dean at the University of California-Berkeley, came to Silicon Valley -- usually regarded as Stanford University turf -- to deliver that message Tuesday night. Playing science's genetic lottery http://news.com.com/Playing+sciences+genetic+lottery/2009-11395_3-6058330.html In the next decade, single-celled animals might be some of the most important figures in high technology. Driving this trend is a small but growing number of start-ups and researchers that are trying to tap the power of the metabolic pathway--the complex chemical reactions inside a living organism that turn food into energy, body parts and waste products. Making Quantum Practical http://www.technologyreview.com/InfoTech-Hardware/wtr_16691,294,p1.html Researchers have succeeded in combining quantum signals with classical optical signals in a conventional fiber-optic line. FPGA/processor development board for unified design http://www.electronicsweekly.com/Articles/2006/04/11/38252/FPGAprocessordevelopmentboardforunifieddesign.htm Altium's next-generation FPGA-based development board addresses the need for unified processor/FPGA system design. Called NanoBoard-NB2 (NB2), it provides developers with a configurable and extendable hardware platform on which to implement and interactively debug designs targeted to processors and FPGAs. Analysis: Influence of outsourced design on EDA http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=185300145 Semiconductor and systems companies have traditionally been good at outsourcing areas that are not their core competencies. Among the first areas to be outsourced in the late 1970s and early 1980s were test and assembly which led to the growth of the electronic manufacturing services (EMS) industry. EDA-embedded convergence: Maybe next year.maybe sooner http://www.edn.com/article/CA6322654.html?industryid=2814 The industry continues its halting progress toward the combination of EDA and embedded-software design. EDA industry needs to take responsibility, Madhavan says http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=185300532 The EDA industry is guilty of not taking responsibility for the entire design flow and needs to provide customers with greater automation in order to see revenue growth, according to Rajeev Madhavan, chairman and CEO of Magma Design Automation Inc. Electronic design automation grew 3% in 2005 http://www.electronicsweekly.com/Articles/2006/04/07/38175/Electronicdesignautomationgrew3in2005.htm Although the chairman of the EDA Consortium says the industry continued to strengthen in Q4, revenue for the EDA market grew a modest five per cent over Q4 2004 to $1.3bn. OpenAccess adoption still limited, says panel http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=185300531 Interest in OpenAccess among chip designers remains high, though actual adoption continues to be limited, according to a panel of executives at the 8th OpenAccess+ Conference here Tuesday (April 11). The (Not So) Hidden Computer http://www.acmqueue.com/modules.php?name=Content&pa=showpage&pid=380 Ubiquitous computing may not have arrived yet, but ubiquitous computers certainly have. The sustained improvements brought by the fulfillment of Moore's law have led to the use of microprocessors in a vast array of consumer products. Is the growing complexity of purpose-built systems making it difficult to conceal the computers within? Optimizing video safety systems using model-based design http://www.eetasia.com/ARTICLES/2006MAR/C/2006MAR_SPE3.HTM Passive safety devices, such as airbags and roof reinforcement, have helped save the lives of many crash victims. Today, leading automobile manufacturers and suppliers have added active safety features that help prevent crashes and rollovers from occurring in the first place. According to the U.S. Department of Transportation, more than 18,000 deaths per year -- 40% of all automobile-related fatalities in the United States -- are caused by unintended lane departures. To address this problem, several companies and academic institutions are designing video-based active safety systems that monitor lane markings and send the driver an audio or tactile warning when the car is about to leave the road or deviate from its lane. A comparison of Network on-Chip and Busses http://www.chipdesignmag.com/display.php?articleId=371 A number of research studies have demonstrated the feasibility and advantages of Network-on-Chip (NoC) over traditional bus-based architectures. This whitepaper summarizes the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NoC, and provides specific data about Arteris' NoC, the first commercial implementation of such architectures. It Isn't Your Fathers Realtime Anymore http://www.acmqueue.com/modules.php?name=Content&pa=showpage&pid=368 Isn't it a shame the way the term realtime has become so misused? There has been a slow devolution since 1982, when realtime systems became the main focus of research, teaching, and consulting. Over these past 20-plus years, realtime become one of the most overloaded, overused, and overrated terms in the lexicon of computing. Worse, it has been purloined by users outside of the computing community and has been shamelessly exploited by marketing opportunists. Read Phillip Laplante complete article on this topic. Atmel, CEA-Leti to work on nanocrystal flash http://www.embedded.com/showArticle.jhtml?articleID=185300799 Atmel Corp. and Leti, the applied research laboratory in electronics operated by the French Atomic Energy Commission (CEA), announced Wednesday (April 12) that they have concluded a collaborative agreement on silicon nanocrystal technology for use in flash memory. The first results of the collaboration are expected to be published before the end of the year 2006. The Price of Performance http://www.acmqueue.com/modules.php?name=Content&pa=showpage&pid=330 Luiz Andr Barroso writes: In the late 1990s, our research group at DEC was one of a growing number of teams advocating the CMP (chip multiprocessor) as an alternative to highly complex single-threaded CPUs. We were designing the Piranha system which was a radical point in the CMP design space in that we used very simple cores (similar to the early RISC designs of the late 80s) to provide a higher level of thread-level parallelism. Our main goal was to achieve the best commercial workload performance for a given silicon budget. Magma tool suite promises push-button compilation http://www.eetimes.com/showArticle.jhtml?articleID=185303007 Magma Design Automation Monday claims that a new fully automated RTL-to-GDSII design suite is capable of implementing any IC, of any size, in two days or less. "This is stage one of the silicon compiler dream," said Magma CEO Rajeev Madhavan. He said Talus can take a design from concept to completion with as few as three commands. Magma's Blast Fusion, which will continue to address designs at 90 nanometers and above, as well as midlevel-complexity 65 nm, Madhavan said. Talus will target very complex chips with tens of millions of gates. Talus provides an RTL-to-completion platform that concurrently analyzes and optimizes timing, area, power, signal integrity and yield. There are two versions. Talus LX will synthesize RTL netlists and will automatically generate physical partitions and power and clock prototypes. Talus PX will provide a complete physical implementation, including near-abutment layout, final physical partitioning, power and signal routing, and chip-level clock tree synthesis. Samsung rolls 3D packaging technology http://www.eetimes.com/showArticle.jhtml?articleID=185301020 Samsung claims that it has developed a three-dimensional (3D) chip-packaging technology, based on a proprietary wafer-level stack process (WSP). Samsung's WSP technology uses "through silicon via" interconnections to enable a range of small, hybrid packages for use in handsets and other products. The company's first 3D package consists of a 16-gigabit memory solution, which stacks eight 2-Gbit NAND chips in the same unit. South Korea's Samsung (Seoul) said the technology is a much smaller version of today's multi-chip packages (MCPs). Samsung's WSP prototype sample, which vertically stacks eight 50-micrometer, 2-Gbit NAND flash die, is 0.56-mm in height. Will multi-core processing fulfil its potential? http://www.electronicsweekly.com/Articles/2006/04/17/38185/Willmulti-coreprocessingfulfilitspotential.htm Multi-core processing is the future. Everyone says so. So why is it not moving more quickly into the industry mainstream? "Von Neumann is a poor use of scaling, all the energy is going on the communication between the processor and the memory. It's much better to use 20 microprocessors running at 100MHz than one at 2GHz," says IMEC co-founder Professor Hugo De Man. "Five of the top ten supercomputers use massively parallel processing using Blue Gene," says Dr Bernie Meyerson, CTO of IBM. Although everyone accepts that multi-cores running at low speed get over the power density brick wall which was hit by single processors running at high speed, people are finding multi-core much more difficult to implement than expected. ======================================================================== What is Network-on-Chip? --------------------------------- Avinoam Kolodny, Technion Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange data encoded in packets of bits, using a network as a "public transportation" sub-system for the information traffic. An NoC is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches. An NoC is similar to a modern telecommunications network, using digital bit-packet switching over multiplexed links. The wires in the links of the NoC are shared by many signals. A high level of parallelism is achieved, because all links in the NoC can operate simultaneously on different data packets. Therefore, as the complexity of integrated systems keeps growing, an NoC provides enhanced performance and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). The adoption of NoC architecture is driven by several forces: from a physical design viewpoint, in nanometer CMOS technology, interconnects dominate both performance and dynamic power dissipation, as signal propagation in wires across the chip requires multiple clock cycles. NoC links can reduce the complexity of designing wires for predictable speed, power, noise, reliability, etc., thanks to their regular, well controlled structure. From a system design viewpoint, with the advent of multi-core processor systems, a network is a natural architectural choice. An NoC can provide separation between computation and communication, support modularity and IP reuse via standard interfaces, handle synchronization issues, serve as a platform for system test, and, hence, increase engineering productivity. Although NoCs can borrow concepts and techniques from the well-established domain of computer networking, it is impractical to blindly adopt features of "classical" computer networks and symmetric multiprocessors. In particular, NoC switches must be small, energy-efficient, and fast. The routing algorithms should be implemented by simple logic, and the number of data buffers should be minimal. Network topology and properties may be application-specific. NoCs need to support "quality of service," namely achieve the various requirements in terms of throughput, end-to-end delays and deadlines. To date, several prototype NoCs have been designed, analyzed and implemented in both industry and academia (see a recent full-day workshop on NoCs [6]). However, many challenging research problems remain to be solved at all levels, from the physical link level through the network level, and all the way up to the system architecture and application software. The first dedicated research symposium on Networks on Chip (NoC) will be held in Princeton, NJ, in May 2007. To learn more, see: 1. Jantsch, J. Oberg and H. Tenhunen (Eds.), Journal of System Architecture, special issue on networks on chip, Volume 50, Issues 2-3, Pages 61-168 (February 2004). 2. L. Benini (Ed.), Integration . the VLSI journal, special issue on networks on chip, Volume 38, Issue 1, Pages 1-130 (October 2004). 3. A. Jantsch and H. Tenhunen (Eds.), "Networks on Chip," Kluwer Academic Publishers, 2003. 4. E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, "QNoC: QoS architecture and design process for cost-effective Network on Chip," The Journal of Systems Architecture, Volume 50, pp. 105-128, February 2004. 5. E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny , "Cost considerations in Network on Chip," Integration - the VLSI journal, Vol. 38, No. 1, pp. 19-42, Oct. 2004. 6. http://async.org.uk/noc2006 ======================================================================== Submission deadlines: --------------------- DTIS'06 - Int'l Conference on Design & Test of Integrated Systems in Nanoscale Technology Tunis, Tunisia Sep 5-7, 2006 Deadline: Apr 16, 2006 (Extended) http://www.ceslab.org/conferences/DTIS2006/ TACS'06 - Workshop on Temperature Aware Computer Systems Boston, MA Jun 18, 2006 Deadline: Apr 19, 2006 (Extended) http://www.eecs.harvard.edu/~dbrooks/tacs06/ ICCAD'06 - Int'l Conference on Computer Aided Design San Jose, CA Nov 5-9, 2006 Deadline: Apr 19, 2006 http://www.iccad.com/ FC'06 - Int'l Workshop on Future Computing Technologies Las Vegas, Nevada Jun 26-29, 2006 Deadline: Apr 20, 2006 http://users.cjb.net/fut-comp/ ICCSC'06 - Int'l Conference on Circuits and Systems for Communications Bucharest, Romania Jul 6-7, 2006 Deadline: Apr 28, 2006 http://iccsc06.lce.pub.ro/ ReCoSoC'06 - Int'l Workshop on Reconfigurable Communication Centric System-on-Chips Montpellier, France Jul 3-5, 2006 Deadline: Apr 29, 2006 http://www.lirmm.fr/RECOSOC06/ HiPC'06 - Int'l Conference on High Performance Computing Bangalore, India Dec 18-21, 2006 Deadline: May 5, 2006 http://www.hipc.org/ CODES-ISSS'06 - Int'l Conference on Hardware/Software Codesign and System Synthesis EMSOFT'06 - Conference on Embedded Software CASES'06 - Int'l Conference on Compilers, Architecture and Synthesis for Embedded Systems Seoul, Korea Oct 23-27, 2006 Deadline: May 8, 2006 http://www.codes-isss.org/ HiPEAC'07: Int'l Conference on High Performance Embedded Architectures & Compilers Ghent, Belgium Jan 29-30, 2007 Deadline: Jun 9, 2006 http://www.hipeac.net/hipeac2007/ SMACD'06 - Int'l Workshop on Symbolic Methods and Applications to Circuit Design Florence, Italy Oct 12-13, 2006 Deadline: Jun 11, 2006 http://www.smacd06.unifi.it/ ICFPT'06 - Int'l Conference on Field-Programmable Technology Bangkok, Thailand Dec 13-15, 2006 Deadline: Jun 12, 2006 http://www.icfpt2006.org/ ProRISC'06 - Workshop on Signal Processing, Integrated Systems and Circuits Koningshof Veldhoven, Nederland Nov 23-24, 2006 Deadline: Jun 30, 2006 http://www.stw.nl/programmas/prorisc/ ======================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- FCCM'06 - Symposium on Field-Programmable Custom Computing Machines Napa Valley, California Apr 24-26, 2006 http://www.fccm.org/ VLSI-TSA'06 - Int'l Symposium on VLSI Tech., Sys. & Applications VLSI-DAT'06 - Int'l Symposium on VLSI Design, Automation & Test Hsinchu, Taiwan Apr 24-26, 2006 http://vlsidat.itri.org.tw/2006/General/ IPDPS'06 - Int'l Parallel and Distributed Processing Symposium Rhodes Island, Greece Apr 25-29, 2006 http://www.ipdps.org/ GLSVLSI'06 - Great Lakes Symposium on VLSI Philadelphia, PA Apr 30-May 2, 2006 http://www.glsvlsi.org/ VTS'06 - VLSI Test Symposium Berkeley, California Apr 30-May 4, 2006 http://www.tttc-vts.org/public_html/new/index.php ISCAS'06 - Int'l Symposium on Circuits and Systems Island of Kos, Greece May 21-24, 2006 http://www.iscas06.org/ ETS'06 - European Test Symposium Southampton, UK May 21-25, 2006 http://www.ecs.soton.ac.uk/~mz/ETS06/ ICSE'06 - Int'l Conference on Software Engineering Shanghai, China May 20-28, 2006 http://www.icse-conferences.org/2006/ ICICDT'06 - Int'l Conference on Integrated Circuit Design & Technology Padova, Italy May 24-26, 2006 http://www.icicdt.org/ AHS'06 - Conference on Adaptive Hardware and Systems Istanbul, Turkey Jun 16-18, 2006 http://ehw.jpl.nasa.gov/events/ahs2006/ DAC'06 - Design Automation Conference San Francisco, CA Jul 24-28, 2006 http://www.dac.com/ DAC'06 - SIGDA Ph.D. Forum at DAC San Francisco, CA Jul 25, 2006 http://www.sigda.org/daforum/ EUC'06 - Int'l Conference on Embedded And Ubiquitous Computing Seoul, Korea Aug 1-4, 2006 http://euc06.euc-conference.org/ MWSCAS'06 - Int'l Midwest Symposium on Circuits and Systems San Juan, Puerto Rico Aug 6-9, 2006 http://mwscas06.ece.uprm.edu/ EC'06 - Int'l Workshop on Embedded Computing Columbus, OH Aug 14, 2006 http://juliet.stfx.ca/~lyang/icpp06-ec/ ASAP'06 - Int'l Conference on Application-specific Systems, Architectures and Processors Steamboat Springs, CO Sep 11-13, 2006 http://asap2006.grm.polymtl.ca/ ESAS'06 - International Workshop on Engineering Semantic Agent Systems Chicago, IL Sep 18-21, 2OO6 http://conferences.computer.org/compsac/2006/ESAS.html ======================================================================== Upcoming funding opportunities ------------------------------- DOD Wireless Adaptable Network Node (WANN) (BAA06-26) Deadline: May 24, 2006 http://www.federal-business-daily.com/search.php?record=200604:11256 High Performance computing for modeling and simulation Broad Agency Announcement (BAA) - W911NF-04-R-0005 Deadline: April 27, 2006 (white paper) http://www.arl.army.mil/main/main/default.cfm?Action=6&Page=8 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 Optoelectronics: Components and Information Processing Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/optoelectronics.htm Software and Systems Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/software_and_systems.htm Information Fusion and Artificial Intelligence Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/information_fusion.htm Computational Mathematics Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/computational_mathematics.htm Electronics Design for Cold Environments (CRREL-66) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf Sensors, Sensor Systems, Data Acquisition, Processing, and Transmission Systems (ITL-6) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf High Performance Computing (HPC) and Networking (ITL-4) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf NSF Computing Community Consortium (CCC): Defining the Large-Scale Infrastructure Needs of the Computing Research Community - NSF 06-551 Deadline: June 10, 2006 http://www.nsf.gov/pubs/2006/nsf06551/nsf06551.htm Theoretical Foundations 2006 (TF06) . NSF 06-542 Deadline: May 25, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13679&org=CISE&from=home Information and Intelligent Systems: Advancing Collaborative and Intelligent Systems and their Societal Implications - NSF 05-551 Deadline: April 18, 2006; April 20, 2006 http://www.nsf.gov/publications/pub_summ.jsp?ods_key=nsf05551 DARPA Advanced Soldier Sensor Information System and Technology Deadline: August 04, 2006 http://fedbizopps.cos.com/cgi-bin/eps/spg/ODA/DARPA/CMO/BAA04-38/listing.html?notice=MOD Fellowship Sloan Research Fellowships Deadline: September 15, 2006 http://www.sloan.org/programs/scitech_fellowships.shtml ======================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To manage your subscription, go to "Subscriber's corner" on http://listserv.acm.org/ - you need to login using the email address where this newsletter is delivered. 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