======================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org ======================================================================== 1 March 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 5 Online archive: http://www.sigda.org/newsletter ======================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) "What is Embedded System Design in an FPGA?" Contributing author: Stephen Brown Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Upcoming Funding Opportunities Qinru Qiu (6) Call for Papers: The 2006 IEEE International Conference on Field-Programmable Technology (ICFPT 06) Theerayod Wiangtong (7) Call for Papers: 2nd IEEE International Workshop on Defect and Fault Tolerant Nanoscale Architectures (NANOARCH'2006) Steve Levitan Jie Chen ======================================================================== Dear ACM/SIGDA members, As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; ======================================================================== SIGDA News ----------------------- "IBM claims 193-nm litho record" http://www.eetimes.com/showArticle.jhtml?articleID=180204799 IBM Corp. announced achieving the world's smallest line patterns using a 193nm immersion scanner from ASML Holding NV, a new optical lithography apparatus and new materials. IBM claims to have made distinct and uniformly spaced ridges only 29.9-nm wide. This is below the 32-nm level that were commonly considered the limit for optical lithography techniques and three times better than currently common 90nm features. In IBM's NEMO experiments, the lens and fluid had refractive indices of about 1.6, and the photoresist's index was 1.7. Future research is aimed at developing lens, fluid and photoresist materials with indices of refraction of 1.9, which would enable even smaller features to be imaged. "Intel delays EUV lithography" http://www.eetimes.com/showArticle.jhtml?articleID=180204862 Intel Corp. has apparently rescheduled its efforts to bring extreme ultraviolet (EUV) lithography into high-volume production for the 32-nm node by 2009, citing the lack of necessary materials and tools from companies like ASML, Nikon and Canon. Yan Borodovsky, Intel senior fellow and director of advanced lithography in its Technology and Manufacturing Group discussed Intel's plans for EUV lithography at the SPIE Microlithography conference. He pointed out that at Intel, EUV, along with various 193-nm techniques, are possible options for chip production at the 22-nm node in 2011. However, for 32-nm high-volume production, the company is attempting to extend 193-nm wavelength lithography, including the use of dry, immersion and double-exposure techniques, Indeed, EUV still faces a plethora of technical challenges despite billions of dollars of R&D being poured into the technology. At present, there are no adequate power sources for EUV. The shelve life of a condenser for an EUV tool is about a month now. Many had hoped to see shelf lives of four years. And there is no way to inspect the masks, which are supposed to be defect free. "Panel mulls do-it-yourself EDA" http://www.eetimes.com/showArticle.jhtml?articleID=181400453 The recent data shows that there seems to be an increasing trend toward internal CAD tool development. According to Gartner Dataquest figures, 27 percent of chip designers were using in-house tools last year, an increase over previous years. There are "power users" who have always used in-house tools, but they constitute about 10 percent of the total design population. It thus seems that in-house development is moving to the mainstream. At a "build or buy" panel discussion at the recent DesignCon, vendor representatives predictably raised a number of arguments against in-house tool development. If you write your own tools, they said, it takes a lot of time, you'll have bugs and it probably isn't your area of expertise. It may be a more-difficult and expensive proposition than you envision. "EDA Software Sold in Walmart" http://www.reed-electronics.com/electronicnews/article/CA6308640.html?industryid=21365 To increase the overall awareness of EDA.s importance in development of electronics, Henderson, Nevada-based mixed-language simulator and design tool supplier for ASIC and FPGA devices Aldec Inc. said today that its Active-HDL Student Edition is now being sold in Walmart.s online store as well as in Barnes & Noble book stores. "EDA firms face off at conference" http://www.electronicsweekly.com/Articles/2006/02/27/37822/EDAfirmsfaceoffatconference.htm EDA executives were taken to task and sparks flew at a panel meeting at the Design and Verification Conference. Topics ranged from lawsuits to rumours of corporate demise to the old battles over System Verilog versus SystemC. .We didn.t start [the lawsuit with Synopsys],. said Magma.s CEO Rajeev Madhavan, when asked whether he regretted the lawsuit. .We sent a letter and they responded to it with litigation.. "Summit Design's Vista(TM) IDE Simplifies Intellectual Property Development and Design Sharing For SystemC-Based Designs Without A Run-Time License" http://sanjose.dbusinessnews.com/shownews.php?newsid=64089&type_news=latest Summit Design, Inc., a leading provider of electronic system-level (ESL) and hardware description language (HDL) design solutions, announced today that Vista(TM) IDE for SystemC can now easily create and compile executables of SystemC designs based on the OSCI simulation kernel. Such designs can be created and debugged with Vista, but do not depend on the features of Vista once compiled. These compiled designs can be freely distributed without requiring a Vista license or distribution agreement. With Vista, intellectual property (IP) distribution and design sharing is simplified. The IP is shipped with the requisite testbenches and executable specifications in a format that requires only the open-source OSCI SystemC kernel for execution. "Engineer readies tool that generates logic specs" http://www.eetasia.com/ART_8800405535_499485_8fc956ef_no.HTM After working in labs designing fault-tolerant flight-control systems, Dave McFarland came to realize that there's no good way to specify logic and look at all the possible combinations. So he built a tool to handle the job. A graphical aid for developing digital control, McFarland's Logic Design Tool (LDT) generates a complete specification for combinatorial and sequential logic, letting users specify all transitions for all states and all input combinations. It can then provide multiple views of the logic, identify dead or hanging states, search for best- and worst-case performance paths, and generate source files in C, Pascal, Ada, VHDL or Espresso. "Military Nanotech Spending Proves Difficult to Tap" http://www.nanotech-now.com/news.cgi?story_id=13969 With threats to the U.S. increasingly coming from terrorist organizations, rogue nations, and insurgencies, the military is driving a major effort to improve its capabilities . making it one of the best prospective buyers for applications of nanotechnology. But companies large and small that supply these nanotech solutions are failing to exploit the military market effectively because of mismatched development strategies, according to a new report from Lux Research entitled .Setting Supplier Strategies for Military Nanotech Applications.. "Preparing for a Quantum Leap in Computing" http://www.physorg.com/news11287.html Imagine a place where anything possible always happens, like a TV screen that displays all the channels at once. If that seems beyond imagination, you are not alone. The world of quantum physics is so weird that even the scientists who study it say it challenges everyday concepts of common sense. "Designs on common platform" http://www.fabtech.org/index.php?option=content&task=view&id=1294&Itemid=2 New intellectual property (IP) design support is to be developed for the 65nm common process platform of IBM, Chartered Semiconductor Manufacturing and Samsung. ARM is collaborating with the three companies to offer the ARM Advantage Artisan physical intellectual property (IP) on the 65nm generic Common Platform process, enable multi-sourcing strategies. In addition, Cadence Design Systems announced immediate availability of a 90nm reference flow that addresses power-management and design-yield issues as part of an ongoing collaboration with IBM and Chartered. "Electronic system-level design tools come up short" http://www.eetasia.com/ARTICLES/2006FEB/C/2006FEB_ART_WK4.HTM If electronic system-level and design-for-manufacturing tools represent the EDA industry's best opportunities for growth, they need to pack far more capabilities than they do today, users and vendors said at the recent 2006 DesignCon conference. Otherwise, some warned, chip designers will develop their own tools. "I started writing place-and-route tools when I was in an internal CAD group," said one of the more outspoken users, Richard Tobias, CTO and VP of engineering at Pixelworks. "Now I'm CTO of a fabless semiconductor company, and I absolutely don't want to build tools in-house but I have to." "Magma Announces Availability of Integrated Advanced Low-Power Reference Flow for IBM-Chartered 90-Nanometer Common Platform" http://home.businesswire.com/portal/site/google/index.jsp?ndmViewId=news_view&newsId=20060227005366&newsLang=en Magma(R) Design Automation Inc. (Nasdaq:LAVA), a provider of semiconductor design software, today announced the availability of an advanced low-power IC implementation reference flow for the 90-nanometer low-power process offered through the IBM-Chartered Semiconductor Manufacturing Common Platform. The Magma flow, featuring Blast Power(TM), Blast Fusion(R), Blast Create(TM) and Blast Rail(TM) NX, addresses the three major concerns of power management: dynamic power, leakage power and power distribution. It has been qualified using real-world designs and libraries. "Panelists: ESL is promising but still needs work" http://www.edn.com/article/CA6305884.html?spacedesc=newProducts IC architects are using ESL (electronic-system-level) design methodologies to derive SOC (system-on-chip) architectures. But ESL tools, specifically for SystemC, still have a long way to go before system designers, let alone software and hardware engineers, will adopt them. "Biology inspires perceptive machines" http://istresults.cordis.lu/index.cfm/section/news/tpl/article/ID/80430/BrowsingType/Features Teaching a machine to sense its environment is one of the most intractable problems of computer science, but one European project is looking to nature for help in cracking the conundrum. It combined streams of sensory data to produce an adaptive, composite impression of surroundings in near real-time. ======================================================================== What is Embedded System Design in an FPGA? --------------------------------------------- Prof. Stephen Brown, University of Toronto A typical digital system design involves a significant amount of custom logic circuitry, but also includes some pre-designed major components, such as processors, memory units, and various types of input/output interfaces. In a traditional approach for designing such systems, a new integrated circuit chip is created for the custom logic circuits, but each pre-designed component is included as a separate chip. This column discusses a different approach for realizing digital systems, called embedded system design. It leverages the advanced capabilities of today's integrated circuit technology by implementing many of the components of the system within a single chip, such as a field programmable gate array (FPGA). FPGAs are a good choice for implementing digital systems because they: * offer large logic capacity, exceeding several million equivalent logic gates, and include dedicated memory resources * include special hardware circuitry that is often needed in digital systems, such as digital signal processing (multiply and accumulate) blocks, and PLLs (or DLLs) that support complex clocking schemes * support a wide range of interconnection standards, such as DDR memory, PCI, and high-speed serial protocols. In addition to the above features, FPGAs provide the significant benefit of being "off-the-shelf" chips that are programmed by the end user. This user-programmability avoids the need for long manufacturing times and high non-recurring engineering (NRE) costs that would be required if a custom integrated circuit were manufactured. Also, the FPGA can be re-programmed as many times as needed to make changes or fix errors. In embedded system design there is a lot of flexibility for deciding which parts of the system should be embedded in the FPGA and which parts should remain as separate chips. Possibly the most compelling choice is to integrate most of the system into the FPGA chip, including the processor and its peripherals (like bus interfaces and parallel/serial ports) and some of the memory, such as processor cache memory. Two types of processors are available for use in FPGA devices: hard and soft. A hard processor is a pre-designed circuit that is fabricated somewhere within the FPGA chip. A more flexible alternative is to use a soft processor. In this case the processor exists as code written in a hardware description language, and it is implemented along with the rest of the system by using the logic and memory resources in the FPGA fabric. An advantage of this approach is that resources on the FPGA are consumed for processors only when these components are actually needed in the system. It is also possible to include multiple soft processors in the FPGA when desired. Regardless of the specific set of components used in the system, there exist powerful tools to help with its design, as described below. Embedded System Design Software Tools There are two main aspects to the software tools for embedded system design: 1) the creation of the system hardware and 2) the development of software that runs on the processors included in the system. FPGA manufacturers provide automated tools to facilitate both parts of this design flow. For creating the hardware circuitry, the tools allow the user to build their system by making use of pre-designed building blocks for processors, memory controllers, digital signal processing circuits, and various communication modules (for example, UARTs). The software allows easy instantiation of these sub-circuits and can automatically interconnect them on the FPGA chip. Design of these components is seamlessly integrated into the tool set that is used to create the custom logic circuits which are also implemented in the FPGA. The CAD tools generate memory maps for the system, which allow the processor(s) to access the system's hardware resources. Application software development is supported with the typical toolsets that are expected by software programmers, including compilers, debuggers, and operating system support. Open Research Issues One example of an interesting area for future research in embedded system design is in the use of soft processors on FPGAs to create multiprocessor systems. Research is needed to determine how soft processors should be interconnected on an FPGA such that fast program execution can be obtained, and how a memory hierarchy can be designed in such a system to enable efficient sharing of data. A more advanced topic is the study of FPGA architecture features that best support multiprocessing with soft processors without sacrificing chip area or speed performance for other types of applications. To learn more, see 1. J.O. Hamblen, T.S. Hall, and M.D. Furman, "Rapid Prototyping of Digital Systems", Springer 2005 ISBN 0-387-27728-5. 2. Altera Corporation, "The Quartus II Development Handbook", http://www.altera.com 3. Altera Corporation, "Nios II Processor Reference Handbook", http://www.altera.com 4. Altera Corporation, "Nios II Software Developer's Handbook," http://www.altera.com 5. Xilinx Corporation, "Xilinx ISE Software Manuals and Help", http://www.xilinx.com 6. Xilinx Corporation, "Embedded Development Kit (EDK) User Guides," http://www.xilinx.com 7. Bob Garrett, "Multi-Processor Solutions with FPGAs", http://www.fpgajournal.com ======================================================================== Submission deadlines: --------------------- ISLPED'06 - Int'l Symposium on Low Power Electronics and Design Tegernsee (Munich area), Germany Oct 4-6, 2006 Deadline: Mar 3, 2006 http://www.islped.org/ EC'06 - Int'l Workshop on Embedded Computing Columbus, OH Aug 14, 2006 Deadline: Mar 06, 2006 http://juliet.stfx.ca/~lyang/icpp06-ec/ FPL'06 - Int'l Conference on Field Programmable Logic and Applications Madrid, Spain Aug 28-30, 2006 Deadline: Mar 10, 2006 http://fpl.org/ MWSCAS'06 - Int'l Midwest Symposium on Circuits and Systems San Juan, Puerto Rico Aug 6-9, 2006 Deadline: Mar 12, 2006 http://mwscas06.ece.uprm.edu/ ASAP'06 - Int'l Conference on Application-specific Systems, Architectures and Processors Steamboat Springs, CO Sep 11-13, 2006 Deadline : March 20, 2006 http://asap2006.grm.polymtl.ca/ PACT'06 - Int'l Conference on Parallel Architectures and Compilation Techniques Seattle, WA Sep 16-20, 2006 Deadline: Mar 27, 2006 http://www.pactconf.org VLSI-SoC'06 - Int'l Conference on Very Large Scale Integration French Riviera, France October 16-18, 2006 Deadline: Mar 27, 2006 http://tima.imag.fr/conferences/VLSI-SoC06/ SBCCI'06 - Symposium on Integrated Circuits and Systems Design Ouro Preto, Minas Gerais, Brazil Aug 28-Sep 1, 2006 Deadline: Apr 2, 2006 http://www.sbc.org.br/sbcci FDL'06 - Forum on specification & Design Languages TU Darmstadt, Germany September 19-22, 2006 Deadline: Apr 3, 2006 http://www.ecsi-association.org/ecsi/fdl/fdl05/default.htm ICCAD'06 - Int'l Conference on Computer Aided Design San Jose, CA November 5-9, 2006 Deadline: Apr 19, 2006 http://www.iccad.com/ CODES-ISSS'06 - Int'l Conference on Hardware/Software Codesign and System Synthesis Seoul, Korea October 22-25, 2006 Deadline: May 8, 2006 http://www.codes-isss.org/ ICFPT'06 - Int'l Conference on Field-Programmable Technology Bangkok, Thailand Dec 13-15, 2006 Deadline: Jun 12, 2006 http://www.icfpt2006.org/ ======================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- SLIP'06 - System Level Interconnect Prediction Munich, Germany Mar 4-5, 2006 http://www.sliponline.org DATE'06 - Design Automation and Test in Europe Munich, Germany Mar 6-10, 2006 http://www.date-conference.com/ ISQED'06 - Int'l Symposium on Quality Electronic Design San Jose, CA Mar 27-29, 2006 http://www.isqed.org/ SASIMI'06 - Workshop on Synthesis and System Integration of Mixed Information Technology Nagoya, Japan Apr 3-4, 2006 http://www.sasimi.jp/ ISPD'06 - Int'l Symposium on Physical Design San Jose, CA Apr 9-12, 2006 http://www.ispd.cc/ VLSI-TSA'06 - Int'l Symposium on VLSI Tech., Sys. & Applications VLSI-DAT'06 - Int'l Symposium on VLSI Design, Automation & Test Hsinchu, Taiwan Apr 24-26, 2006 http://vlsidat.itri.org.tw/2006/General/ IPDPS'06 - Int'l Parallel and Distributed Processing Symposium Rhodes Island, Greece Apr 25-29, 2006 http://www.ipdps.org/ GLSVLSI'06 - Great Lakes Symposium on VLSI Philadelphia, PA Apr 30-May 2, 2006 http://www.glsvlsi.org/ ISCAS'06 - Int'l Symposium on Circuits and Systems Island of Kos, Greece May 21-24, 2006 http://www.iscas06.org/ ETS'06 - European Test Symposium Southampton, UK May 21-25, 2006 http://www.ecs.soton.ac.uk/~mz/ETS06/ ICSE'06 - Int'l Conference on Software Engineering Shanghai, China May 20-28, 2006 http://www.icse-conferences.org/2006/ DAC'06 - SIGDA Ph.D. Forum at DAC San Francisco, CA Jul 25, 2006 http://www.sigda.org/daforum/ DAC'06 - Design Automation Conference San Francisco, CA Jul 24-28, 2006 http://www.dac.com/ ASAP'06 - Int'l Conference on Application-specific Systems, Architectures and Processors Steamboat Springs, CO Sep 11-13, 2006 http://asap2006.grm.polymtl.ca/ ======================================================================== Upcoming funding opportunities ------------------------------- DOD Optoelectronics: Components and Information Processing Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/optoelectronics.htm Software and Systems Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/software_and_systems.htm Information Fusion and Artificial Intelligence Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/information_fusion.htm Computational Mathematics Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/computational_mathematics.htm Electronics Design for Cold Environments (CRREL-66) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf Sensors, Sensor Systems, Data Acquisition, Processing, and Transmission Systems (ITL-6) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf High Performance Computing (HPC) and Networking (ITL-4) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf NSF Theoretical Foundations 2006 (TF06) Deadline: May 25, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13679&org=CISE&from=home Integrative Graduate Education and Research Traineeship Program . NSF 06-525 Deadline: March 27, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=12759&org=CISE&from=home Cyber Trust . NSF 05-518 Deadline: March 6, 2006 http://www.nsf.gov/pubs/2006/nsf06517/nsf06517.htm Information and Intelligent Systems: Advancing Collaborative and Intelligent Systems and their Societal Implications - NSF 05-551 Deadline: April 18, 2006; April 20, 2006 http://www.nsf.gov/publications/pub_summ.jsp?ods_key=nsf05551 DARPA Spoken Language Communication and Translation System for Tactical Use (TRANSTAC) Deadline: March 24, 2006 (Initial Closing) http://www.darpa.mil/ipto/solicitations/open/06-21_PIP.htm Advanced Soldier Sensor Information System and Technology Deadline: August 04, 2006 http://fedbizopps.cos.com/cgi-bin/eps/spg/ODA/DARPA/CMO/BAA04-38/listing.html?notice=MOD NAVSEA Science and Technology BAA - Countermeasures Technology Deadline: Open until March 21, 2006 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Science and Technology BAA . Audition and Communication Deadline: Open until March 21, 2006 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Science and Technology BAA . Test and Evaluation Deadline: Open until March 21, 2006 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Fellowship NASA Summer Faculty Research Opportunities (NSFRO) Deadline: March 14, 2006; May 02, 2006 http://www.asee.org/resources/fellowships/nsfro/general.cfm Sloan Research Fellowships Deadline: September 15, 2006 http://www.sloan.org/programs/scitech_fellowships.shtml ======================================================================== Call for Papers ----------------------- The 2006 IEEE International Conference on Field-Programmable Technology (ICFPT 06) ----------------------------------------- www.icfpt2006.org Fortune Hotel, Bangkok, Thailand December 13 - 15, 2006 Organized by the Mahanakorn University of Technology, Bangkok, Thailand Technical co-sponsorship by IEEE Circuit and Systems Society, Thailand Chapter ------------------------------------------------- CALL FOR PAPERS ================== ICFPT is a fast growing conference on field-programmable technologies, including complex programmable logic devices and systems containing such components. The development of, and the applications of, field-programmable technology have become an important topic of research for universities, government, and industry worldwide. Field-programmable devices combine the flexibility of software with the performance of hardware. Their regular structure facilitates rapid improvement in density, capability and speed. Field-programmable systems have a wide variety of applications, such as accelerating computations in molecular biology and medical imaging, low-power control and data processing for palm-size computers, and emulating novel electronic products before manufacture; even advanced microprocessors from Intel and ARM have benefited from field-programmable hardware emulators. Submissions are solicited on a wide variety of topics related to field-programmable technologies, including but not limited to: * Applications of field-programmable technology: biomedical and scientific computation accelerators, network processors, real-time systems, rapid prototyping, hardware emulation, digital signal processing, interactive multimedia, machine vision, computer graphics, cryptography, robotics, manufacturing systems, embedded applications, evolvable and biologically-inspired hardware. * Design techniques and tools for field-programmable technology: placement, routing, synthesis, verification, technology mapping, partitioning, parallelization, timing optimization, design and run-time environments, languages and modeling techniques, provably-correct development, intellectual property core based design, domain-specific development, hardware/software co-design. * Architectures for field-programmable technology: field programmable gate arrays, complex programmable logic devices, field programmable interconnect, field programmable analogue arrays, field programmable arithmetic arrays, memory architectures, interface technologies, low-power techniques, adaptive devices, reconfigurable computing systems, other emerging technologies. * Device technology for field-programmable logic: programmable memories including non-volatile, dynamic and static memory cells and arrays, interconnect devices, circuits and switches, emerging VLSI device technologies. * Novel use of reconfigurability, including evolvable hardware and adaptive computing, possible forms and system implications of reconfiguration for fault tolerance and avoidance, implications and effects of nanotechnology and reconfigurable computing and others. Important Dates: ================ Submission of papers: June 12 2006 Notification of acceptance: July 31 2006 Registration deadline: September 4 2006 Conference start: December 13 2006 Submission Guidelines ===================== The program committee solicits papers describing original research in field-programmable technology, including, but not limited to, the areas of interest indicated above. Papers should be submitted electronically in PDF format, following the IEEE style. Full papers should not exceed 8 pages in length, while posters should not exceed 4 pages in length. Manuscripts must not identify authors or their affiliations. Papers that identify authors will NOT be considered. Submissions must be made via the conference webs. The paper submission site for the conference is: http://www.icfpt2006.org/submit.htm Proposals for half and full day tutorials in the areas of interest are also sought. Initial inquiries should be directed to icfpt@icfpt2006.org. Questions regarding the FPT conference, including the submission procedure and grants, can be sent to: icfpt@icfpt2006.org Programme Committee: ==================== Alex Yakovlev (University of Newcastle, UK) Andre DeHon (Caltech, USA) Andy Ye (Ryerson University, Canada) Apostolos Dollas (Technical University of Crete, Greece) Christos-Savvas Bouganis (Imperial College, UK) David Kearney (University of South Australia, Australia) David Wu (Chinese University of Hong Kong) Dinesh Bhatia (University of Texas Dallas, USA) Eduardo Boemo (University of Madrid, Spain) Florent De Dinechin (ENS-Lyon, France) George Constantinides (Imperial College, UK) Gordon Brebner (Xilinx) Guy Lemieux (University of British Columbia, Canada) Henry Styles (Xilinx) Jim Hwang (Xilinx) Jinian Bian (Tsinghua University, China) Joao Cardoso (University of Algarve, Portugal) Jonathan Rose (Toronto University, Canada) Juanjo Noguera (Xilinx) Jürgen Teich (University of Erlangen-Nuernberg, Germany) Kara Poon (Actel) Katherine Compton (University of Wisconsin-Madison, USA) Kia Bazargan (University of Minnesota) Kobchai Dejhan (KMITL, Thailand) Koji Kotani (University of Tohoku, Japan) Laurence Turner (University of Calgary, Canada) Makoto Ikeda (University of Tokyo, Japan) Manfred Glesner (TU Darmstadt, Germany) Marco Platzner (University of Paderborn, Germany) Mark Shand (Hewlett Packard) Masahiro Fujita (University of Tokyo, Japan) Mike Hutton (Altera) Neil Bergmann (University of Queensland, Australia) Nikil Dutt (University of California Irvine, USA) Oliver Diessel (University of New South Wales, Australia) Oskar Mencer (Imperial College London, UK) Patrick Lysaght (Xilinx) Paul Beckett (RMIT University, Australia) Pedro Diniz (Information Sciences Institute, USA) Peter Cheung (Imperial College, UK) Phil James-Roxby (Xilinx) Philip Leong (Imperial College, UK) Ranga Vemuri (University of Cincinnati, USA) Ranjani Parthasarathy (Anna University, India) Roger Woods (Queen's University Belfast, UK) Russ Tessier (University of Massachusetts Amherst, USA) Sakir Sezer (Queen's University Belfast, UK) Satnam Singh (Microsoft) Satoshi Komatsu (University of Tokyo, Japan) Steve Wilton (University of British Columbia, Canada) Steven Quigley (University of Birmingham, UK) Tarek El-Ghazawi (George Washington University, USA) Tetsuo Hironaka (University of Hiroshima, Japan) Ting-Chi Wang (Tsing Hua University, Taiwan) Tom Kean (Algotronix) Tulika Mitra (NUS, Singapore) Vaughn Betz (Altera) Wai-Kei Mak (Tsing Hua University, Taiwan) Wanchalerm Pora (Chulalongkorn University, Thailand) Wayne Luk (Imperial College London, UK) Weng Fai Wong (NUS, Singapore) Yao-Wen Chang (National Taiwan University, Taiwan) Organizing Committee: ===================== General Chair: Sujate Jantarang (MUT) Vice Chair: Phaophak Sirisuk (MUT) Technical Program Co-Chairs: George Constantinides (Imperial College) Wai-Kei Mak (Tsing Hua University, Taiwan) Publications Chair: Nalin Sidahao (MUT) Exhibition Co-Chair: Jitkasame Ngarmnil (MUT) Apinunt Thanachayanont (KMITL) Publicity Co-Chair: Surin Kittitorakul (KMITL) Pinit Kumhom (KMUTT) Nattha Jindapetch (PSU) Local Arrangement Co-Chair: Peerapol Yuvapoositanon (MUT) Supakorn Siddichai (NECTEC) Review Process Administrator: Altaf Abdul Gaffar (Imperial College) Finance Chair and General Secretariat: Theerayod Wiangtong (MUT) ======================================================================== Call For Papers ---------------- 2nd IEEE International Workshop on Defect and Fault Tolerant Nanoscale Architectures (NANOARCH'2006) http://www.nanoarch.org June 17, 2006 Boston Park Plaza Hotel, Boston, MA, USA * Several NSF supported travel grants will be available for students participating in NANOARCH 2006. Current defect tolerance, fault-tolerance and manufacturing test techniques are designed under the assumption that a system under test is composed largely of correctly functioning units. However, this assumption is severely tested in emerging nanoelectronics such as molecular electronics, quantum electronics, single electron transistors and carbon nanotubes and nanowires. In these nanoelectronics, self-assembly based fabrication results in failures rates an order of magnitude higher than in traditional CMOS. Consequently, defect and fault tolerance - at the physical, circuit and most importantly at the system level- is an enabling technology for building reliable nanoelectronic systems. NANOARCH will investigate novel defect and fault tolerance architectures targeting these highly unreliable nanoelectronics. The workshop will be a forum for presenting theoretical, simulation and case studies on new defect models, defect and fault tolerance architectures, associated experimental reliability evaluation and validation frameworks and computer aided simulation and design tools for these emerging nanoelectronics. Topics of interest include but are not limited to: .Defect tolerant nanoelectronic architectures at device, circuit, and system level .Fault tolerant nanoelectronic architectures at the device, circuit, and system level .Emerging computational paradigms for nanoelectronics .Modeling and simulation of novel nanoelectronic architectures and concepts .Implementing micro-architectural concepts using nanoarchitectural building blocks .Dynamic reconfiguration in nanoelectronic architectures .Defect and fault models in emerging nanoelectronic device technologies .Manufacture testing methodologies for nanoelectronic architectures .Yield models, yield analysis and yield enhancement in nanoelectronics .CAD targeting defect and fault-tolerant nanoelectronic architectures The Program Committee invites authors to submit papers up to 8 pages in length, describing original, unpublished recent work. Clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status. Electronic submission through the workshop website is required. The submission of a paper proposal will be considered evidence that upon acceptance, the author(s) will present their paper at the workshop. Final versions of accepted papers will be included in the NANOARCH Workshop Digest Important deadlines: (please submit to the workshop website http://www.nanoarch.org) Abstracts: March 20, 2006 Paper: March 27, 2006 Acceptance notification: May 1, 2006 Final version of papers: June 1, 2006 GENERAL CHAIR R. Karri, Polytechnic U PROGRAM CHAIR A. Orailoglu, UC San Diego SPECIAL ISSUE CO-CHAIRS M. Stan, U Virginia, and K. Likharev, Stony Brook SPECIAL SESSIONS CHAIR D. Hammerstrom, Portland State PUBLICITY CO-CHAIRS S. Levitan, U. Pittsburgh, and J. Chen, National Institute of Nanotechnology & U Alberta INDUSTRY LIAISON W. Joyner, SRC NANO TC LIAISON R. Kapur, Synopsys ASIAN LIAISON K. Kim, Incheon PUBLICATIONS CHAIR D. Sorin, Duke E-MEDIA CHAIR I. Bayraktaroglu, Sun PROGRAM COMMITTEE Iris Bahar, Brown U Valeriu Beiu, Washington State U Shamik. Das, MITRE Andre DeHon, Caltech Chris Dwyer, Duke U James Ellenbogen, MITRE Haldun Hadimioglu, Polytechnic U Niraj Jha, Princeton Alexander Khitun, UC Los Angeles Yusuf Leblebici, EPFL Meyya Meyyappan, NASA Ames Kaushik Roy, Purdue U Alberto Sangiovanni-Vincentelli, UC Berkeley Sandeep Shukla, Virginia Tech Kang Wang, UC Los Angeles Kaijie Wu, UIC ======================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To manage your subscription, go to "Subscriber's corner" on http://listserv.acm.org/ - you need to login using the email address where this newsletter is delivered. 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