| Wednesday, June 7 |
| 12:00 - 1:00 : Lunch |
| 1:00 - 3:00 : Synthesis chair: Michel Berkelaar |
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Factor Cuts
Satrajit Chatterjee, Alan Mishchenko, and Robert Brayton |
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Integrated Logic Synthesis Using Simulated Annealing
Petra Farm, Elena Dubrova, and Andreas Kuehlmann |
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Scalable Logic Synthesis using a Simple Circuit Structure
Alan Mishchenko and Robert Brayton |
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Generalized Buffering of PTL Logic Stages using Boolean Division and Don't Cares
Rajesh Garg and Sunil P. Khatri |
| 3:00 - 3:15 : Two-Minute Poster Presentations |
| 3:15 - 4:00 : Poster Session 1 |
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Efficient Techniques for Large BDDs
Kazuya Shinozuka |
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Boolean Function Minimization: The Information Theoretic Approach
Javad Safaei and Hamid Beigy |
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Stochastic Programming Based Optimization Framework in Presence of Variability
Vishal Khandelwal and Ankur Srivastava |
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Performance Analysis of the Asynchronous Nonlinear Pipeline using the Max-Plus Algebra
Jian Ruan, Lei Wang, Zhiying Wang, and Kui Dai |
|
An Approximate Method by Queuing Network Modeling for Performance Evaluation of Asynchronous Pipeline Rings
Lei Wang, Zhi-ying Wang, and Kui Dai |
|
A Low Power Overhead Bus Coding Technique for Minimizing Inductive Crosstalk in VLSI Interconnects
K. S. Sainarayanan, J. V. R. Ravindra, and M. B. Srinivas |
| 4:00 - 5:30 : Physical Issues chair: Christoph Albrecht |
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Design and Analysis of ``Tree + Local Meshes'' Clock Architecture
Gustavo R. Wilke and Rajeev Murgai |
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An Improved Sliding Window Scheme for Clock Mesh Analysis
Subodh M. Reddy and Rajeev Murgai |
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Keeping Physical Synthesis Safe and Sound
Kai-hui Chang, Igor L. Markov, and Valeria Bertacco |
| 5:30 - 7:00 : IWLS Programming Challenge chair: Christoph Albrecht, Florian Krohm, Bob Brayton, and Valavan Manohararajah |
|
Introduction to the OA Gear Func and Aig package
Aaron Hurst |
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State-dependent Leakage Minimization in OpenAccess
Donald Chai |
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Fast Simulation and Equivalence Checking Using OAGear
Kai-hui Chang, David A. Papa, Igor L. Markov, and Valeria Bertacco |
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Graph Optimization by Simulated Annealing
Petra Farm |
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SAT Sweeping with Local Observability Don't-Cares
Qi Zhu and Nathan Kitchen |
| 7:00 - 9:00 : Dinner |
| Thursday, June 8 |
| 7:30 - 8:30 : Breakfast |
| 8:30 - 10:00 : High-Level Synthesis chair: Marc Riedel |
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A Design Method of Address Generators Using Hash Memories
Tsutomu Sasao |
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Optimizing Fixed-Size Bit-Vector Arithmetic using Finite Ring Algebra
Sivaram Gopalakrishnan, Priyank Kalla, and Florian Enescu |
|
Protocol Wrapper Generation from Statement Based Specification
Yuji Ishikawa, Shota Watanabe, Kenshu Seto, and Masahiro Fujita |
| 10:00 - 10:15 : Two-Minute Poster Presentations |
| 10:15 - 11:00 : Poster Session 2 |
|
A Fully Multiplexer-based Implementation of Redundant Number System
Sreehari Veeramachaneni, Pradeep Yarlagadda, and M. B. Srinivas |
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Fast CMOS Logic Style Using Minimum Transistor Stack for Pull-up and Pull-down Networks
Felipe R. Schneider, Renato P. Ribas, and Andre I. Reis |
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BDDs and transistor networks with minimum pull-up/pull-down chains
Leomar S. da Rosa Junior, Felipe S. Marques, Tiago M. G. Cardoso, Renato P. Ribas, and Andre I. Reis |
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On prefix graph generation algorithm for binary addition under area-delay trade-off
Taeko Matsunaga and Yusuke Matsunaga |
|
Analysis of Maximum Switching Activities in Sequential Circuits for Power Supply Integrity Validation
Hiroyuki Higuchi |
|
Automatic Protocol Transducer Synthesis aiming at facilitating IP-Reuse
Shota Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, and Masahiro Fujita |
| 11:00 - 1:00 : Invited Session: New Directions for Logic Synthesis chair: Marc Riedel |
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Engineering New Molecules for Programming Complex Cellular Systems
Christina Smolke, Caltech |
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Frequent Subgraph Mining Across Massive Biological Networks for Functional Discovery
Jasmine Zhou, USC |
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Synthetically Modified Structural Proteins: Self-Assembling Building Blocks for Nanoscale Materials
Matt Francis, U. C. Berkeley |
| 1:00 - 2:30 : Lunch and Planning for IWLS 2007 |
| 2:30 - 5:30 : Social Activity: Hiking Trip |
| 5:30 - 8:00 : Dinner |
| Friday, June 9 |
| 7:30 - 8:30 : Breakfast |
| 8:30 - 10:00 : Verification 1 chair: Mukul Prasad |
|
Inductively Finding a Reachable State Space Over-Approximation
Michael L. Case, Alan Mishchenko, and Robert K. Brayton |
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Improvements to Combinational Equivalence Checking
Alan Mishchenko, Satrajit Chatterjee, Robert Brayton, and Niklas Een |
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Advances and Insights into Parallel SAT Solving
Stephen Plaza, Ian Kountanis, Zaher Andraus, Valeria Bertacco, and Trevor Mudge |
| 10:00 - 10:15 : Two-Minute Poster Presentations |
| 10:15 - 11:00 : Poster Session 3 |
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Design of a Reversible PLD Architecture
Jae-Jin Lee and Gi-Yong Song |
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Reversible Logic Implementation of BCD Subtractor in IEEE 754r Format
Himanshu Thapliyal and M. B. Srinivas |
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Synthesis of a Reversible Bit-Serial GF(2m) Systolic multiplier using a Novel Reversible Gate
R. V. Kamala and M. B. Srinivas |
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Design of Asynchronous Circuits on Top of Synchronous FPGAs
Renato U. Mocho, Giovani H. Sartori, Renato P. Ribas, and Andre I. Reis |
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On Automatic Synthesis of Data Dependent Micropipelines
Alexander Smirnov, Mark Karpovsky, and Alexander Taubin |
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A Compositional Approach to Symmetry Detection in Circuits
Donald Chai and Andreas Kuehlmann |
| 11:00 - 12:30 : Variability chair: Andreas Kuehlmann |
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Variability Driven Gate Sizing for Binning Yield Optimization
Azadeh Davoodi and Ankur Srivastava |
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Latch-Based Design under Process Variation
Aaron P. Hurst and Robert K. Brayton |
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Efficient and Accurate Statistical Timing Analysis for Non-Linear, Non-Gaussian Variability With Incremental Attributes
Ashish Dobhal, Vishal Khandelwal, and Ankur Srivastava |
| 12:30 - 1:30 : Lunch |
| 1:30 - 3:00 : Verification 2 chair: Michael Theobald |
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Design Error Detection in System-Level Designs by Dependence Analysis and Formal Checker
Daisuke Ando, Tasuku Nishihara, Shunsuke Sasaki, Takeshi Matsumoto, and Masahiro Fujita |
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Verification after Synthesis
Alan Mishchenko and Robert Brayton |
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Improved Threshold Voltage Assignment via Combinatorial Implementation Selection
Soheil Ghiasi |