ISPD 2005 TABLE OF CONTENTS

Sessions: [Welcome & Keynote Address] [1] [2] [3] [Keynote Address] [4] [5] [6] [7] [8] [9] [10]

Welcome & Keynote Address

The Death of Logic Synthesis [p. 1] Slides
R. Madhavan (Magma Design Automation, Inc.)

Session 1: Routing Techniques

Chair: R. Nijssen (Magma Design Automation, Inc.)
Slides A Diagnostic Method for Detecting and Assessing the Impact of Physical Design Optimizations on Routing [p. 2]
R. Lembach, R. A. Arce-Nazario, D. Eisenmenger, C. Wood (IBM Corporation)

Slides An Efficient Tile-Based ECO Router with Routing Graph Reduction and Enhanced Global Routing Flow [p. 7]
J.-Y. Li (Taiwan Semiconductor Manufacturing Company Ltd.), Y.-L. Li (National Chaio-Tung University)

Slides Routing of Analog Busses with Parasitic Symmetry [p. 14]
L. Schreiner, M. Olbrich, E. Barke (The University of Hannover), V. Meyer zu Bexten (Atmel Germany GmbH)

Slides Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment [p. 20]
D. Wu, J. Hu, R. Mahapatra (Texas A&M University)

Slides Fast and Accurate Rectilinear Steiner Minimal Tree Algorithm for VLSI Design [p. 28]
C. Chu (Iowa State University), Y.-C. Wong (Rio Design Automation)

Slides A Global Routing Method for 2-Layer Ball Grid Array Packages [p. 36]
Y. Kubo (The University of Kitakyushu), A. Takahashi (Tokyo Institute of Technology)

Session 2: Geometric Programming and Clocks

Chair: A. B. Kahng (University of California at San Diego)
Slides Geometric Programming for Circuit Optimization [p. 44]
S. P. Boyd, S. J. Kim (Stanford University)

Slides Delay Insertion Method in Clock Skew Scheduling [p. 47]
B. Taskin, I. S. Kourtev (The University of Pittsburgh)

Slides Improved Algorithms for Link-Based Non-Tree Clock Networks for Skew Variability Reduction [p. 55]
A. Rajaram, D. Z. Pan (The University of Texas at Austin), J. Hu (Texas A&M University)

Session 3: Power, Buffering and Open Source

Chair: C. Chen (National Taiwan University)
Slides Effects of On-Chip Inductance on Power Distribution Grid [p. 63]
A. Muramatsu (Kyoto University), M. Hashimoto (Osaka University) H. Onodera (Kyoto University),

Slides A Fast Algorithm for Power Grid Design [p. 70]
J. Singh, S. S. Sapatnekar (The University of Minnesota)

Slides Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation [p. 78]
L. He (University of California at Los Angeles), A. Kahng (University of California at San Diego & Blaze DFM, Inc.), K. H. Tam, J. Xiong (The University of California at Los Angeles)

Slides An Efficient Surface-Based Low-Power Buffer Insertion Algorithm [p. 86]
R. R. Rao, D. Blaauw, D. Sylvester (The University of Michigan), C. J. Alpert, S. Nassif (IBM Corporation)

Slides Early Research Experience With OpenAccess Gear: An Open Source Design Development Environment for Physical Design [p. 94]
Z. Xiu (Carnegie Mellon University), D. A. Papa (The University of Michigan), P. Chong, C. Albrecht, A. Kuehlmann (Cadence Bekeley Laboratories), R. A. Rutenbar (Carnegie Mellon University), I. L. Markov (The University of Michigan)

Keynote Address (Dinner Speaker)

Slides A New Era for CAD [p. 101]
G. Smith (Gartner Dataquest)

Session 4: Keynote and Tutorial on the History and Future of Physical Design

Chair: D. Kirkpatrick (Intel Corporation)
Keynote Address: Challenges of Analog/Mixed-Signal SoC Design and Verification [p. 102]
J.-H. Chern (Mentor Graphics Corporation)

Tutorial on DFM for Physical Design [p. 103] Slides
A. Strojwas (Carnegie Mellon University and PDF Solutions)

Session 5: Floorplanning

Chair: J. Cong (University of California at Los Angeles)
Slides Modern Floorplanning Based on Fast Simulated Annealing [p. 104]
T.-C. Chen, Y.-W. Chang (National Taiwan University)

Slides Multi-Bend Bus Driven Floorplanning [p. 113]
J. H. Y. Law, E. F. Y. Young (The Chinese University of Hong Kong)

Slides Floorplan Assisted Data Rate Enhancement through Wire Pipelining: A Real Assessment [p. 121]
M. R. Casu (Politecnico di Torino), L. Macchiarulo (The University of Hawaii at Manoa)

Slides Are Floorplan Representations Important in Digital Design? [p. 129]
H. H. Chan (The University of Michigan), S. N. Adya (Synplicity Inc.), I. L. Markov (The University of Michigan)

Session 6: Technology Mapping

Chair: X. Yang (Synplicity Inc.)
Slides An Efficient Technology Mapping Algorithm Targeting Routing Congestion under Delay Constraints [p. 137]
R. S. Shelar (Intel Corporation), P. Saxena (Synopsys Inc.), X. Wang (Intel Corporation), S. S. Sapatnekar (The University of Minnesota)

Slides Wire Length Prediction-based Technology Mapping and Fanout Optimization [p. 145]
Q. Liu, M. Marek-Sadowska (University of California at Santa Barbara)

Slides Mapping Algorithm for Large-scale Field Programmable Analog Array [p. 152]
F. Baskaya, S. Reddy, S. K. Lim, T. Hall, D. V. Anderson (Georgia Institute of Technology)

Session 7: Advanced Techniques and Technologies

Chair: M. Marek-Sadowska (University of California at Santa Barbara)
Slides Fast Interval-Valued Statistical Interconnect Modeling and Reduction [p. 159]
J. D. Ma, R. A. Rutenbar (Carnegie Mellon University)

Slides Thermal Via Placement in 3D Ics [p. 167]
B. Goplen, S. Sapatnekar (The University of Minnesota)

Slides Technology Migration Technique for Designs with Strong RET-driven Layout Restrictions [p. 175]
X. Yuan, K. W. McCullen (IBM Corporation), F.-L. Heng (IBM T.J. Watson Research Center), R. F. Walker, J. Hibbeler, R. J. Allen, R. R. Narayan (IBM Corporation)

Session 8: Physical Synthesis

Chair: P. H. Madden (The State University of New York & Kitakyushu University)
Invited Talk: Insights and Perspectives on Physical Synthesis [p. 183]
S. Krishnamoorthy (Sierra Design Automation)

Invited Talk: Physical Design Tools for Hierarchy [p. 184]
P. Villarrubia (IBM Corporation)

Session 9: Placement

Chair: I. Markov (The University of Michigan)
Slides .wmv Multilevel Generalized Force-directed Method for Circuit Placement [p. 185]
T. Chan, J. Cong, K. Sze (University of California at Los Angeles)

Slides Unified Quadratic Programming Approach for Mixed Mode Placement [p. 193]
B. Yao, H. Chen, C.-K. Cheng (University of California at San Diego), N.-C. Chou, L.-T. Liu, P. Suaris (Mentor Graphics Corporation)

Slides A Semi-Persistent Clustering Technique for VLSI Circuit Placement [p. 200]
C. Alpert (IBM Corporation), A. Kahng (University of California at San Diego), G.-J. Nam (IBM Corporation), S. Reda (University of California at San Diego), P. Villarrubia (IBM Corporation)

Slides Evaluation of Placer Suboptimality Via Zero-Change Netlist Transformations [p. 208]
A. B. Kahng, S. Reda (University of California at San Diego)

Session 10: 2005 ISPD Placement Contest

Chair: G.-J. Nam (IBM Corporation)
Slides The ISPD2005 Placement Contest and Benchmark Suite [p. 216]
G.-J. Nam, C. J. Alpert, P. Villarubbia, B. Winter, M. Yildiz (IBM Corporation)

Slides FastPlace: An Analytical Placer for Mixed-Mode Designs [p. 221]
N. Viswanathan, M. Pan, C. C.-N. Chu (Iowa State University)

Slides Capo: Robust and Scalable Open-Source Min-Cut Floorplacer [p. 224]
J. A. Roy, D. A. Papa (The University of Michigan), S. N. Adya (Synplicity Inc.), H. H. Chan, A. N. Ng, J. F. Lu, I. L. Markov (The University of Michigan)

Slides mPL6: A Robust Multilevel Mixed-Size Placement Engine [p. 227]
T. F. Chan, J. Cong, M. Romesis, J. R. Shinneri, K. Sze, M. Xie (University of California at Los Angeles)

Slides Recursive Bisection Placement: Feng Shui 5.0 Implementation Details [p. 230]
A. R. Agnihorti (The State University of New York at Binghamton), S. Ono, P. H. Madden (The State University of New York at Binghamton & The University of Kitakyushu)

Slides APlace: A General Analytic Placement Framework [p. 233]
A. B. Kahng, S. Reda, Q. Wang (University of California at San Diego)

Slides NTUplace: A Ratio Partitioning Based Placement Algorithm for Large-Scale Mixed-Size Designs [p. 236]
T.-C. Chen, T.-C. Hsu, Z.-W. Jiang, Y.-W. Chang (National Taiwan University)

Slides mFAR: Fixed-Points-Addition-Based VLSI Placement Algorithm [p. 239]
B. Hu (Flexlogics Inc.), Y. Zeng, M. Marek-Sadowska (University of California at Santa Barbara)

Kraftwerk - A Versatile Placement Approach [p. 242]
B. Obermeier, H. Ranke, F. M. Johannes (Technical University of Munich),

Slides Dragon2005: Large-Scale Mixed-size Placement Tool [p. 245]
T. Taghavi (University of California at Los Angeles), X. Yang (Synplicity Inc.), B.-K. Choi (Magma Design Automation, Inc.), M. Wang (Blaze-DFM, Inc.), M. Sarrafzadeh (University of California at Los Angeles),