Behavioral Synthesis from an Extensible Object Oriented Language In the last decade, logic synthesis has changed the way that the digital circuits are designed. Unfortunately, behavioral synthesis, naturally conceived as its next step, still lacks industrial acceptance despite the intensive research invested. This dissertation identifies the technical obstacles that keep conventional behavioral synthesis systems from wider practical use, and develop techniques to address issues such as scalability to system level design, scalability to emerging architectural alternatives, and scalability to deep submicron technology. Traditionally, behavioral description is specified in hardware description languages such as VHDL or Verilog, or special purpose languages such as Silage. Unfortunately, such languages cannot scale to handle system level design, which is heterogeneous in nature. Given this background, the first part of the dissertation focuses on the language issues by designing a system level design language (SLDL) called OpenJ, which can not only serve as behavioral specification, but also cater the requirements for system level specification. After surveying the existing approaches in SLDL design, a layered, extensible language architecture is proposed in contrasts to the traditional monolithic language architecture, to resolve the heterogeneity/simplicity dilemma inherent in SLDL design. OpenJ consists of the kernel layer, which is essentially the Java language reengineered to be simple, modular and polymorphic; and the open layer, which exports parameterizable language constructs; and the domain layer which precisely captures the computational models essential for embedded systems. I argue that OpenJ behavioral specification is familiar, as object oriented design paradigm is well-established for system designers; and convenient, as the the redundant, yet error-prone procedure of translating system level specification to behavioral specification in HDL is eliminated; and powerful, as OpenJ offers new capabilities, such as reusability and memory programmability, to hardware design. Traditionally, behavioral synthesis synthesizes behavioral description into an ASIC architecture consisting of a controller and datapath. Unfortunately, the techniques developed in the past does not scale to handle the emerging architectural alternatives, such as application specific instruction processor (ASIP) and reconfigurable hardware architectures. In the second part of the dissertation, a formal framework of architectural models, which abstracts away the apparent differences of these architectures are developed. This framework hence enables the unified treatment of code generation and behavioral synthesis, a dichotomy otherwise. A retargettable compiler infrastructure is developed in the OpenJ platform based on this philosophy. Traditionally, behavioral synthesis are developed with physical level design completely decoupled. Unfortunately, these techniques does not scale to deep submicron technology where interconnect delay becomes dominant. The difficulty stems from the phase coupling problem inherent between scheduling and physical design. In the third part of the dissertation, the theoretical framework for a new concept of scheduling called soft scheduling is established. In contrasts to the traditional schedulers referred as hard schedulers, soft schedulers make soft decisions at a time, or decisions that can be adjusted later. A specific soft scheduling formulation, called threaded schedule, under which a linear, optimal (in the sense of online optimality) algorithm is guaranteed, is then developed. With soft scheduling, a datapath netlist can be generated. Hence, placement and routing can be subsequently performed, before the before the controller is finialized.