Sponsored &
Supported
By
Chair
Robert Jones (Intel)
SIGDA Liaison
Soha Hassoun (Tufts)
Contact E-mail
daforum@sigda.org
Program Committee
- Fadi Aloul (American U. Dubai)
- Clark Barrett (New York U.)
- Naehyuck Chang (Seoul National U.)
- Pasquale Cocchini (Intel)
- Katherine Compton (Wisconsin)
- Sumit Gupta (UC Irvine)
- Ian Harris (UC Irvine)
- Jiang Hu (Texas A&M)
- Srinivas Katkoori (U. South Florida)
- Victor Kravets (IBM)
- Prabhakar Kudva (IBM)
- Guy Lemieux (U. British Columbia)
- John Lillis (U. Illinois at Chicago)
- Yung-Hsiang Lu (Purdue)
- Ion Mandoiu (Connecticut)
- Radu Marculescu (Carnegie Mellon)
- Janet Meiling (U. of Arizona)
- Kartik Mohanram (Rice)
- Roberto Passerone (Cadence)
- Darshan Patra (Intel)
- Sule Ozev (Duke)
- Mike Wirthlin (Brigham Young)
- Jin Yang (Intel)
- Dirk Ziegenbein (Bosch)
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Call for Participation
The SIGDA PhD Forum at DAC will be held on Tuesday, June 8, 2004
from 6:30-8:00 p.m. at the Sails Pavilion of the San Diego
Convention Center.
In a change from previous years, the forum will be held in a large
hall between the exhibits and the technical conference rooms.
Additionally, we have asked the students to leave their posters up
through Thursday morning.
This year we had a record 136 submissions. A total of 44 students
were invited to attend; 36 will present their dissertation research
at the forum.
Helpful links:
Program
Interconnect and timing analysis
Timing Analysis of High-Performance Integrated Circuits
Chirayu Amin,
Northwestern University
Buffer Planning for Global Wires With and Without Statistical Process Variations
Giuseppe Garcea,
Delft University of Technology (The Netherlands)
Accurate Interconnect Modeling and Efficient Transient
Simulation of VLSI Interconnect Structures
Qinwei Xu,
University of Michigan
VLSI Interconnect Synthesis
and Prediction
Bao Liu, UC San Diego
Skin and Proximity Effects
Modeling
Shizhong Mei, Northwestern University
Physical design
Multi-objective Circuit Partitioning for Cutsize
and Path-Based Delay Minimization
Cristinel
Ababei,
University of Minnesota
Analog/RF Layout Automation: Layout Retargeting
via Symbolic Template
Nuttorn Jangkrajarng, University of Washington
Electromigration-Aware Design of Integrated
Circuits
Goeran Jerke, Dresden University of Technology (Germany)
Congestion Estimation in Modern VLSI
Floorplanning and Placement Design
Zion Shen, Iowa State University
On-chip synthesis and optimization
Analysis and Minimization of Leakage Current
Dongwoo Lee,
University of Michigan, Ann Arbor
Efficient and Scalable
Algorithms for the Binate Covering Problem
Xiao Yu Li, North Carolina State University
Energy Minimization of Pipelined Processor Using a Low
Voltage Pipelined Cache
Jun Cheol Park,
Georgia Institute of Technology
Automated Synthesis of Analog and RF Circuits using Symbolic
Performance Models
Mukesh Ranjan,
University of Cincinnati
Cyclic Combinational Circuits
Marc Riedel,
California Institute of Technology
System-level analysis and synthesis
Power Estimation and Power Optimization Policies for
Processor-Based Systems
Jose L. Ayala,
Technical University of Madrid (Spain)
Resources Balancing: A Technique for Minimization of
Current Surge in Microprocessor
Yiran Chen,
Purdue University
Analysis and Verification of Real-Time Embedded Systems
Luis Alejandro Cortes,
Linköping University (Sweden)
eBlocks: Embedded Systems Building Blocks
Susan Cotterell,
University of California, Riverside
Customizing Clustered VLIW Architectures with Focus on
Interconnects and Functional Units
Anup Gangwar,
Indian Institute of Technology Delhi (India)
Providing QoS with Reduced Energy Consumption via
Real-Time Voltage Scaling on Embedded Systems
Shaoxiong Hua,
University of Maryland
System-Level Performance Analysis for Complex Embedded
Applications
Marek
Jersak,
Technical University of Braunschweig (Germany)
Low-Power Design Technique at Circuit and Microarchitectural
Boundary
Hai Li,
Purdue University
NoC Synthesis Flow for
Customized Domain Specific MPSoCs
Srinivasan Murali, Stanford University
Efficient Cosynthesis from Extended Dataflow Graphs for
Multimedia Applications
Hyunok Oh,
Seoul National University (South Korea)
Energy-Delay Efficient Customizable Data Memory Subsystems for
Embedded Media Processing
Anand Ramachandran,
The University of Texas at Austin
Instruction-set Extension
and Code Generation for Application-specific Processors
Kenshu Seto, University of Tokyo (Japan)
Flywheel: Enabling Performance Increase and Power
Efficiency by Using Multiple Speed Pipelines
Emil Talpes, Carnegie Mellon University
Software Design Flow for
Heterogeneous and Highly Parallel System on Chip
Mohamed Wassim, Youssef INP Grenoble (France)
Design Techniques for Ambient Intelligent Systems
Nick Zamora,
Carnegie Mellon University
Testing
Integrated Circuit Outlier Identification With Multiple Parameter
Correlation
Sagar Sabade,
Texas A&M University
Verification
Heuristic and Exact Optimization of Reduced Ordered
Binary Decision Diagrams (BDDs)
Ruediger Ebendt,
University of Bremen (Germany)
Specification-Driven Validation of Programmable Embedded Systems
Prabhat Mishra,
University of California, Irvine
Using Functional Verification to Evaluate the Accuracy of
Model Checking Applied to Embedded Systems: Theory and Application
Graziano
Pravadelli,
University of Verona (Italy)
Formalizing Shared Memory Consistency Models for
Program Analysis
Yue Yang,
University of Utah
FPGAs, Reconfigurable Systems
Circuits, Fabrics and CAD Algorithms for Power-Efficient FPGAs
Fei Li, UCLA
Place and Route Techniques for FPGA
Architecture Advancement
Akshay Sharma, University of Washington
Automated Floating-point to Fixed-point
Conversion
Changchun Shi, UC Berkeley
Contact Information
For further information, please send e-mail to:
daforum@sigda.org
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