Sponsored & Supported By SIGDA DAC Contact daforum@sigda.org SIGDA Liaison Soha Hassoun Sister forums SIGDA Design Automation Summer School Organizers Soha Hassoun (Tufts) Diana Marculescu (CMU) Robert Jones (Intel) Darko Kirovski (MSR) Chris Chu (ISU) Yehia Massoud (Synopsys) Michael Wirthlin (BYU) Mokhtar Hirech (Synopsys) Archive of Past Forums '02 '01 '00 '99 '98

Conference Program Analog and Mixed-Signal Design Pedram Mohseni - University of Michigan, Ann Arbor Advisor: Professor Khalil Najafi Paper: A Wireless FM Multi-Channel Microsystem for Biomedical Neural Recording Applications Glenn Wolfe - University of Cincinnati Advisor: Dr. Ranga Vemuri Paper: Extraction and Use of Neural Network Models in Automated Synthesis of Operational Amplifiers Maysam Ghovanloo - University of Michigan, Ann Arbor Advisor: Prof. Khalil Najafi Paper: Towards A Button-Sized 1024-Site Wireless Cortical Microstimulating Array Xiaoling Huang - University of Arkansas Advisor: H. Alan Mantooth Paper: Modeling Nonlinear Dynamics in Analog Circuits Via Root Localization Interconnect Analysis and Physical Design Syed Alam - Massachusetts Institute of Technology Advisor: Donald E. Troxel and Carl V. Thompson Paper: Reliability Computer-Aided Design Tool for 3-D Integrated Circuits Satrajit Gupta - Carnegie Mellon University Advisor: Larry Pileggi Paper: Hierarchical Interconnect Circuit Models Andrey Mezhiba - University of Rochester Advisor: Eby G. Friedman Paper: Inductive Properties of High-Performance Power Distribution Grids Yu-Chun Ma - Tsinghua University, Beijing, China Advisor: Xianlong Hong Paper: VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation Jingyu Xu - Tsinghua University, Beijing, China Advisor: Xianlong Hong Paper: A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design Hui Xu - Carnegie Mellon University Advisor: Rob Rutenbar Paper: sub-SAT: A Formulation for Relaxed Boolean Satisfiabilty with Applications in Routing Parivallal Kannan - University of Texas at Dallas Advisor: Dr. Dinesh Bhatia Paper: On Metrics for Comparing Routability Estimation Methods for FPGAs Logic Synthesis Aseem Agarwal - University of Michigan, Ann Arbor Advisor: David Blaauw Paper: Statistical Timing Analysis Rupesh Shelar - University of Minnesota Advisor: Sachin S. Sapatnekar Paper: Synthesis techniques for deep sub-micron technologies Power Estimation and Low Power Design Qiang Chen - Georgia Institute of Technology Advisor: James D. Meindl Paper: A Comprehensive Analytical Subthreshold Swing Model for Double-Gate MOSFETs Kyu-won Choi - Georgia Institute of Technology Advisor: Dr. Abhijit Chatterjee Paper: Hierarchical Supply Voltage, Threshold Voltage, Gate Size, and Interconnect Width Co-optimization for Ultra-Low Power CMOS VLSI in Nanometer Technologies Jose L Rossello - Balearic Islands University, Palma de Mallorca, Spain Advisor: Jaume Segura Paper: Charge-Based Analytical Model for the Evaluation of Power Consumption in Submicron CMOS Buffers Ansgar Stammermann - OFFIS Research Institute, Oldenburg, Germany Advisor: Wolfgang Nebel Paper: System Level Optimization and Design Space Exploration for Low Power Murali Jayapala - ESAT/ACCA, K.U.Leuven, Heverlee, Belgium Advisor: Francky Catthoor Paper: A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors Ying Zhang - Duke University Advisor: Dr. Krishnendu Chakrabarty Paper: Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems Piyush Mishra - Polytechnic University, Brooklyn, New York Advisor: Prof. Ramesh Karri Paper: Optimizing the Energy Consumed by SecureWireless Sessions – Wireless Transport Layer Security Case Study System Level Design Jong-eun Lee - Seoul National University Advisor: Kiyoung Choi Paper: Efficient Instruction Encoding for Automatic Instruction Set Design of Configurable ASIPs Kyeong Ryu - Georgia Institute of Technology Advisor: Vincent J. Mooney III Paper: Automated Bus Generation for Multiprocessor SoC Design Bilge Akgul - Georgia Institute of Technology Advisor: Vincent Mooney Paper: The System-on-a-Chip Lock Cache Zhong Wang - University of Notre Dame Advisor: Xiaobo Sharon Hu, Edwin H.-M. Sha Paper: Combined Partitioning and Data Padding for Scheduling Multiple Loop Nests Patrick Schaumont - University of California, Los Angeles Advisor: Ingrid Verbauwhede Paper: Domain SpecificTools andMethods forApplication in Security ProcessorDesign Jingcao Hu - Carnegie Mellon University Advisor: Radu Marculescu Paper: Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures Satish Pillai - The University of Texas at Austin Advisor: Margarida F. Jacome Paper: Clustered VLIW Architectures with Predicated Switching Testing Xiao Liu - Virginia Tech. Advisor: Michael S. Hsiao Paper: Techniques to Reduce Data Volume and Application Time for Transition Test Shahin Nazarian - University of Southern California Advisor: Professors M.A. Breuer and S.K. Gupta Paper: XIDEN: Crosstalk Target Identification Framework Liang-Chi Chen - University of Southern California Advisor: Melvin A. Breuer Paper: A New Gate Delay Model for Simultaneous Switching and Its Applications Chunsheng Liu - Duke University Advisor: Krishnendu Chakrabarty Paper: A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis Bartomeu Alorda - Balearic Islands University, Palma de Mallorca, Spain Advisor: Jaume Segura Paper: Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs Kaijie Wu - Polytechnic University, Brooklyn, New York Advisor: Ramesh Karri Paper: Algorithm Level Recomputing Using Allocation Diversity: A Register Transfer Level Time Redundancy-Based CED Technique Krishna Chakravadhanula - The University of Texas at Austin Advisor: Dr. Nur Touba Paper: Test Vector Encoding Using LFSR Reseeding Chee-Kian Ong - University of California, Santa Barbara Advisor: Prof. Kwang-Ting (Tim) Cheng Paper: Delta-sigma Modulator Based Mixed-signal BIST Architecture for SoC Amir Attarha - University of Texas, Dallas Advisor: Dr. Mehrdad Nourani Paper: Testing Interconnects for Noise and Skew in Gigahertz SoCs Verification Chao Wang - University of Colorado Advisor: Gary D. Hachtel, Fabio Somenzi Paper: Sharp Disjunctive Decomposition for Language Emptiness Checking Tankut Akgul - Georgia Institute of Technology Advisor: Vincent Mooney Paper: Instructionlevel Reverse Execution for Debugging Xiao Li - North Carolina State University Advisor: Matthias F. Stallmann Paper: The Role of a Skeptic Agent in Testing and Benchmarking of SAT Algorithms Valeria Bertacco - Stanford University Advisor: Kunle Olukotun / David Dill Paper: Efficient State Representation for Symbolic Simulation Marco Pena - Technical University of Catalonia, Barcelona, Spain Advisor: Paper: A case study for the verification of complex timed circuits: IPCMOS FPGA and Reconfigurable Computing Heidi Ziegler - University of Southern California Advisor: Mary Hall Paper: Coarse-Grain Pipelining on Multiple FPGA Architectures Fernanda Lima - Universidade Federal do Rio Grande do Sul, Brazil Advisor: Ricardo Reis Paper: Reducing Pin and Area Overhead in Fault-Tolerant FPGAbased Designs Joonseok Park - University of Southern California Advisor: Dr. Pedro C. Diniz Paper: Synthesis of Pipelined Memory Access Controllers for Streamed Data Applications on FPGA-based Computing Engines Emerging Technologies Matthew Ziegler - University of Virginia Advisor: Mircea Stan Paper: A Case for CMOS/nano Co-design