12th Annual ACM/SIGDA Ph.D. Forum at DAC

Sponsored By SIGDA DAC Supported By Intel IBM Research NEC Research STMicroelectronics Synopsys Cadence Altera Xilinx Magma Design Automation Synplicity TPC Chair Jin Yang   Intel, USA TPC Co-Chair Eli Bozorgzadeh   UCI, USA Publicity Chair Alex K. Jones   University of Pittsburgh Finance Chair Eli Bozorgzadeh   UCI, USA Past Chair Tony Givargis   UCI, USA SIGDA Liaison Robert B. Jones   Intel, USA Program Committee Cristinel Ababei   Magma, USA Fadi Aloul   Amer. Univ. Sharjah, UAE Iris Bahar   Brown Univ., USA Eli Bozorgzadeh   UCI, USA Samarjit Chakraborty   Natl. Univ., Singapore Naehyuck Chang   Seoul Natl. Univ., Korea Deming Chen   UIUC, USA Vivek Chickermane   Cadence, USA Philip Chong   Cadence, USA Pasquale Cocchini   Intel, USA Katherine Compton   Univ. Wisconsin, USA Adam Donlin   Xilinx, USA Peter Feldmann   IBM, USA Ian Harris   UC Irvine, USA Jiang Hu   Texas A&M Univ., USA Alex Jones   Univ. of Pittsburgh, USA Prabhakar Kudva   IBM, USA Marcello Lajolo   NEC labs , USA Peng Li   Texas A&M Univ., USA Roman Lysecky   Univ. of Arizona, USA Seda Memik   Northwestern University, USA Subhasish Mitra   Stanford Univ., USA Kartik Mohanram   Rice Univ., USA Gi-Joon Nam   IBM, USA Davide Pandini   ST Micro, Italy Carl Pixley   Synopsys, USA Donatella Sciuto   Politechnico di Milano, Italy Youngsoo Shin   KAIST, Korea Chao Wang   NEC Labs, USA Jianping (Jane) Xu   Intel Corp Mohammad Tehranipoor   University of Connecticut, USA Zhou Li   IBM, USA Tony Givargis   UC Irvine, USA Deshanand Singh   Altera, USA Sriram Vangal   Intel Corp Jesse Bingham   Intel Corp Marc Geilen   Eindhoven Univ. Tech., The Netherlands Sister Forums SIGDA CADathlon Archive of Past Forums 2007   2006   2005   2004   2003 2002   2001   2000   1999   1998

An announcement for the 2009 Ph.D. Forum at DAC will be coming soon!

The Ph.D. Forum at the Design Automation Conference is a poster session hosted by SIGDA for Ph.D. students to present and discuss their dissertation research with people in the EDA community. It is one of the premier forums for Ph.D. students in design automation to get feedback on their research and for industry to see academic work in progress. 400+ people attended each of the last three forums.

Participation in the forum is competitive, with an acceptance rate around 30%. Limited funds will be available for travel assistance, based on the financial need.

The forum is open to all members of the design automation community and is free-of-charge. It is co-located with DAC to attract the large DAC audience, but DAC registration is not required in order to attend this event.

Accepted Submissions

Track 1: System-level design, synthesis and optimization, including NOC and SOC

Source Re-coding to Create MPSoC Models for System-Synthesis
Pramod Chandraiah, University of California, Irvine (USA)

Algorithm-Architecture Co-Design for Energy Efficient Software Defined Radio Baseband
Min Li, NES, IMEC (Belgium)

Energy Optimization of Advanced Flash Memory Subsystems for Portable Appliances
Yongsoo Joo, Seoul National University (South Korea)

Predictable Mapping of Streaming Applications on Multiprocessors
Sander Stuijk, Eindhoven University of Technology (Netherlands)

Interactive Performance Debugging of Real-Time Embedded Systems
Unmesh Dutta Bordoloi, National University of Singapore (Singapore)

Systematic and Automated Multi-processor System Design, Programming, and Implementation
Hristo Nikolov, Leiden University (Netherlands)

Analysis and Optimization of Software for NAND Flash in Embedded Systems
Siddharth Choudhuri, University of California, Irvine (USA)

Application Specific Processor Core Construction from C Code
Jelena Trajkovic, University of California, Irvine (USA)

System-Level Analysis and Mitigation of the Performance Impact of Manufacturing Process Variations
Siddharth Garg, Carnegie Mellon University (USA)

Track 2: Logic level synthesis, optimization and physical design (including emerging technologies)

Numerically convex forms and their application in gate-sizing
Sanghamitra Roy, University of Wisconsin-Madison (USA)

Synthesis of Digital Microfluidic Biochips: Modeling, Placement, and Routing
Ping-Hung Yuh, National Taiwan University (Taiwan)

Synthesis and Optimization of Nonzero Clock Skew Circuits
Chun-Hua Cheng, Chung Yuan Christian University (Taiwan)

Gridless Routing Considering Nanometer Electrical Effects
Tai-Chen Chen, National Taiwan University (Taiwan)

Track 3: Power and thermal modeling, analysis, optimization and management

Thermal Aware and Low Power Optimizations for VLSI Synthesis
Min Ni, Northwestern University (USA)

Low Power Signal Processing Circuit and System Design
Yang Liu, Rensselaer Polytechnic Institute (USA)

System Level Design Techniques for Power and Thermal Management on Uni-processor and Chip Multi-processor Architectures
Sushu Zhang, Arizona State University (USA)

Track 4: Timing and noise analysis, including interconnect and RF

Robust and Efficient Finite Point based Gate models with Process Variations
Alex Mitev, University of Arizona (USA)

Algorithmic Techniques for Parasitic Extraction of 3D VLSI Circuits
Yang Yi, Texas A&M University (USA)

Track 5: Verification, testing, pre- and post-silicon validation, failure analysis

Mathematical Methods to Improve Microprocessor Speed Debug
Desta Tadesse, Brown University (USA)

Scaling formal methods towards hierarchical protocols in shared memory processors
Xiaofang Chen, University of Utah (USA)

Delay Fault Testing and Modelling in Multi Voltage Design Systems
Noohul Basheer Zain Ali, University of Southampton (United Kingdom)

Effective Verification Solution For Today’s Microprocessors
Ilya Wagner, University of Michigan at Ann Arbor (USA)

Track 6: Design for resilience and reliability, variability aware design

Lithography Modeling and Optical Proximity Correction for Nanometer Design for Manufacturing
Peng Yu, University of Texas at Austin (USA)

A Cross-Layer, Error-Aware Methodology for Reliable Design of Resource Constrained Embedded Systems
Kyoungwoo Lee, University of California at Irvine (USA)

Design, Analysis, and Test of Logic Circuits under Uncertainty
Smita Krishnaswamy, University of Michigan at Ann Arbor (USA)

Track 7: FPGA and reconfigurable systems

Design Methodology and CAD Tools for Nanometer FPGAs: Optimization for Leakage Power and Variability
Hassan Hassan, University of Waterloo (Canada)

Early planning for placement constraints for achieving Timing closure in FPGA design flow
Love Singhal, University of California at Irvine (USA)

Contact Information

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