Stochastic Performance Analysis of Interconnects in the Presence of Manufacturing Process Variations
Praveen Ghanta
SIGDA Ph.D. Forum at DAC 2006 (Ph.D. Forum 2006)
San Francisco, CA, July 2006
Abstract
Statistical timing and power analysis that are highly important problems in the
sub-100nm regime require variational performance models for the circuit building blocks
like the interconnects and the CMOS gates. In this dissertation, we propose efficient
and accurate methods to develop L2 (mean-square) optimal stochastic voltage, delay,
slew and power models for interconnects, CMOS gates and circuits in the presence of
process and environmental variations. The methods are based on representing the
stochastic response as an orthonormal polynomial series in a Hilbert space of the
process random variables. In case of the interconnects, the voltage response
coefficients are obtained by applying the Galerkin residual error minimization method
to the state-space representation of the interconnects. In case of the CMOS gates, we
use efficient response surface methods (employing SPICE runs) based on interpolation on
quadrature grids to obtain the coefficients of the delay, slew and power models. We
also extend our methods to characterize the voltage drops in power grids and to perform
system-level power analysis in the presence of process and environmental variations.
Further, given any arbitrary covariance function we also demonstrate a numerical method
(based on the Karhunen-Loeve expansion) to efficiently and accurately obtain an
uncorrelated set of random variables that serves as an attractive alternative to
principal component analysis. Our analyses have been exhaustively applied to several
industrial circuits and test cases, and the results show speed-ups of up to two orders
of magnitude over Monte Carlo simulations for comparable accuracy.